SGM822
3-Rail Power Sequencer
with Programmable Timing
GENERAL DESCRIPTION
FEATURES
The SGM822 is an integrated, 3-rail power sequencer.
● Up to 3-Rail Power Sequence Control
It controls the power-up and power-down sequence of
● Low Quiescent Current: 36μA (TYP)
three power supplies by pulling their enable or
● Input Voltage Range: 2.7V to 5.5V
shutdown pins high or low. Staggered start sequence
● Pin-Selected Flag Output Logic
can avoid the impact of latch conditions or large inrush
● Capacitor-Programmable Power-Up/Power-Down
Sequencing Delay
current on system reliability.
This simple sequencer has three open-drain output
flags. When the enable (EN) pin is pulled high, the flags
are successively released from FLAG1 to FLAG3 after
individual
programmable
delay
time.
Then
the
● Available in Green MSOP-8 and UTDFN-1.5×1.5-8L
Packages
APPLICATIONS
connected power supplies power up. When the EN pin
Multivoltage Systems
is pulled low, the flags output low with a reverse
Servers
sequence from FLAG3 to FLAG1 after individual
Networking Systems
programmable
Telecom Equipment
delay
time.
The
delay
time
is
programmed by connecting a capacitor between the
Microprocessor, Microcontroller and FPGA Sequencing
TADJ pin and ground. The logic of the output flags can
Multiple Supply Sequencing
be inverted by the user.
The SGM822 is available in Green MSOP-8 and
UTDFN-1.5×1.5-8L packages. It operates over an
ambient temperature range of -40℃ to +125℃.
TYPICAL SYSTEM APPLICATION
TYPICAL APPLICATION
2.7V to 5.5V Supply
Power Supply
0.1µF
Device 1
VCC
FLAG1
Enable
Enable Input
FLAG2
INV
INV
Device 2
EN
Device 3
FLAG3
EN
SGM822
EN
SGM822
Invert
EN
0.1µF
VCC
CADJ
10nF
TADJ
GND
R1
100kΩ
R2
100kΩ
R3
100kΩ
FLAG1
Flag 1
FLAG2
Flag 2
FLAG3
Flag 3
EN
GND
Figure 2. Typical Application Circuit
Figure 1. Typical System Application
SG Micro Corp
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APRIL 2024 – REV. A.2
3-Rail Power Sequencer
with Programmable Timing
SGM822
PACKAGE/ORDERING INFORMATION
MODEL
PACKAGE
DESCRIPTION
SPECIFIED
TEMPERATURE
RANGE
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MSOP-8
-40℃ to +125℃
SGM822XMS8G/TR
SGM822
XMS8
XXXXX
Tape and Reel, 4000
UTDFN-1.5×1.5-8L
-40℃ to +125℃
SGM822XUDW8G/TR
0NE
XXX
Tape and Reel, 4000
SGM822
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
MSOP-8
XXXXX
Vendor Code
Trace Code
Date Code - Year
UTDFN-1.5×1.5-8L
YYY
XXX
Serial Number
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
VCC, EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND
............................................................................. -0.3V to 6V
Package Thermal Resistance
MSOP-8, θJA ....................................................... 183.3℃/W
MSOP-8, θJB ....................................................... 126.4℃/W
MSOP-8, θJC ......................................................... 84.5℃/W
UTDFN-1.5×1.5-8L, θJA....................................... 149.5℃/W
UTDFN-1.5×1.5-8L, θJB....................................... 105.7℃/W
UTDFN-1.5×1.5-8L, θJC ...................................... 126.4℃/W
Junction Temperature .................................................+150℃
Storage Temperature Range ....................... -65℃ to +150℃
Lead Temperature (Soldering, 10s) ............................+260℃
ESD Susceptibility
HBM ............................................................................. 4000V
CDM ............................................................................ 1000V
RECOMMENDED OPERATING CONDITIONS
VCC to GND .......................................................2.7V to 5.5V
EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND
.................................................................-0.3V to VCC + 0.3V
Operating Junction Temperature Range ...... -40℃ to +125℃
SG Micro Corp
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OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failure to observe proper handling and installation procedures
can cause damage. ESD damage can range from subtle
performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
APRIL 2024
2
3-Rail Power Sequencer
with Programmable Timing
SGM822
PIN CONFIGURATIONS
(TOP VIEW)
VCC
(TOP VIEW)
1
8
FLAG1
EN
2
7
FLAG2
GND
3
6
FLAG3
INV
4
5
TADJ
MSOP-8
VCC
1
8
FLAG1
EN
2
7
FLAG2
GND
3
6
FLAG3
INV 4
5
TADJ
UTDFN-1.5×1.5-8L
PIN DESCRIPTION
PIN
NAME
I/O
FUNCTION
1
VCC
I
Input Supply.
2
EN
I
Precision Enable.
3
GND
–
Ground.
4
INV
I
Output Logic Invert.
5
TADJ
O
Timer Adjustment.
6
FLAG3
O
Open-Drain Output 3.
7
FLAG2
O
Open-Drain Output 2.
8
FLAG1
O
Open-Drain Output 1.
NOTE: I: input; O: output.
SG Micro Corp
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APRIL 2024
3
3-Rail Power Sequencer
with Programmable Timing
SGM822
ELECTRICAL CHARACTERISTICS
(VCC = 3.3V, TJ = -40℃ to +125℃, typical values are measured at TJ = +25℃, unless otherwise noted.)
PARAMETER
Operating Quiescent Current
SYMBOL
IQ
FLAGx Leakage Current
IFLAG
FLAGx Output Voltage Low
VOL
TADJ Source Current
ITADJ_SRC
TADJ Sink Current
CONDITIONS
MIN
TYP
MAX
EN = H
30
55
EN = L
36
65
0.001
0.5
VFLAGx = 3.3V
UNITS
µA
µA
VFLAGx = 6.0V
1.0
IFLAGx = 1.2mA
0.3
V
15
µA
7
11
ITADJ_SNK
7
11
15
µA
High Threshold Level
VHTH
1.1
1.2
1.3
V
Low Threshold Level
VLTH
0.4
0.5
0.6
V
1.10
1.30
1.45
ms
10
Clock Cycles
Clock Cycle
Flag Delay Time
tCLK
9
tD2, tD3, tD5, tD6
EN Pin Threshold
VEN
EN Pin Pull-Up Current
IEN
INV Pin VIH
VIH_INV
INV Pin VIL
VIL_INV
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CADJ = 10nF
tD1, tD4
8
1.1
VEN = 0V
1.2
Clock Cycles
1.3
6.5
V
µA
0.9 × VCC
V
0.1 × VCC
V
APRIL 2024
4
3-Rail Power Sequencer
with Programmable Timing
SGM822
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3V, unless otherwise noted.
Enable Threshold vs. Temperature
1.230
45
1.225
Enable Threshold (V)
Operating Quiescent Current (μA)
Operating Quiescent Current vs. Temperature
50
EN = L
40
35
30
EN = H
25
20
1.220
1.215
1.210
1.205
-50
-25
0
25
50
75
100
125
1.200
150
-50
-25
0
Temperature (℃)
Delay Time vs. Temperature
CADJ = 10nF Nominal
Delay Time (ms)
10.8
10.7
10.6
10.5
-50
-25
0
25
50
75
100
125
45
150
40
35
30
150
EN = H
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
FLAG Voltage vs. Supply Voltage
1
CADJ = 10nF Nominal
10.53
0.8
10.51
0.6
VFLAG (V)
Delay Time (ms)
125
EN = L
Delay Time vs. Supply Voltage
10.49
10.47
10.45
100
50
Temperature (℃)
10.55
75
Operating Quiescent Current vs. Supply Voltage
10.9
10.4
50
55
Operating Quiescent Current (μA)
11.0
25
Temperature (℃)
INV Low, RFLAG = 100kΩ
0.4
0.2
2.5
3
3.5
4
4.5
Supply Voltage (V)
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5
5.5
0
0
0.4
0.8
1.2
1.6
2
Supply Voltage (V)
APRIL 2024
5
3-Rail Power Sequencer
with Programmable Timing
SGM822
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VCC = 3.3V, unless otherwise noted.
FLAG Voltage vs. FLAG Current
0.5
VFLAG (V)
0.4
0.3
VCC = 3.3V
0.2
VCC = 5V
0.1
0
0
1
2
3
4
5
IFLAG (mA)
FUNCTIONAL BLOCK DIAGRAM
VCC
FLAG1
6.5μA
+
EN
tD1
_
tD2
FLAG2
tD3
1.2V
Timing Delay
Generation
tD4
Sequence
Control
tD5
TADJ
Clock
tD6
FLAG3
INV
GND
Figure 3. SGM822 Block Diagram
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APRIL 2024
6
3-Rail Power Sequencer
with Programmable Timing
SGM822
DETAILED DESCRIPTION
The SGM822 multivoltage power sequencer provides
power-up and power-down control for up to three power
supplies. Three output flags are connected to the
enable or shutdown pins of the power supplies to
control the operation. The delay time between each flag
signals is programmed by the TADJ capacitor. These
functions allow users to design a complex power
system without the concern of large inrush currents or
latch-up conditions that may cause the system
abnormality or even damaged. The user can use the
invert (INV) pin to reverse the logic of the flag outputs.
The INV pin is not allowed to be floating. The following
discussion assumes INV is held low so that the flag
output is active high.
Adjustable Timing
An external timing capacitor is connected between the
TADJ pin and ground that establishes the clock
waveform. The SGM822 linearly charges or discharges
this capacitor by a fixed current source/sink, denoted
ITADJ_SRC/ITADJ_SNK, of magnitude 11µA between
predefined threshold voltage levels, denoted VHTH and
VLTH. Figure 4 shows the timing waveform. Once the
capacitor voltage drops to VLTH, the chip reverses to
charge again. With this method, the clock cycle is
generated.
asserted, the open-drain flags will be sequentially
released.
The first flag (FLAG1) is released after a fixed time
period, denoted tD1 in Figure 5. This corresponds to
least nine, maximum ten, clock cycles depending on
where EN is asserted relative to the clock signal. After
the release of the first flag, another timing procedure
will begin to delay the release of the second flag
(FLAG2). This timing procedure simultaneously begins
when the timing capacitor starts charging. As a result,
the delay time, denoted tD2, corresponds to exactly
eight clock periods. Similarly, FLAG3 is released after
the delay time, denoted tD3, again eight clock cycles,
has expired. A 10nF TADJ capacitor generates typical
delay time tD2 and tD3 of 10.4ms and tD1 of from 11.7ms
to 13ms.
The power-down sequence is the same as power-up,
but in reverse order. When EN is pulled low, the third
flag (FLAG3) is pulled low after the delay time, denoted
tD4, has expired. The second and first flags will then
follow in a sequential manner after the corresponding
delay time. The delay time, denoted tD4, tD5, tD6, is equal
to tD1, tD2, tD3, respectively.
For robustness, the internal pull-down FET of each flag
is designed to limit the sink current level so that it can
sustain a short circuit to VCC for a short period.
High Threshold Level,
VHTH = 1.2V
EN
TADJ
Low Threshold Level,
VLTH = 0.5V
FLAG1
tCLK
Figure 4. TADJ Pin Timing Waveform
The clock cycle period is directly proportional to the
timing capacitor value. Considering the TADJ threshold
voltage levels and the charge/discharge current
magnitude, it can be shown that the timing capacitorclock period relationship is typically 130µs/nF. For
example, a 10nF capacitor sets up a clock period of
1.3ms.
FLAG2
FLAG3
TADJ
tD1
tD2
tD3
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 5. Power-Up Sequence, INV Low
The flag outputs are controlled by the enable (EN) pin.
After power-on, all the flags are held low until the
precision EN voltage exceeds its threshold. After EN is
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APRIL 2024
7
3-Rail Power Sequencer
with Programmable Timing
SGM822
DETAILED DESCRIPTION (continued)
EN
FLAG1
FLAG2
FLAG3
TADJ
tD1
tD2
tD3
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 6. Power-Up Sequence, INV High
EN
FLAG1
FLAG2
FLAG3
TADJ
tD4
tD5
tD6
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 7. Power-Down Sequence, INV Low
EN
FLAG1
FLAG2
FLAG3
TADJ
tD4
tD5
tD6
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 8. Power-Down Sequence, INV High
SG Micro Corp
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APRIL 2024
8
3-Rail Power Sequencer
with Programmable Timing
SGM822
DETAILED DESCRIPTION (continued)
Enable Circuit
R
VCCENABLE= 1.2V × 1 + EN1 - 6.5μA × REN1
REN2
The enable circuit is designed with an internal
comparator, an accurate bandgap voltage (1.2V, TYP),
to provide a precision enable threshold. With this
precision enable function, the user can use an external
capacitor to set the timing as shown in Figure 9.
Input Supply
(2.7V to 5.5V)
REN1
VCC
6.5μA
EN
EN
+
CEN
1.2V
(2)
FLAG1
SGM822
Enable
INV
_
FLAG2
REN2
FLAG3
TADJ
CADJ
GND
Figure 9. Precision Enable Circuit
Using the internal current source to charge the external
capacitor CEN, assuming EN is charging from 0V, the
delay time can be calculated by the equation as follows.
tENABLE _ DELAY =
1.2V × CEN
6.5μA
(1)
Figure 11. Enable Based On Input Supply Level
The EN pin provides the glitch-free feature to make the
system robust. The timer will start counting at the EN
rising edge, but will always reset if EN is pulled low
before FLAG1 is released. This is illustrated in Figure
12 with INV low.
EN
EN
1.2V
FLAG1
0V
tD1
tENABLE_DELAY
Figure 10. Enable Delay Timing
Alternatively, sequencing can be based on a certain
event. For example, connect the power supply of
SGM822 to EN pin through a resistor divider, as shown
in Figure 11. After the VCC voltage exceeds the
threshold voltage, the sequencing begins to execute.
When calculating the VCC threshold voltage that
triggers the sequencing event, take care of the effects
of the internal EN pull-up current source. The supply
voltage for which EN is asserted is given by:
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Figure 12. Enable Glitch Timing, INV Low
If EN is pulled low before the complete power-up
sequence, the SGM822 will enter a controlled
shutdown. Figure 13 describes the flag sequence if EN
is pulled low after FLAG1 releases, but before the
entire power-up sequence is completed. INV is
assumed low.
APRIL 2024
9
3-Rail Power Sequencer
with Programmable Timing
SGM822
DETAILED DESCRIPTION (continued)
EN
FLAG1
FLAG2
FLAG3
TADJ
tD4
tD1
9 Clock
Cycles
< 8 Clock
Cycles
9 Clock
Cycles
EN
FLAG1
FLAG2
FLAG3
TADJ
tD1
tD2
9 Clock
Cycles
8 Clock
Cycles
< 8 Clock
Cycles
tD4
tD5
9 Clock
Cycles
8 Clock
Cycles
Figure 13. Incomplete Sequence Timing, INV Low
The Sequencing with EN Pin Control
The timing sequence of the SGM822 is controlled by
the enable (EN) pin. After power-on, all the flags are
held low until the precision EN pin is pulled high. After
EN is pulled high, the power-up sequence begins to
execute.
INV Pin Setting the Logic Output
When the INV pin is tied to a logic low, the flag output is
active high. When the INV pin is tied to a logic high, the
flag output is active low.
When EN is pulled low, the power-down sequence will
execute. After the third flag (FLAG3) corresponding
delay time expires, FLAG3 is pulled low. The second
and first flags will then be pulled low after their
appropriate delays.
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APRIL 2024
10
3-Rail Power Sequencer
with Programmable Timing
SGM822
APPLICATION INFORMATION
Pulling up Flag Pins to Independent Power
Supply
The SGM822 contains three open-drain output flags
which need external pulled-up resistors, for example
100kΩ pull-up resistors. This part is designed to protect
the flag output pins from damaging if these pins are
shorted to VCC for a short period.
For some application scenarios, the flag output voltage
needs to be different from the VCC voltage. The
separate flag power supply is used to pull up the
open-drain outputs. With this method, each flag is
pulled high to the required level of the controlled power
supplies. The user must make sure the flag supply
voltage is within the recommended operating range.
Design Example
In this example, the SGM822 is used to implement a
power-up (1 - 2 - 3) and power-down (3 - 2 - 1) sequence
of three power supplies.
Design Requirements
For this design example, use the parameters listed in
Table 1.
Design Procedure
A timing capacitor of CADJ = 10nF generates typical delay
time tD2 and tD3 of 10.4ms and tD1 of between 11.7ms
and 13ms. Connect the INV pin to GND so that the
output flags are active high. See Adjustable Timing for
calculating the value for CADJ.
2.7V to 5.5V Supply
VCC
Enable Input
R1
100kΩ
EN
SGM822
INV
CADJ
10nF
TADJ
GND
Flag
Supply
0.1µF
R2
100kΩ
R3
100kΩ
FLAG1
Flag 1
FLAG2
Flag 2
FLAG3
Flag 3
Figure 14. Sequencing Using Independent Flag Supply
Table 1. Design Parameters
Design Parameter
Example Value
Input Supply Voltage Range
2.7V to 5.5V
Flag Output Voltage, EN high
Input Supply
Flag Output Voltage, EN low
0V
Flag Timing Delay, tD1
11.7ms - 13ms
Flag Timing Delay, tD2 and tD3
10.4ms
Power-Up Sequence
1-2-3
Power-Down Sequence
3-2-1
Table 2. Evaluation Board Bill of Materials
Ref Des
Description
Case Size
Manufacturer
Manufacturer P/N
U1
SGM822 Sequencer
MSOP-8/UTDFN-1.5×1.5-8L
SGMICRO
XXX
R1
100kΩ
0603
Vishay Dale
CRCW06031003F-e3
R2
100kΩ
0603
Vishay Dale
CRCW06031003F-e3
R3
100kΩ
0603
Vishay Dale
CRCW06031003F-e3
CADJ
10nF ±5% 50V C0G
0603
Murata
GRM1885C1H103JA01D
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APRIL 2024
11
3-Rail Power Sequencer
with Programmable Timing
SGM822
APPLICATION CURVES
Power-Up Sequence
Power-Down Sequence
VCC = 5V, CADJ = 10nF
VCC = 5V, CADJ = 10nF
FLAG3
Time (4ms/div)
Time (4ms/div)
Power-Up Sequence
Power-Down Sequence
VCC = 5V, TADJ Open
VCC = 5V, TADJ Open
FLAG1
FLAG2
FLAG3
Time (20μs/div)
EN
5V/div 5V/div 5V/div 5V/div
5V/div 5V/div 5V/div 5V/div
EN
5V/div 5V/div 5V/div 5V/div
FLAG2
5V/div
FLAG3
FLAG1
5V/div
FLAG2
EN
5V/div
FLAG1
5V/div
EN
FLAG1
FLAG2
FLAG3
Time (20μs/div)
LAYOUT GUIDELINES
An input capacitor is not necessary but recommended
to avoid the possible noise effect which might be
present on the VCC pin. A 0.1μF ceramic capacitor
may be placed as close as possible to the VCC pin.
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Connect pull-up resistors between the flag output pins
and a positive input supply (VCC or an independent
flag supply). Minimal trace length is recommended to
avoid the unexpected noise from the environment. A
typical value for the pull-up resistors is 100kΩ.
APRIL 2024
12
SGM822
3-Rail Power Sequencer
with Programmable Timing
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
APRIL 2024 ‒ REV.A.1 to REV.A.2
Page
Added UTDFN-1.5×1.5-8L package................................................................................................................................................................... All
Changed Electrical Characteristics section .......................................................................................................................................................... 4
AUGUST 2020 ‒ REV.A to REV.A.1
Page
Changed Absolute Maximum Ratings section ...................................................................................................................................................... 2
Changed Electrical Characteristics section .......................................................................................................................................................... 4
Changed Enable Circuit section......................................................................................................................................................................... 10
Changes from Original (JULY 2020) to REV.A
Page
Changed from product preview to production data ............................................................................................................................................. All
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APRIL 2024
13
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
MSOP-8
b
E1
E
4.8
1.02
e
0.41
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
D
ccc C
A
SEATING PLANE
A1
H
A2
c
L
C
Symbol
θ
Dimensions In Millimeters
MIN
MOD
MAX
A
-
-
1.100
A1
0.000
-
0.150
A2
0.750
-
0.950
b
0.220
-
0.380
c
0.080
-
0.230
D
2.800
-
3.200
E
2.800
-
3.200
E1
4.650
-
5.150
e
L
0.650 BSC
0.400
H
θ
-
0.800
0.250 TYP
0°
ccc
-
8°
0.100
NOTES:
1. This drawing is subject to change without notice.
2. The dimensions do not include mold flashes, protrusions or gate burrs.
3. Reference JEDEC MO-187.
SG Micro Corp
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TX00014.001
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
UTDFN-1.5×1.5-8L
e
N5
N8
E2
k
E1
D
D2
D1
E3
N4
TOP VIEW
N1
b
L
BOTTOM VIEW
0.40
1.2
1.10
0.7
A
A1
A2
SIDE VIEW
Symbol
0.25
Dimensions
In Millimeters
MIN
MAX
A
0.400
A1
0.000
A2
1.450
D1
0.600
D2
1.450
E1
1.100
E2
1.200
0.050
0.000
1.550
0.057
0.800
0.024
0.002
0.061
0.031
0.008 REF
1.550
0.057
1.300
0.043
0.061
0.051
0.002 REF
1.400
0.047
0.250
0.006
0.055
0.008 REF
0.400 BSC
0.150
0.020
0.005 REF
0.200 REF
0.150
e
L
0.016
0.050 REF
k
b
0.500
0.200 REF
E
E3
Dimensions
In Inches
MIN
MAX
0.127 REF
D
0.45
0.010
0.016 BSC
0.250
0.006
0.010
NOTE: This drawing is subject to change without notice.
SG Micro Corp
www.sg-micro.com
TX00130.000
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
W
P0
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
B0
Reel Diameter
A0
P1
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel
Diameter
Reel Width
W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
P1
(mm)
P2
(mm)
W
(mm)
Pin1
Quadrant
MSOP-8
13″
12.4
5.20
3.30
1.50
4.0
8.0
2.0
12.0
Q1
UTDFN-1.5×1.5-8L
7"
9.0
1.70
1.70
0.75
4.0
4.0
2.0
8.0
Q1
SG Micro Corp
www.sg-micro.com
TX10000.000
DD0001
Package Type
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Pizza/Carton
7″ (Option)
368
227
224
8
7″
442
410
224
18
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
DD0002
Reel Type
TX20000.000
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