IR3Y38

IR3Y38M IR3Y38M DESCRIPTION CCD Signal Process & Digital Interface IC PIN CONNECTIONS VLOGIC VRB VRT Å NC ADIN ADOFS AGCCTL GND3 AGCOUT VCC3 GND2 The IR3Y38M is a bipolar single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, automatic gain control amplifier (AGC), reference voltage generator, black level detection circuit, 10-bit analog-to-digital converter (ADC), and serial interface for internal circuits. 48-PIN QFP TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 DO0 1 DO1 2 DO2 3 DO3 4 DO4 5 GND6 6 VCC6 7 DO5 8 DO6 9 DO7 10 DO8 11 DO9 12 13 14 15 16 17 18 19 20 21 22 23 24 ADCK GND5 VCC5 SCK VCC4 GND4 SDATA CLPCAP CCDIN REFIN GND1 SHISET 36 VCC2 35 Ô 34 OFSCTL 33 OBCAP 32 Î 31 fl/H3 30 fl/H2 29 fl/H1 28  27 ‰ 26 REFCAP 25 VCC1 FEATURES • Low power consumption : 315 mW (TYP.) • Wide AGC range : 12 to 43.5 dB • High speed sample-and-hold circuits : pulse width 12 ns (MIN.) • Built-in standby mode for power saving applications • Built-in serial interface to control the AGC gain, maximum gain and offset adjustment • 10-bit ADC operating up to 18 MHz • Digital interface for operating 3.3 V logic ICs • Single +5 V power supply • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 IR3Y38M BLOCK DIAGRAM VCC1 GND1 25 23 REFIN REFCAP CCDIN  fl/H1 fl/H2 28 29 30 SCK 16 SDATA 19 ADCK VCC4 GND4 VCC5 GND5 13 17 18 15 14 7 VCC6 22 26 21 CLAMP CLP S/H1 fl/H1 S/H2 fl/H2 SERIAL PARALLEL CONVERTER 6 GND6 12 DO9 CLAMP CLP S/H1 fl/H1 S/H2 fl/H2 11 DO8 MAX. GAIN SELECTOR 10 DO7 10-BIT A/D CONVERTER 9 DO6 OUTPUT BUFFER 8 DO5 5 DO4 4 DO3 3 DO2 2 DO1 CLPCAP SHISET 20 24 BIAS ERROR AMP CLAMP & S/H CURRENT SETUP S/H3 OBP + – AGC AMP + – VCC2 36 GND2 37 fl/H3 8-BIT AGC GAIN CONTROL D/A CONVERTER – + OBP BIAS GAIN 1 DO0 6-BIT OFFSET CONTROL D/A CONVERTER + CLAMP VCC3 38 GND3 40 31 32 35 fl/H3 Î Ô 34 33 OFSCTL OBCAP BLK + 41 39 43 45 42 47 46 AGCCTL AGCOUT ADIN Å ADOFS VRB VRT 48 27 VLOGIC ‰ 2 IR3Y38M PIN DESCRIPTION (The voltage is measured on condition that VCC1 to VCC6 = +5.0 V, VLOGIC = +3.3 V.) PIN NO. PIN NAME VOLTAGE 1 2 3 4 5 6 7 8 9 10 11 12 DO0 DO1 DO2 DO3 DO4 GND6 VCC6 DO5 DO6 DO7 DO8 DO9 0.2 V 10 k EQUIVALENT CIRCUIT VCC6 500 DESCRIPTION Digital data output pins of the A/D converter. DO0 is LSB. The data format is a straight binary code. VOL : 0.2 V (TYP.) 3.1 V 200 0.2 V 10 k VOH : VLOGIC – 0.2 V (TYP.) GND pin of the output buffer of the A/D converter. Power supply pin of the output buffer of the A/D converter. Digital data output pins of the A/D converter. DO9 is MSB. 200 GND6 0.0 V 5.0 V VCC6 500 3.1 V The data format is a straight binary code. VOL : 0.2 V (TYP.) VOH : VLOGIC – 0.2 V (TYP.) Clock input pin of the A/D converter. The A/D conversion is executed at the rising edge of the ADCK, and the data is output at the falling edge of the ADCK. GND5 GND6 VCC5 150 µ > 2.1 V 200 13 ADCK < 0.7 V 13 Duty : 50% fmax : 18 MHz (MIN.) Digital GND pin of the A/D converter. Digital power supply pin of the A/D converter. Clock input pin of the serial interface. Refer to "TRUTH TABLE" of pin 19. 14 15 GND5 VCC5 0.0 V 5.0 V VCC1 15 µ > 2.1 V 200 16 SCK < 0.7 V 16 GND1 3 IR3Y38M PIN NO. PIN NAME VOLTAGE 17 18 VCC4 GND4 5.0 V 0.0 V VCC1 15 µ EQUIVALENT CIRCUIT DESCRIPTION Analog power supply pin of the A/D converter. Analog GND pin of the A/D converter. Data input pin of the serial interface. TRUTH TABLE SDATA DATA 0 1 GND1 VCC1 > 2.1 V 200 19 SDATA < 0.7 V 19 SCK › fi fi Action SHIFT – STORE Bias decoupling pin of the CDS signal clamp circuit. This pin is connected to the GND1 via a 20 CLPCAP 3.2 V 200 20 capacitor. 100 µ GND1 VCC1 Signal input pin of the CDS. Input CCD signal to this pin via a capacitor. Reference input pin of the CDS. 21 CCDIN 2.5 V 26 k 200 150 µ 22 REFIN 2.5 V 26 k 150 µ This pin is connected to the GND1 via a capacitor. GND1 GND pin of the CDS/AGC. Pay careful attention to board 23 GND1 0.0 V layout of the GND1 because the CDS/AGC are noise-sensitive circuitry. VCC1 2k 2k 26 k Operation current setting pin of the CDS and fl/H3 circuits. This pin is connected to the GND1 via a resistor. The slew rates of the fl/Hs are in 24 SHISET 1.7 V 24 200 13 k inverse proportion to the value of the resistor. GND1 4 IR3Y38M PIN NO. PIN NAME VOLTAGE 5.0 V 25 VCC1 EQUIVALENT CIRCUIT DESCRIPTION Power supply pin of the CDS/AGC. VCC1 36 k 200 26 63 k 2k 150 µ 75 µ Bias decoupling pin of the CDS reference clamp circuit. This pin is connected to the GND1 via a capacitor. 26 REFCAP 3.2 V GND1 VCC1 5.0 V (open) 27 ‰ > 2.1 V 27 Standby function control pin. All actions stop and the power consumption is decreased when low. The threshold voltage has 0.4 V hysteresis. Connect to the Vcc if not used. Pulse input pin of the CDS feed- 110 k 200 40 µ 68 k 65 k 10 k 32 k < 0.7 V 75 k GND1 28  VCC1 through level clamp. Signal is clamped when low. Pulse input pin of the fl/H1. Signal is sampled when low. Pulse input pin of the fl/H2. Signal is sampled when low. Pulse input pin of the fl/H3. Signal is sampled when low. 29 30 31 fl/H1 > 2.1 V 200 50 µ fl/H2 flH3 < 0.7 V 100 GND1 32 Î Pulse input pin of the OPB clamp and bias error amplifier. Signal is clamped when low. Clamp capacitor pin of the optical black clamp (OPB clamp) circuit. Connect to the GND2 via a capacitor. VCC2 20 k 3.3 k 200 33 20 k 3.3 k 33 OBCAP 3.7 V 80 µ 80 µ GND2 5 IR3Y38M PIN NO. PIN NAME VOLTAGE EQUIVALENT CIRCUIT VCC1 DESCRIPTION Decoupling capacitor pin of the blanking offset control D/A converter. Connect to the GND1 via a capacitor. 2.15 34 OFSCTL to 2.30 V 200 34 10 k 2.2 V 100 µ 30 k D/A GND1 VCC2 20 µ Blanking pulse input pin. The output of the AGCOUT pin is blanked when low. The blanking level can be controlled by the serial interface. > 2.1 V 200 35 Ô < 0.7 V 35 GND2 36 37 VCC2 GND2 5.0 V 0.0 V Power supply pin of the fl/H3 and OPB clamp circuits. GND pin of the fl/H3 and OPB clamp circuits. Power supply pin of the output buffer circuit connected to the AGCOUT pin. VCC3 300 38 VCC3 5.0 V Signal output pin of the AGC. Connect to the ADIN pin via a capacitor. 20 39 39 0.9 V AGCOUT (Î = L) 10 k GND3 40 GND3 0.0 V VCC1 50 µ GND pin of the output buffer circuit connected to the AGCOUT pin. Decoupling capacitor pin of the AGC gain control D/A converter. Connect to the GND1 via a 11 k 2.5 41 AGCCTL to 3.8 V 41 200 capacitor. D/A GND1 6 IR3Y38M PIN NO. PIN NAME VOLTAGE 3.3 V (open) 42 ADOFS Input range 1.6 to 5.0 V 200 42 79 k 25 µ 25 µ 75 µ 70 k 70 k EQUIVALENT CIRCUIT VCC4 DESCRIPTION Voltage adjustment pin of the ADC black level clamp. This pin is biased at 3.3 V from the inside of the IC. Connect to the GND4 via a capacitor if not used. GND4 VCC4 50 µ 50 µ Signal input pin of the ADC. Connect to the AGCOUT pin via a capacitor. This capacitor is also used as the clamp capacitor of the ADC blank 43 ADIN 1.4 V (Å = L) 200 43 16 k 16 k level clamp. GND4 No connection. It is recommended 44 NC to connect to GND for better heat radiation and avoiding noise. Pulse input pin of the ADC black level clamp. Signal is clamped when low. When the ADOFS is opened, the clamped level is set to make the ADC output 61 (decimal). GND4 VCC4 5 VCC4 25 µ > 2.1 V 45 Å < 0.7 V 200 45 Upper reference decoupling pin of the ADC. Connect to the GND4 via a capacitor. 46 VRT 3.90 V 46 VRT GND4 VCC4 Lower reference decoupling pin of 5 47 VRB the ADC. Connect to the GND4 via a capacitor. 47 VRB 1.95 V GND4 GND4 7 IR3Y38M PIN NO. PIN NAME VOLTAGE EQUIVALENT CIRCUIT VCC5 25 µ 200 48 DESCRIPTION ADC output voltage setting pin. The high level voltage of the DO0 to DO9 pins is set to VLOGIC – 0.2 V. It is recommended to connect to the power supply of the following logic ICs. 48 VLOGIC 3.3 V GND5 FUNCTIONAL DESCRIPTION CDS Circuit The clamp circuit clamps the feed-through level of the CCD signal with the  pulse. Then the fl/H1 circuit samples the signal period of the one with the fl/H1 pulse and holds on. Thus the video signal is obtained. But this signal has a level drop caused by the reset pulse of the CCD signal, and for removing it, the fl/H2 circuit samples this signal again with the fl/H2 pulse. For reducing the effect of the sampling pulse or other noise sources, the CDS circuit is formed with a differential structure. Blanking Circuit The output signal is fixed to the blanking level with the Ô pulse. The blanking level is the sum of the black level and the offset value decided by the value of the OFFSET serial register. A/D Converter Circuit The fl/H3 circuit samples the amplified signal with the fl/H3 pulse and the A/D converter converts the sampled signal to 10-bit straight binary digital data. The clamp circuit placed in front of the A/D converter clamps the signal level beside the lower limit of the convertible input range with the Å pulse. The clamped level is controllable by the voltage of the ADOFS pin. The A/D conversion is executed at the rising edge of the ADCK clock, and the data is output at the falling edge. The high level voltage of the outputs is controlled by the voltage of the VLOGIC pin. Bias Error Amplifier Circuit For stabilizing the bias level of the CDS circuit and reducing the offset of the AGC circuit, the bias error amplifier acts with the Î pulse during the OPB period. AGC Amplifier Circuit The AGC amplifier amplifies the video signal obtained by the CDS circuit. The gain of the AGC is controlled by the value of the AGCGAIN serial register. And the maximum gain of the AGC is controlled by the value of the GAINSEL serial register. Standby Function By making the ‰ pin low, all actions of this IC stop and power consumption is decreased. The outputs of the A/D converter (DO0 to DO9) turn to high impedance when on standby. OPB Clamp Circuit For clamping the level of the amplified signal to the black level, the OPB clamp circuit acts with the Î pulse during the OPB period. 8 IR3Y38M Serial Interface Circuit The IR3Y38M has a serial interface to control the gain of the AGC amplifier and the offset of the blanking level. This interface is constituted by a shift register for serial-parallel conversion, data registers and D/A converters. The data input to SDATA is fetched and shifted at SDATA SCK Shift Register Store D2-D9 D0 D1 Decoder Select the rising edge of the SCK. While transmitting data, the SDATA must be low when the SCK falls. When the SDATA is high and the SCK falls, the data on the shift register is stored at the selected data register at the following falling edge of the SDATA. The stored data register is selected by the data of the D0 and D1 bits. GAIN SEL 0 1 2 3 4 MAXIMUM GAIN (dB) 22 25 28 31.5 34.5 38 41 43.5 3-bit Register 8-bit Register 6-bit Register 5 6 7 Gain Selector 8-bit D/A Converter 6-bit D/A Converter AGC GAIN 3.3 µs min. OFFSET Dummy Cycle SCK Store SDATA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA REGISTER GAIN SEL AGC GAIN OFFSET (Don't care) D9 d0 D8 d1 D7 d2 d0 D6 d3 d1 D5 d4 d2 D4 d0 d5 d3 D3 d1 d6 d4 D2 d2 d7 d5 MSB D1 0 0 1 1 D0 0 1 0 1 LSB 43.5 AGC GAIN (dB) 65 22 12 0 GA I E NS L= 7 GAIN S EL = 0 255 OFFSET (mV) –75 0 Value of OFFSET 63 Value of AGC GAIN 9 IR3Y38M TIMING CHART Reset Pulse Feed-through Level Signal Level CCD IN SIG1 SIG2 SIG3  fl/H1 fl/H2 S/H1 output SIG2 SIG1 SIG3 SIG3 S/H2 output SIG2 SIG1 AGC output SIG1 SIG2 SIG3 fl/H3 SIG1 S/H3 output SIG2 SIG3 ADCK DO0-DO9 SIG1 SIG2 SIG3 tDLH tDHL tWLH tWHL 10 IR3Y38M CCD IN –1 ns min.  12 ns min. fl/H1 2 ns min. 3 ns min. 2 ns min. 12 ns min. fl/H2 3 ns min. fl/H3 35 ns min. ADCK 35 ns min. 5 ns min. 3 ns min. 12 ns min. 1 ns min. 12 ns min. 25 ns min. 25 ns min. signal interval OPB interval idle transfer interval signal interval Î 1.5 µs min. Ô Å 1.5 µs min. 11 IR3Y38M PRECAUTIONS Each VCC1 to VCC6 pin corresponds to the each GND1 to GND6 pin. Connect a ceramic capacitor as near the IC as possible between each corresponding VCC pin and GND pin. The GND1 pin is the ground of the CDS/ADC circuit handling a weak signal. Pay careful attention to the board layout of the GND1 pattern in order to avoid the potential fluctuation of the GND1 caused by the current of the other GND pins. Especially pay attention to the current of the GND6 pin's flowing spiky current. All the GND pins must be at the same potential and not open. And keep the potential difference of each VCC pin within 0.3 V. The high level voltage of the outputs of the A/D converter is controllable by the voltage of the VLOGIC pin, but take care that the high level voltage does not fall below about 1.5 V, in spite of making the VLOGIC pin 0 V. This may cause the latch up of the following logic ICs if the power supply of this IC rises up faster than the power supply of the following logic. To avoid this problem, it is recommended to make the ‰ pin low until the voltage of the logic power supply becomes stable. Take care too that the high level voltage does not rise above about VCC – 1.0 V, in spite of making the VLOGIC pin the VCC potential. Restore the value of the serial register when setting up the power supply or making the ‰ pin high because the value will have been removed in that case. ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Power consumption PD derating ratio Operating temperature Storage temperature TOPR TSTG SYMBOL VCC1-VCC6 VIN PD (Unless otherwise specified, TA = +25 ˚C) CONDITIONS RATING 7 –0.3 to VCC + 0.3 570 4.5 –30 to +70 –55 to +150 UNIT V V mW mW/˚C ˚C ˚C TA ≤ +25 ˚C TA > +25 ˚C RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage Standard CCD input signal level Input "Low" voltage Input "High" voltage S/H pulse width Clamp pulse width A/D converter clock frequency Serial interface clock frequency SYMBOL VCC1-VCC6 VCCD VIL VIH tWS/H tWC fADCK fSCK APPLICABLE PINS CCDIN ‡, SCK, SDATA, ‰, Â, fl/H1, fl/H2, fl/H3, Î, Ô, Å Â, fl/H1, fl/H2, fl/H3 Î, Å ADCK SCK RATING 4.75 to 5.25 200 0 to 0.7 2.1 to VCC ≥ 12 ≥ 1.5 ≤ 18 ≤ 300 UNIT V mVp-p V V ns µs MHz kHz 12 IR3Y38M ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 0 V, SCK = 0 V, SDATA = 0 V, ‰ = 3.3 V,  = 0 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 0 V, SW42 = OFF, SW43 = (a), Å = 3.3 V) The current direction flowing into the pin is positive direction. • General PARAMETER Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) Total supply current Standby supply current Input "Low" current (1) Input "High" current (1) Input "Low" current (2) Input "High" current (2) Input "Low" current (3) Input "High" current (3) Input "Low" current (4) Input "High" current (4) ‰ voltage ‰ impedance SYMBOL CONDITIONS Measure pin 25 (VCC1) ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC ISTBY Measure pin 36 (VCC2). Measure pin 38 (VCC3). Measure pin 17 (VCC4). Measure pin 15 (VCC5). Measure pin 7 (VCC6). Total of ICC1 to ICC6 ‰ = 0 V, Total of ICC1 to ICC6. Apply to pin 28 (Â), pin 29 (fl/H1), pin 30 (fl/H2), pin 31 (fl/H3), and pin 32 (Î). VIL = 0 V IIH1 Apply to pin 28 (Â), pin 29 (fl/H1), pin 30 (fl/H2), pin 31 (fl/H3), and pin 32 (Î). VIH = 3.3 V Apply to pin 16 (SCK) and pin 19 (SDATA). VIL = 0 V Apply to pin 16 (SCK) and pin 19 (SDATA). VIH = 3.3 V Apply to pin 35 (Ô) and pin 45 (Å). VIL = 0 V Apply to pin 35 (Ô) and pin 45 (Å). VIH = 3.3 V Apply to pin 13 (ADCK). VIL = 0 V Apply to pin 13 (ADCK). VIH = 3.3 V Open pin 27 (‰). – 0 0.1 µA MIN. – – – – – – – – TYP. 27 2.3 0.7 13 16 5.0 63 4.5 MAX. 34 2.8 1.0 20 21 6.5 77 6.5 UNIT mA mA mA mA mA mA mA mA IIL1 –3.5 –2.0 – µA IIL2 IIH2 IIL3 IIH3 IIL4 IIH4 V27 Z27 –0.3 – –0.5 – –3.5 – 4.5 70 –0.2 0 –0.3 0 –2.0 0 5.0 110 – 0.1 0 0.1 – 0.1 – 140 µA µA µA µA µA µA V k$ 13 IR3Y38M • CDS & AGC Circuits PARAMETER CLPCAP voltage CCDIN voltage REFIN voltage SHISET voltage REFCAP voltage OBCAP voltage AGCOUT voltage CCDIN impedance REFIN impedance REFCAP impedance OFSCTL impedance AGCCTL impedance CLPCAP charge current CLPCAP discharge current CLPCAP leakage current OBCAP charge current OBCAP discharge current OBCAP leakage current SYMBOL V20 V21 V22 V24 V26 V33 V39 Z21 Z22 Z26 Z34 Z41 IL20 IH20 IZ20 IL33 IH33 IZ33 CLPCAP = 2.8 V, OBP = 0 V Measure the current of CLPCAP. CLPCAP = 3.6 V, OBP = 0 V Measure the current of CLPCAP. CLPCAP = 3.2 V, OBP = 3.3 V Measure the current of CLPCAP. OBCAP = 3.3 V, OBP = 0 V Measure the current of OBCAP. OBCAP = 4.1 V, OBP = 0 V Measure the current of OBCAP. OBCAP = 3.7 V, OBP = 3.3 V Measure the current of OBCAP. CONDITIONS MIN. 2.9 2.3 2.3 1.5 2.9 3.3 0.7 9 9 15 6 7 – 110 –0.5 – 65 –0.5 TYP. 3.2 2.5 2.5 1.7 3.2 3.7 0.9 13 13 23 9 11 –135 135 0 –90 90 0 MAX. 3.6 2.8 2.8 1.9 3.6 4.0 1.1 18 18 32 12 15 –110 – 0.5 –65 – 0.5 UNIT V V V V V V V k$ k$ k$ k$ k$ µA µA µA µA µA µA 14 IR3Y38M • A/D Converter Circuit PARAMETER ADOFS voltage ADIN voltage VRT voltage VRB voltage ADOFS impedance ADIN charge current ADIN discharge current ADIN leakage current SYMBOL V42 V43 V46 V47 Z42 IL43 IH43 IZ43 ADIN = 1.0 V, ADCLP = 0 V Measure the current of ADIN. ADIN = 1.8 V, ADCLP = 0 V Measure the current of ADIN. ADIN = 1.4 V, ADCLP = 3.3 V Measure the current of ADIN. SW43 = (b), ADCIN = 0.8 V Change the level of ADCK to L/H/L, then measure the voltages of DO0 to DO9 pins. SW43 = (b), ADCIN = 3.5 V Output "High" voltage VOH Change the level of ADCK to L/H/L, then measure the voltages of DO0 to DO9 pins. 2.9 3.1 – V ADCLP = 0 V CONDITIONS MIN. 3.0 1.2 3.7 1.8 50 – 30 –0.3 TYP. 3.3 1.4 3.9 1.95 70 –45 45 0 MAX. 3.6 1.6 4.1 2.2 90 –30 – 0.3 UNIT V V V V k$ µA µA µA Output "Low" voltage VOL – 0.2 0.4 V 15 IR3Y38M AC Characteristics (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 0 V, SCK = 0 V, SDATA = 0 V, ‰ = 3.3 V,  = 3.3 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 3.3 V, SW42 = OFF, SW43 = (a), Å = 3.3 V, (OFFSET) = 32) The value of the serial register is written with decimal. • CDS & AGC Circuits PARAMETER SYMBOL CONDITIONS (GAIN SEL) = 0, (AGC GAIN) = 0  = SG2, Î = SG3 Input the attenuated SG1 (f = 2 MHz, V = 1.6 Vp-p) to the SIN and seek the attenuation amount to make the amplitude of AGCOUT 1.6 Vp-p. AGC maximum gain (0) AGC maximum gain (1) AGC maximum gain (2) AGC maximum gain (3) AGC maximum gain (4) AGC maximum gain (5) AGC maximum gain (6) AGC maximum gain (7) AGC gain variable width (GAIN SEL) = 0, (AGC GAIN) = 255 GAX0 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 1, (AGC GAIN) = 255 GAX1 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 2, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. GAX3 (GAIN SEL) = 3, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 4, (AGC GAIN) = 255 GAX4 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 5, (AGC GAIN) = 255 GAX5 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 6, (AGC GAIN) = 255 GAX6 Measure the gain using the same procedure as for the measurement of GAN. (GAIN SEL) = 7, (AGC GAIN) = 255 Measure the gain using the same procedure as for the measurement of GAN. GAR GAR = GAX7 – GAN 26.5 31.5 35.5 dB 36.5 41 44.5 dB 34 38 42 dB 31 34.5 38 dB 28.5 31.5 35 dB 23 25 28 dB 20.5 22 24.5 dB MIN. TYP. MAX. UNIT AGC minimum gain GAN 11 12 13 dB GAX2 26 28 31 dB GAX7 38.5 43.5 47.5 dB 16 IR3Y38M PARAMETER SYMBOL CONDITIONS (GAIN SEL) = 0, (AGC GAIN) = 0  = SG2, Î = SG3 Bandwidth (1) (Minimum gain) fTN Input the SG1 (f = 2 MHz, V = 0.2 Vp-p) to the SIN and measure the amplitude of the AGCOUT. Increase the frequency and measure the frequency when the amplitude attenuates to –3 dB. (GAIN SEL) = 7, (AGC GAIN) = 255  = SG2, Î = SG3 Bandwidth (2) (Maximum gain) fTX Input the SG1 (f = 2 MHz, V = 8 mVp-p) to the SIN and measure the amplitude of the AGCOUT. Increase the frequency and measure the frequency when the amplitude attenuates to –3 dB. (GAIN SEL) = 0, (AGC GAIN) = 0 SIN = GND1, (OFFSET) = 0,  = 0 V, OFFSET adjustment limit (1) (OFFSET = 0) Î=0V Measure the voltage of the AGCOUT at BLK = 3.3 V and define it VBO11. Measure the one similarly at BLK = 0 V and define it VBO12. VBON = VBO12 – VBO11 (GAIN SEL) = 0, (AGC GAIN) = 0 OFFSET adjustment limit (2) (OFFSET = 63) SIN = GND1, (OFFSET) = 63,  = 0 V, VBOX Î=0V Measure the VBO21 and VBO22 similarly to above-mentioned method. VBON = VBO22 – VBO21 (GAIN SEL) = 0, (AGC GAIN) = 0  = SG2, Î = SG3 VDYN Input the SG1 (f = 2 MHz, V = 0.9 Vp-p) to the SIN and measure the amplitude of the AGCOUT. (GAIN SEL) = 7, (AGC GAIN) = 255  = SG2, Î = SG3 Input the SG1 (f = 2 MHz, V = 50 mVp-p) to the SIN and measure the amplitude of the AGCOUT. 2.0 2.2 – Vp-p 50 65 – mV 13 20 – MHz 24 35 – MHz MIN. TYP. MAX. UNIT VBON – –75 –60 mV Output dynamic range (1) (Minimum gain) Output dynamic range (2) (Maximum gain) VDYX 2.0 2.2 – Vp-p 17 IR3Y38M • A/D Converter Circuit (Unless otherwise specified, TA = +25 ˚C, VCC1 = VCC2 = VCC3 = VCC4 = VCC5 = VCC6 = 5.0 V, VLOGIC = 3.3 V, ADCK = 18 MHz square wave, ˘= 0 V, ˙ = 0 V, ‰ = 3.3 V,  = 3.3 V, fl/H1 = 0 V, fl/H2 = 0 V, fl/H3 = 0 V, Ô = 3.3 V, Î = 3.3 V, SW42 = OFF, SW43 = (b), Å = 3.3 V) PARAMETER SYMBOL SW43 = (a) Å=0V ADCIN = GND4 Read the output value of DO0 to DO9. Clamp value adjustment limit (1) Clamp value adjustment limit (2) Differential linearity error Integral linearity error SW42 = ON, V42 = 5.0 V, Å = 0 V, DCLPN ADCIN = GND4 Read the output value of DO0 to DO9. DCLPX SW42 = ON, V42 = 1.6 V, Å = 0 V, ADCIN = GND4 Read the output value of DO0 to DO9. DLE ADCIN = SG4 Read the output value of DO0 to DO9 at about 10 times and make it a histogram. Normalize the histogram and obtain the DLE. Integrate the histogram and obtain the ILE. Propagation delay (L/H) ADCIN = SG4, CL = 20 pF Measure the delay time from the falling edge (50%) of the ADCK to the rising edge (50%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF Propagation delay (H/L) tDHL Measure the delay time from the falling edge (50%) of the ADCK to the falling edge (50%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF Output rise time tWLH Measure the rise time (10%/90%) of the DO0 to DO9. ADCIN = SG4, CL = 20 pF Output fall time tWHL Measure the fall time (90%/10%) of the DO0 to DO9. 10 17 25 ns 10 17 25 ns 15 26 38 ns 6 CONDITIONS MIN. TYP. MAX. UNIT Clamp value DCLP 56 61 66 – 31 36 41 – 81 86 91 – – ±0.5 ±0.9 LSB ILE – ±3 ±7 LSB tDLH 15 26 38 ns 18 IR3Y38M Measurement Waveforms f [Hz] SG1 V 3.3 V SG2 0V 3.3 V SG3 0V above 1.5 µs below 100 µs 3.5 V SG4 1.1 V 1 ms 19 IR3Y38M Test Circuit Ô Î fl/H3 fl/H2 fl/H1  0.1 µF 0.1 µF 0.1 µF Vcc2 + 100 µF 0.1 µF V27 Vcc1 36 Vcc2 35 34 33 32 31 30 29 28 27 26 25 Vcc1 SHISET 0.1 µF + 100 µF 37 Vcc3 AGCOUT + 100 µF 0.1 µF STBY GND2 Vcc3 24 23 1 µF 22 K$ 38 39 +– + S/H3 + AGC Gain – Bias GND1 S/H2 S/H2 – ERR + S/H1 S/H1 Clamp Clamp 22 1 µF GND SIN 0.1 µF 40 0.1 µF GND3 21 20 19 41 SW42 v42 0.1 µF ADIN 42 43 44 NC + 6-bit D/A 8-bit D/A Gain Selector SDATA (a) SW43 (b) Serial/Parallel Converter GND4 Vcc4 18 17 16 0.1 µF 100 µF + VCC4 SCK VCC5 CLAMP 10-bit A/D Converter Å 45 VRT 46 0.1 µF 0.1 µF VRB Vcc5 15 14 + 0.1 µF 100 µF 47 Output Buffer 48 VLOGIC GND6 Vcc6 GND5 13 8 20 pF ADCK 1 20 pF 20 pF DO0 2 20 pF DO1 3 20 pF DO2 4 20 pF DO3 5 6 7 9 20 pF 10 20 pF 11 20 pF 12 0.1 µF 20 pF 100 µF + DO4 Vcc6 DO5 DO6 DO7 DO8 DO9 20 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE 48 QFP (QFP048-P-0707) (Unit : mm) 0.5TYP. 36 M 37 0.08 0.2±0.08 (1.0) 25 24 7.0±0.2 9.0±0.3 0.15±0.05 1 (1.0) 7.0±0.2 9.0±0.3 12 (1.0) (1.0) 48 13 0.65±0.2 1.45±0.2 0.1±0.1 21 Package base plane 8.0±0.2 0.1