IR3Y48

IR3Y48M IR3Y48M DESCRIPTION CCD Signal Process & Digital Interface IC PIN CONNECTIONS 48-PIN QFP TOP VIEW The IR3Y48M is a CMOS single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, automatic gain control amplifier (AGC), reference voltage generator, black level detection circuit, 20 MHz 10-bit analog-to-digital converter (ADC), timing circuit for internally required pulses, and serial interface for internal circuits. 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 AVDD4 2 NC 3 VRN 4 VRP 5 AVDD2 6 AVDD2 7 AVSS2 8 AVSS2 9 VCOM 10 CCDIN 11 REFIN 12 13 14 15 16 17 18 19 20 21 22 23 24 CLPCAP ADIN OBCAP MONOUT NC AISET AVDD1 AVSS1 NC ADCK SHR SHD 36 OP 35 RESETN 34 AVDD3 33 AVSS3 32 STBYN 31 CSN 30 SDATA 29 SCK 28 OBP 27 CCDCLP 26 BLK 25 ADCLP FEATURES • Low power consumption : 110 mW (TYP.) at 20 MHz mode • Wide AGC range : 0 to 36 dB (Gain step : 0.094 dB/step) • High speed sample-and-hold circuits : pulse width 10 ns (MIN.) • Power save operation : 84 mW (TYP.) at 15 MHz mode • Standby mode : less than 0.3 mW • Built-in serial interface • 10-bit ADC operating up to 20 MHz – Non-linearity DNL : 0.6 LSB (TYP.) INL : 1.5 LSB (TYP.) • Maximum input level of CCD signals : 1.1 Vp-p • Accepts a direct signal input to ADC or AGC (input level : 1 Vp-p (TYP.)) • Single +3 V power supply • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 DO9 DO8 DO7 DO6 DO5 DVDD DVSS DO4 DO3 DO2 DO1 DO0 (QFP048-P-0707) IR3Y48M BLOCK DIAGRAM SHR 23 CLPCAP 13 DC CLAMP SHD 24 CLPCAP MONOUT 16 BANDGAP VREF CCDCLP REFIN CDS + 12 S/H AGC ROUGH AGC FINE 10-BIT ADC VRP 5 VCOM 10 4 VRN DO0 to DO9 37 to 41, 44 to 48 19 AVDD1 6,7 AVDD2 34 AVDD3 CCDIN 11 ADCLP 6 dB/STEP (0 to 12 dB) CCD ADIN 14 OBCAP 15 6 dB/STEP 0.094 dB/STEP (0 to 18 dB) (0 to 6 dB) DAC COMPARE REGISTER (7-BIT) 2 AVDD4 20 AVSS1 8,9 AVSS2 OBP AISET 18 TIMING GENERATOR SERIAL REGISTER 33 AVSS3 43 DVDD 42 DVSS ADCK 22 26 BLK 28 27 25 31 29 30 OBP CCDCLP ADCLP CSN SCK SDATA 36 OP 35 RESETN 32 STBYN 2 IR3Y48M PIN DESCRIPTION PIN NO. SYMBOL 1 NC 2 3 AVDD4 NC I/O – – – VDD EQUIVALENT CIRCUIT DESCRIPTION No connection. Supply of 2.7 to 3.6 V analog power. No connection. ADC internal negative reference voltage. (Connect to AVSS via 0.1 µF.) ADC internal positive reference 4 VRN O 5 VRP O ◊ GND voltage. (Connect to AVSS via 0.1 µF.) Supply of 2.7 to 3.6 V analog power. Supply of 2.7 to 3.6 V analog power. An analog grounding pin. An analog grounding pin. 6 7 8 9 AVDD2 AVDD2 AVSS2 AVSS2 – – – – VDD ADC internal common reference voltage. (Connect to AVSS via 0.1 µF.) 10 VCOM O 10 ◊ GND CDS circuit data input. VDD 11 CCDIN I CDS circuit reference input. 12 REFIN I ◊ GND 13 14 15 16 CLPCAP ADIN OBCAP MONOUT O I O ◊ Clamp level output. VDD (Connect to AVSS via 0.1 µF.) ADIN signal input. Black level integration voltage. (Connect to AVSS via 0.033 µF.) O GND Monitor output of CDS or AGC. ◊ Internal gate 3 IR3Y48M PIN NO. SYMBOL 17 NC I/O – VDD EQUIVALENT CIRCUIT DESCRIPTION No connection. Internal analog circuit bias input. (Connect to AVSS via 4.7 k$.) 18 AISET I 18 ◊ GND 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 AVDD1 AVSS1 NC ADCK SHR SHD ADCLP BLK CCDCLP OBP SCK SDATA CSN STBYN AVSS3 AVDD3 – – – I I I I I I I I I I I – – VDD GND Supply of 2.7 to 3.6 V analog power. An analog grounding pin. No connection. ADC sampling clock input. Reference sampling pulse input. VDD Data sampling pulse input. Clamp and black calibration control for ADIN signal. Blanking pulse input. Clamp control input. Black level period pulse input. Serial port clock input. Serial port data input. Serial port chip selection (active at low). Standby control (standby at low). An analog grounding pin. Supply of 2.7 to 3.6 V analog power. Reset signal input (reset at low). 35 RESETN I Serial I/F operation code enable pin 36 OP I GND (active at low). ◊ Internal gate 4 IR3Y48M PIN NO. SYMBOL 37 38 39 40 41 42 43 44 45 46 47 48 DO0 DO1 DO2 DO3 DO4 DVSS DVDD DO5 DO6 DO7 DO8 DO9 I/O O VDD EQUIVALENT CIRCUIT DESCRIPTION ADC digital output (LSB). (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) Digital output driver GND. A digital grounding pin. Digital output driver power supply. (2.7 to 3.6 V) ADC digital output. (Capable of High-Z) VDD O O O GND O – – O O O O GND ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output. (Capable of High-Z) ADC digital output (MSB). (Capable of High-Z) O NOTES : • NC pins are recommended to be connected to AVSS on PCB even they are not connected electrically in the chip. • High-Z at standby. 5 IR3Y48M FUNCTIONAL DESCRIPTION Outline The configuration of IR3Y48M is described below. SHR SHD MONOUT IR3Y48M Clamp VREF REFIN CCDIN CCD ADIN Black Control CDS + AGC 10-bit ADC DO0 toDO9 ADCK Timing Generator Serial Register BLK OBP CCDCLP ADCLP CSN SCK SDATA GENERAL TIMING CCD OB ADCK Effective Pixel (OB) Blanking BLK OBP CCDCLP DO0-DO9 Data Output Black Code 6 IR3Y48M CDS Circuit CDS circuit holds CCD precharge (reference) level at SHR pulse, then it samples CCD pixel data at SHD pulse. Correlated (common) noise is removed by subtraction of precharge level from pixel data level. CDS has the gain of maximum 12 dB (6 dB/step). This gain is a part of total gain and it is controlled by register value similar to gain in AGC circuit. Connect signal from CCD sensor to CCDIN pin through C-coupling. Place the same capacitor between REFIN and AVSS. Reference Clock (SHR) Data Clock (SHD) REFIN CDS CCD CCDIN CDS Output = V (CDS) = V (DAT) – V (PREC) CDS Operation Reset Pulse Reset Pulse V (PREC) V (CDS) V (DAT) SHR SHD SIG MAX. Level SHR SHD SIG fSMAX = 20 MHz/tSMIN = 50 ns 7 IR3Y48M Clamp Circuit DC CLAMP DC level of the analog input is fixed by internal DC clamp circuit. DC level of C-coupled CCD signal at CDS input is set to CLPCAP by DC clamping. Normally clamp switch is turned on at black level calibration period. Place 0.1 µF external capacitance between CLPCAP and AVSS. SHR SHD CCDCLP Clamp Timing Timing Control (Register Conditions) CCD REFIN ADCK CCDIN (CCDCLP) Clamp Source CLPCAP CCDCLP DC Clamp Function CLPCAP Level CLPCAP REFIN, CCDIN Clamp Level CLAMP OF ADIN SIGNAL Clamp operation for ADIN path is also available. Note that clamp voltage [CLPCAP] is different between CCD input and ADIN. ADCLP signal is used for both clamp and black level control at ADIN input mode. It is also possible to turn off clamp operation by register setting. CLAMP CONTROL Following items are selectable through register setting. a) Clamp current Normal or fast clamp is selectable for charge current. (Select normal clamp in general) b) Clamp target Input signal (REFIN and CCDIN) to be clamped is selectable. It is also possible to turn off the clamp function. ADIN ADCLP Timing Control To AGC or To ADC (ADCLP) CLPCAP ADIN DC Clamp Function 8 IR3Y48M Black Level Cancel Circuit The purpose of black level cancel is to adjust the AGC input level which can equalize the ADC output code to black level code written in the register. The black level cancelling is generally done during OB (optical black period) pulsed by OBP pulse. The register value ((1 to) 16 to 127 LSB : default 64 LSB) is written by serial interface. Black level cancel loop is established while OBP is low (when pulse is not inverted). In this loop, ADC output code is compared with register setting. During OB period, the OBP voltage gradually terminates into certain voltage resulting the output code equal to the register setting. The OBP voltage is discharged under following status : q Set black level reset register to 1 w Set RESET pin low e Power down (by STBYN or register control) The period to reach the final value depends on the status of chip. It may take more than one thousand pixels at start-up or after reset. It may take only several pixels when the status is not changed. DC clamp [CCDCLP] is allowed during OBP low. Black level cancelling for ADIN signal (broken line in the chart) is controlled by ADCLP pulse (clamp and OB control are done simultaneously) instead of OBP. CDS REFIN CCDIN ADIN OBCAP S/H AGC Rough + AGC Fine 10-bit ADC DO0-DO9 DAC OBP (Path for ADIN) ADCLP OBP ADCLP Compare Register (7-bit) Black Level Calibration Blanking CCD Effective Pixel Signal Optical Black Period Blanking Effective Pixel Signal ADCK OBP Previous Black Level Resulting Black Calibration Level (Hold) OBCAP Black Level Calibration Timing 9 IR3Y48M Gain Control Circuit The total gain for CCD input signal covers from 0 to 36 dB. This range consists of CDS (0 to 12 dB (6 dB/ step)), AGC rough (0 to 18 dB (6 dB/step)), and AGC fine (0 to 6 dB (0.094 dB/step)). Total gain is controlled (as described below) by 9-bit gain control register. The gain is fixed to maximum gain when the code exceeds 382 (decimal). The gain of ADIN (which bypassing CDS) is 0 to 24 dB. 0.094 dB 1 step 35.91 dB 0 dB 0D 383D AGC Block CDS 6 dB/step (0 to 12 dB) Rough 6 dB/step (0 to 18 dB) Fine 0.094 dB/step (0 to 6 dB) Total Gain = 0 to 35.91 dB Gain Control 10 IR3Y48M A/D Converter Circuit IR3Y48M integrates 20 MHz 10-bit full pipeline A/D converter (ADC). A/D CONVERSION RANGE The analog input range of the ADC is determined by VREF circuit integrated in IR3Y48M. At ADC direct input (ADIN) mode (Mode (1) Register D5 = 1), feed 1 Vp-p (full scale) signal based on clamp level as zero reference into ADIN input pin. A/D CONVERTER OUTPUT CODE (AT MODE (1) REGISTER D5 = 1) The digital output format is binary. Thus, "all zero" digital output with zero reference input (ADIN = CLPCAP), "all one" digital output with full-scale input (ADIN = CLPCAP + 1 V (TYP.)). CLOCK, PIPELINE DELAY AND OUTPUT DIGITAL DATA TIMING The A/D conversion is performed based on the clock fed to ADCK pin. The track-and-hold operation is completed at falling (when not inverted) edge of ADCK. The 10-bit width parallel data is obtained at rising edge after 5.5 clock pipeline delay. (Sampling edge is selectable by register setting.) CODE AT CLAMP LEVEL (AT MODE (1) REGISTER D5 = 0, D4 = 1) The output code at clamp level can be set throughout (1 to) 16 to 127 LSB at the step of 1 LSB by register setting. ADC OUTPUT CODE LOGIC ADC digital output is High-Z under following conditions : q Set ADC output register to 1 w Set SYBYN pin low e Power down (by STBYN or register control) DIGITAL OUTPUT CODE According to ADIN, digital codes are determined as follows : Data Output at Straight Binary [Mode (1) Register D2 = 0, D5 = 1] ADIN MSB DIGITAL CODE LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp 1 reference + 1 V : : : : Clamp reference 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 1 : 0 1 : 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 11 IR3Y48M Other Functions ADC DIRECT INPUT (ADIN MODE) Direct input path to ADC or AGC is realized by register setting. This direct path can be turned off by register. Black level cancel and clamp are performed at the same timing of ADCLP low. These controls can be masked by register setting. BLK, SHR, and SHD controls are ignored at ADIN mode. The signal at AGC input is shown below. (N) ADIN (N+1) (N+2) ADCK (When ADCK is inverted, signal (N) is sampled by this edge) ADCLP DO0-DO9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N Black Cancel & Clamp NOTE : For ADCLP low, both black level cancel and clamp are active at AGC input mode, and only clamp is active at ADC input mode. ADIN Signal Processing (AGC Input) Operation at ADC direct input is shown below. The zero reference (CLPCAP) is established by ADCLP pulse. The ADIN input range is from CLPCAP + 1 V (TYP.) (full scale). Full scale CLPCAP + 1 V ADC dynamic range = 1 Vp-p ADIN CLPCAP ADCLP Clamp ON ADIN Signal Input Level STANDBY MODE The standby mode can be set either by register setting or STBYN pin. If one of the above is set, IR3Y48M powers down. ("OR" logic) 12 IR3Y48M MONITOR OUTPUT By setting the register, the signal from MONOUT is selectable. Alternatives are OFF, CDS output, AGC output, or REFIN/CCDIN output. Even at the CDS gain is set to a certain gain, the CDS output on MONOUT is multiplied by 1/gain resulting the level before CDS amplification. The output level of MONOUT is shown below. The MONOUT level is VCOM (1.1 V, TYP.) at zero reference level. For the maximum amplitude (1.1 Vp-p), the output level is 2.2 V (TYP.). CAUTION : VCOM pin does not have enough driving capabilities. CCD V0 = No signal V1 V2 V3 MAX. signal = 1.1 V MAX. level = VCOM + 1.1 V = 2.2 V V1 V2 V3 V0 = No signal level MONOUT MON reference level = VCOM = 1.1 V (TYP.) Monitor Output Level POLARITY INVERSION Following timing pulse of IR3Y48M control can be inverted by register setting : q ADCK (A/D converter sampling pulse) w SHR, SHD (CDS sampling clock) e BLK, OBP, CCDCLP, ADCLP (Enable controls) POWER SAVE Power save mode is selectable for the sampling frequency below 15 MHz. The power consumption at this mode is lower than 20 MHz mode. General Notice for Power Supply It is recommended to supply both AVDD and DVDD supply from single regulator. (Observe absolute maximum rating specification : DVDD ≤ (AVDD + 0.3 V) even at the power-up and power-down sequence.) Refer to "APPLICATION CIRCUIT EXAMPLE" against noise of power supply. 13 IR3Y48M Serial Interface Circuit The internal registers of IR3Y48M are controlled through 3-wire serial interface. The 16-bit length control data consists of 2-bit operation code, 4-bit address, and 10-bit data. The controller should set each bit synchronizing to SCK falling since IR3Y48M (receiver) acquire data at SCK rising edge. The data is valid while CSN is low. The written data comes effective at rising edge of CSN. Fix CSN to high when no access is conducted. It is forbidden to write data to the address that is not listed. Always give 16 times SCK rising during CSN low. All data are ignored when SCK rising during CSN low is less than 16. CSN 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDATA O0 O1 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Ope Code Address Data Serial Write Control The effect of operation code is determined by OP pin control. When OP pin is high, the data are always valid regardless of O0 and O1. When OP pin is low, operation code control is active, and the data is written only when both O0 = 0 and O1 = 1 are true. 14 IR3Y48M Registers IR3Y48M has 10-bit x 5 registers to control its operations. All registers are write only. The serial registers are written by serial interface. Register Map R/W ADDRESS REFERENCE NAME A3 A 2 A1 A0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 Mode (1) 1 Mode (2) 0 Gain 1 Black level 0 Test register level reset/Standby Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection Total gain ADC code at black level (1 LSB step) Test mode (ADIN coupling mode) MAJOR FUNCTIONS [DATA] ADCK polarity/ADIN connection/Frequency mode/ADC output/Black W W W W W 1. Reference name 2. Register address [Write] 3. Register bit assignment Mode (1) A3 A2 A1 A0 0000 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Functions ADCK polarity ADIN connection Frequency mode ADC output Black level reset Standby XX X 0 X : Don't care 0 0 0 0 0 0 15 IR3Y48M 4. Register operations CONTROLS OPERATIONS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 Normal operation as timing chart 1 ADCK clock inversion 0 0 1 Frequency mode ADC output Black level reset Standby 0 1 X 0 1 0 1 0 1 ADIN function OFF ADIN signal to AGC ADIN signal to ADC 20 MHz mode 15 MHz mode Normal operation [ADC data output] ADC output High-Z [or logic of STBYN] Normal operation Black level reset [or logic of RESETN] 0 Normal operation 1 Standby [or logic of STBYN] X : Don't care NOTE ADCK polarity ADIN connection 1 2 NOTES : 1. ADC output is set to high impedance if one of following case is true. Case 1 : Set "ADC output" bit to "1". Case 2 : Set STBYN pin to low. Case 3 : Set "Standby" bit to "1". 2. Black level integral CAP [OBCAP] is discharged if following case is true. Case 1 : Set "Black level reset" to "1". Case 2 : Set RESETN pin to low. 16 IR3Y48M 1. Reference name 2. Register address [Write] 3. Register bit assignment Default Functions Clamp current ADIN clamp Clamp target S/H, enable logic Monitor selection X : Don't care Mode (2) A3 A2 A1 A0 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX00000000 4. Register operations CONTROLS D 9 D8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Clamp current ADIN clamp Clamp target 0 1 0 1 0 0 1 1 S/H, enable logic 0 1 0 1 0 0 1 1 Monitor selection 0 1 0 1 0 0 1 1 Fast clamp Clamp operation active for ADIN No clamp for ADIN Normal mode [clamp both REFIN & CCDIN] Clamp REFIN only Clamp CCDIN only Clamp OFF Normal operation as timing chart S/H control polarity inversion Enable control polarity inversion Both of S/H and enable inversion 0 Monitor OFF 1 CDS signal to monitor 0 AGC output monitor 1 Output REFIN and CCDIN (for calibration) 3 4 1 2 OPERATIONS Normal clamp NOTE NOTES : 1. 2. 3. 4. The S/H signals are SHR and SHD. The enable controls are BLK, OBP, CCDCLP, and ADCLP. At this mode, monitor output gain = 0 dB regardless of CDS gain. At this mode, monitor output depends on CDS gain. 17 IR3Y48M 1. Reference name 2. Register address [Write] 3. Register bit assignment Default Functions Total gain X : Don't care Gain A3 A2 A1 A0 0 0 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X000000000 4. Register operations CONTROLS D 9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Total gain (For CCDIN input) 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 π 1 1 0 0 π 0 π 0 π 0 π 0 π 1 1 1 1 0 π 1 1 1 1 1 1 511 1FF 35.906 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 DECIMAL 0 1 2 3 4 62 63 64 65 128 192 256 320 380 381 382 383 384 HEX 0 1 2 3 4 3E 3F 40 41 80 C0 100 140 17C 17D 17E 17F 180 TOTAL GAIN (dB) 0.000 0.094 0.188 0.281 0.375 5.813 5.906 6.000 6.094 12.000 18.000 24.000 30.000 35.625 35.719 35.813 35.906 35.906 1 NOTE 18 IR3Y48M CONTROLS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Total gain (For AGC input) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 π 1 1 0 0 π 0 π 0 π 1 1 0 0 0 π 1 0 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 192 254 255 256 257 258 511 C0 FE FF 100 101 102 1FF 18.000 23.813 23.906 23.906 23.906 23.906 2 23.906 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0 1 0 1 0 TOTAL GAIN (dB) 0.000 0.094 0.188 0.281 0.375 5.813 5.906 6.000 6.094 12.000 DECIMAL 0 1 2 3 4 62 63 64 65 128 HEX 0 1 2 3 4 3E 3F 40 41 80 NOTE NOTES : 1. Gain is always (35.90625 dB, TYP.) for code greater than 382 (decimal). 2. Gain is always (23.906 dB, TYP.) for code greater than 254 (decimal). 19 IR3Y48M 1. Reference name 2. Register address [Write] 3. Register bit assignment Default Functions Black level X : Don't care Black level A3 A2 A1 A0 0 0 1 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX1000000 4. Register operations OPERATIONS [ADC CODE : BINARY] B 9 B 8 B7 B 6 B5 B4 B 3 B2 B1 B 0 Black level 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 π 1 0 0 0 0 π 0 π 0 π 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 124 125 126 127 7C 7D 7E 7F 0 0 0 0 0 0 32 64 20 40 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 DECIMAL FORBIDDEN 1 15 16 17 18 19 HEX FORBIDDEN 1 F 10 11 12 13 NOTE 1 1 1 NOTE : 1. Codes 1 to 15 are available but not recommended black calibration period is specified under 15 < code < 128. 20 IR3Y48M 1. Reference name 2. Register address [Write] 3. Register bit assignment Default Functions ADIN test mode X : Don't care Test register A3 A2 A1 A0 0 1 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX0000000 4. Register operations CONTROLS D9 D 8 D7 D6 D5 D4 D3 D2 D1 D0 ADIN test mode 0 1 OPERATIONS Normal operation VCOM centered ADIN for AC coupling NOTE : D5 to D0 must always be "0". Test register (D6) is prepared for ADIN AC coupled input. Using this mode the signal center is set to VCOM. No clamp signals are required at this mode. Connect C-coupled output to ADIN. The resistance 50 k$ between ADIN (14 pin) and CLPCAP (13 pin) stabilize the DC level at ADIN pin. 21 IR3Y48M ABSOLUTE MAXIMUM RATINGS PARAMETER Power supply voltage Voltage difference Input current Analog input voltage Digital input voltage (Input pin) Digital input voltage (Output pin) Operating temperature Storage temperature SYMBOL AVDD DVDD VDLT IIN VINA VINL VONL TOPR TSTG (AVSS = DVSS = 0 V, all voltages are with respect to GND.) CONDITIONS RATING –0.3 to +4.5 –0.3 to +4.5 or AVDD + 0.3 DVDD – AVDD Except PS 0.3 ±10 AVSS – 0.3 to AVDD + 0.3 AVSS – 0.3 to AVDD + 0.3 AVSS – 0.3 to AVDD + 0.3 –30 to +85 –40 to +125 UNIT V V V mA V V V ˚C ˚C 2 NOTE 1 NOTES : 1. The higher voltage of 4.5 V and AVDD + 0.3 V specifies maximum value of DVDD absolute maximum rating. 2. The VONL limits the excess voltage applied to digital output pins. WARNING : Operation at or beyond these limits may result in permanent damage to the device. Normal operating specifications are not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS = DVSS = 0 V, all voltages are with respect to GND.) PARAMETER Analog Supply voltage Digital output SYMBOL CONDITIONS AVDD At start-up, turn on AVDD before (or at DVDD the same time as) turning on DVDD. MIN. 2.7 2.7 TYP. 3.0 3.0 MAX. 3.6 AVDD UNIT V V ELECTRICAL CHARACTERISTICS Supply Current PARAMETER Analog Supply current at normal operation Digital Analog Digital SYMBOL IA15 ID15 IA20 ID20 IPE IPD CONDITIONS fs = 15 MHz (At 15 MHz mode) fs = 20 MHz (At 20 MHz mode) (At 20 MHz mode) (TA = +25 ˚C, AVDD = DVDD = 3.0 V) MIN. TYP. 28 3 36 3.5 38 MAX. 34 6 44 7 46 0.1 UNIT mA mA mA mA mA mA NOTE 1 Supply current at monitor active Supply current at power down 2 NOTES : 1. Specified under monitor function off. 2. Measured under no analog input and clock fixed at low. 22 IR3Y48M Analog Specifications (Unless otherwise specified, AVDD = DVDD = 3.0 V, TA = +25 ˚C, signal frequency fIN = 1 MHz, signal level = –1 dB (full scale)) The current direction flowing into the pin is positive direction. CDS & CLAMP CIRCUITS PARAMETER Analog input range Input referred noise Input capacitance Input Bandwidth Clamp voltage Black calibration period SYMBOL VICDS VIAI NI CIN CBW VCLPCAP tBKCAL Normally At ADIN 1.65 1.15 1.8 1.3 CONDITIONS Normally At ADIN At fs = 20 MHz At gain = max. At gain = min. (Sampling frequency fS = 20 MHz) MIN. TYP. 1.1 1.1 100 400 15 1 1.95 1.45 2000 MAX. UNIT Vp-p Vp-p µVrms µVrms pF pixel V V pixel 4, 5 3 NOTE 1 2 CCDIN, ADIN & REFIN NOTES : 1. Normally : Signal path through CDS/AGC/ADC In this case analog input range is downward from clamp voltage. ADIN : Signal bypassing CDS (Direct AGC or ADC input) In this case analog input range is upward from clamp voltage. 2. Specified at MONOUT pin. The noise bandwidth is 100 kHz to 5 MHz. 3. Bandwidth from CCDIN/REFIN to ADC. The bandwidth is specified as the settling time of ADC output for step input (full scale – 1 dB) response (at gain = min.). 4. Black calibration period is the period of stabilization of output code within ±1 LSB (average) compared to register value for the black level code of 0 to 50% of the full scale input. (Assuming external capacitance = 0.033 µF.) External capacitor value to OBCAP pin determines the bandwidth of the black level cancel loop. Since the gain of the loop depends on sampling frequency, the maximum frequency (settling within certain pixels) and the minimum frequency (avoiding oscillation of the circuit) are defined. 5. Select the external capacitor referring the following list based on the minimum and maximum operating frequencies. If the black level settling specification (within 2 000 pixels) could be ignored, the maximum sampling frequency for 0.1 µF and 0.33 µF will extend according to the increment. PARAMETER MODE OBCAP MIN. MAX. UNIT 20 MHz 0.033 µF 7.6 20 MHz Available mode sampling 0.033 µF 5.8 15 MHz 15 MHz frequency 0.1 µF 2.2 5.7 MHz mode 0.33 µF 0.6 1.7 MHz 23 IR3Y48M TOTAL GAIN PARAMETER Min. gain At normal operation Max. gain Gain step Min. gain At ADIN operation Max. gain Gain step SYMBOL CONDITIONS Gain between GMNN GMXN GST GMNNA GMXNA GSTA ERPA REFIN/CCDIN and MONOUT Gain between ADIN and MONOUT MIN. –1.9 TYP. –0.9 MAX. 0.1 UNIT dB dB dB dB dB dB LSB 1 NOTE 1 34.906 35.906 36.906 0 0.094 0.188 –1.3 –0.3 0.7 22.906 23.906 24.906 0 0.094 0.188 ±1 CDS and AGC total gain relative accuracy 2 NOTES : 1. Gain is specified for gain between AGC input and MONOUT output. 2. Gain measured at MONOUT pin. A/D CONVERTER CIRCUIT PARAMETER Resolution Integral non-linearity Differential non-linearity S/N S/ (N+D) ADC common voltage VREF voltage (positive) VREF voltage (negative) ADC output black level calibration code Black level step SYMBOL RES INL DNL SN SND VCOM VRP VRN CCAL STCAL CONDITIONS fs = 20 MHz (At 20 MHz mode) fs = 15 MHz (At 15 MHz mode) (fS = 20 MHz. Signal is given to ADIN.) MIN. TYP. MAX. 10 ±2.5 ±1.0 UNIT bits LSB LSB dB dB 1.2 1.45 0.95 127 1 V V V LSB LSB 1 NOTE ±1.5 ±0.5 58 56 1.0 1.25 0.75 16 1.1 1.35 0.85 NOTE : 1. Black level calibration period (tBKCAL) is specified for code = 16 to 127 LSB. Although black level code of 1 to 15 could be set, tBKCAL is not guaranteed for these codes. 24 IR3Y48M Switching Characteristics (AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C, CL < 10 pF) PARAMETER Conversion speed Clock cycle period Clock rise time Clock fall time Clock low period Clock high period Min. reference pulse Min. data pulse Reference sampling delay Data sampling delay Reference pulse setup Data pulse setup Reference pulse hold Data pulse hold Enable pulse setup Enable pulse hold Tristate disable delay Tristate enable delay ADC output data delay SYMBOL fS tCYC tR tF tL tH tWR tWD tDR tDD tSUR tSUD tHR tHD tSUE tHE tDLD tDLE tDL1 tDL2 Active/High-Z High-Z/Active 2 35 –3 –3 5 5 10 10 20 20 CONDITIONS MIN. 0.5 50 (30%/70%) AVDD, DVDD (70%/30%) AVDD, DVDD 23 23 10 10 4 4 2 2 TYP. MAX. 20 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 2 NOTE NOTES : 1. When SHR› is earlier than ADCKfi, assumed positive. (In the above table, SHR› can be delayed a maximum of 3 ns behind ADCKfi.) 2. When SHD› is earlier than ADCK›, assumed positive. (In the above table, SHD› can be delayed a maximum of 3 ns behind ADCK›.) 25 IR3Y48M TIMING CHART tDR CCD Reference sampling Data sampling tDD tWR tHR tSUR SHR tWD SHD tH ADCK tDL DO0-DO9 tHE BLK OBP CCDCLP ADCLP tSUE tHD tSUD tCYC tL ADIN : ADC Direct Input ADCK 0.3AVDD 0.7AVDD N+1 ADC Input N tDL1 Sampling Point N+5 N+4 N+6 5.5 clk delay 0.7DVDD Digital Output N–6 N–5 N–2 N–1 N 0.3DVDD tDL2 26 IR3Y48M [When ADCK Inverted by Register] 0.7AVDD ADCK 0.3AVDD N+1 ADC Input N N+5 N+4 tDL1 N+6 6.0 clk delay Sampling Point 0.7DVDD Digital Output N–6 N–5 N–2 N–1 N 0.3DVDD tDL2 NOTE : At default condition of ADIN mode, falling edge of sampling and rising edge of data out are selected. If each edge should be a rising edge, invert the ADCK by register setting. (The figure shown on the previous page is the default, the following is the inverted one.) Clock Waveform tH 0.7AVDD 0.3AVDD tR tF tL tCYC 27 IR3Y48M CONTROL INTERFACE TIMING (AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C) PARAMETER SCK clock cycle time SCK clock low width SCK clock high width Setup time Hold time SCK, CSN rise time SCK, CSN fall time Serial data number SYMBOL fSCYC tSLO tSHI tSSU tSH tSR tSF SNUM 30%/70% 70%/30% 16 CONDITIONS MIN. 40 40 20 20 6 6 TYP. MAX. 10 UNIT MHz ns ns ns ns ns ns pcs CSN tSSU 50%DVDD fSCYC tSLO tSHI tSH SCK 50%DVDD tSSU tSH O0 SDATA O1 A0 π D8 D9 50%DVDD SNUM Serial I/F Timing Digital DC Characteristics (AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TOPR = –30 to +85 ˚C, measured as DC characteristics.) PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage "High" leakage current High-Z leakage current SYMBOL VIL1 VIH1 VOL VOH ILING IOZ CONDITIONS MIN. 0.7AVDD IOL = 1 mA IOH = –1 mA 0.7DVDD ±10 ±10 0.3DVDD TYP. MAX. UNIT 0.3AVDD V V V V µA µA NOTE 1 NOTE : 1. Specified for SHD, SHR, ADCK, BLK, OBP, CCDCLP, ADCLP, CSN, SCK, SDATA, RESETN, STBYN, and OP. 28 IR3Y48M Data Output Sequence CCD 0 SHR SHD 1 2 3 4 5 6 7 8 ADCK BLK DO0-DO9 Black Level Code 0 1 2 3 Pixel Data Readout Sequence (1) : Conversion Start CCD (N – 1) SHR SHD (N) ADCK BLK DO0-DO9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N Pixel Data Readout Sequence (2) : Conversion End 29 IR3Y48M APPLICATION CIRCUIT EXAMPLE The following schematic is the reference circuit for system design. Optimize capacitance and resistance according to the system environment. CHIP CONTROL ANALOG DIGITAL 36 OP 37 DO0 38 DO1 39 DO2 40 DO3 41 DO4 42 DVSS DIGITAL OUT 0.1 µF 43 DVDD 44 DO5 45 DO6 46 DO7 47 DO8 35 RESETN 34 AVDD3 33 AVSS3 32 STBYN 31 CSN 0.1 µF SIO CONTROL PULSE 30 SDATA 29 SCK 28 OBP 27 CCDCLP 26 BLK 25 ADCLP SHD 24 SAMPLING PULSE SHR 23 ADCK 22 NC 21 AVSS1 20 0.1 µF AVDD1 19 TOP VIEW 4.7 k$ AISET 18 NC 17 MONOUT 16 0.033 µF OBCAP 15 ADIN 14 CCDIN REFIN CLPCAP 13 ADIN 0.1 µF 0.1 µF MONITOR 48 DO9 AVDD4 AVDD2 AVDD2 AVSS2 AVSS2 9 0.1 µF VCOM 10 0.1 µF VRN 4 0.1 µF VRP 5 0.1 µF NC NC 3 0.1 µF 1 10 µF + 3 V (TYP.) 2 6 7 8 11 12 0.1 µF 0.1 µF CCD 30 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE 48 QFP (QFP048-P-0707) (Unit : mm) 0.5TYP. 36 M 37 0.08 0.2±0.08 (1.0) 25 24 7.0±0.2 9.0±0.3 0.15±0.05 1 (1.0) 7.0±0.2 9.0±0.3 12 (1.0) (1.0) 48 13 0.65±0.2 1.45±0.2 0.1±0.1 31 Package base plane 8.0±0.2 0.1