LH28F016SCT-L95

LH28F016SCT 16M Flash Memory Data Sheet FEATURES DESCRIPTION • SmartVoltage Technology – 2.7 V (Read Only), 3.3 V or 5 V VCC – 3.3 V, 5 V, or 12 V VPP SHARP’s LH28F016SCT Flash memory with SmartVoltage technology is a high density, low cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically blocked architecture, flexible voltage, and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code and data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F016SCT offers three levels of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. • High Performance Read Access Time – 95 ns (5 V ±0.25 V) – 100 ns (5 V ±0.5 V) – 120 ns (3.3 V ±0.3 V) – 150 ns (2.7 V - 3.6 V) • High Density Symmetrically-Blocked Architecture – Thirty-two 64KB Erasable Blocks • Low Power Management – Deep Power Down Mode – Automatic Power Savings Mode Decreases ICC in Static Mode • Enhanced Data Protection Features – Absolute Protection with VPP = GND – Flexible Block Locking – Block Erase/Byte Write Lockout during Power Transitions • Automated Byte Write and Block Erase – Command User Interface – Status Register • Enhanced Automated Suspend Options – Byte Write Suspend to Read – Block Erase Suspend to Byte Write – Block Erase Suspend to Read • Extended Cycling Capability – 100,000 Block Erase Cycles – 3.2 Million Block Erase Cycles/Chip • SRAM Compatible Write Interface • Industry Standard Packaging – 40-Lead TSOP • Operating Temperature – 0°C to +70°C • ETOX™ Nonvolatile Flash Technology • CMOS Process (P-type Silicon Substrate) • Not Designed or Rated as Radiation Hardened The LH28F016SCT is manufactured on SHARP’s 0.38 µm ETOX™ V process technology. Available in the industry-standard package of 40-lead TSOP, it is ideal for board-constrained applications. The LH28F0016SCT is based on the 28F008SA architecture, and is a quick and easy upgrade for designs demanding the state-of-the-art. 40-PIN TSOP TOP VIEW A19 1 40 A20 A18 2 39 NC A17 3 38 WE A16 4 37 OE A15 5 36 RY/BY A14 6 35 DQ7 A13 7 34 DQ6 A12 8 33 DQ5 CE 9 32 DQ4 VCC 10 31 VCC VPP 11 30 GND RP 12 29 GND A11 13 28 DQ3 A10 14 27 DQ2 A9 15 26 DQ1 A8 16 25 DQ0 A7 17 24 A0 A6 18 23 A1 A5 19 22 A2 A4 20 21 A3 28F016SCT-L95-1 Figure 1. LH28F016SCT Pinout * ETOX is a trademark of Intel Corporation. Data Sheet 1 LH28F016SCT 16M Flash Memory DQ7 - DQ0 INPUT BUFFER OUTPUT BUFFER I/O LOGIC IDENTIFIER REGISTER OUTPUT MULTIPLEXER STATUS REGISTER DATA REGISTER COMMAND REGISTER VCC CE WE OE RP DATA COMPARATOR WRITE STATE MACHINE INPUT BUFFER ADDRESS LATCH Y-DECODER Y GATING X DECODER 32 64KB BLOCKS ... A20 - A0 PROGRAM/ ERASE VOLTAGE SWITCH RY/BY VPP VCC GND ADDRESS COUNTER ... 28F016SCT-L95-2 Figure 2. LH28F016SCT Block Diagram 2 Data Sheet 16M Flash Memory LH28F016SCT Table 1. Pin Descriptions SYMBOL TYPE DESCRIPTION A20 - A0 Input Address Inputs Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. Data Input/Outputs Inputs data and commands during CUI write cycles; outputs data durInput/ ing memory array, status register, and identifier code read cycles. Data pins float to highDQ7 - DQ0 Output impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. Input Chip Enable Activates the device’s control logic, input buffers, decoders, and sense amplifiers. CE HIGH deselects the device and reduces power consumption to standby levels. RP Input Reset/Deep Power-down Puts the device in deep power-down mode and resets internal automation. RP HIGH enables normal operation. When driven LOW, RP inhibits write operations which provides data protection during power transitions. Exiting from deep powerdown sets the device to read array mode. RP at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP = VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIH < RP < VHH produce spurious results and should not be attempted. OE Input Output Enable WE Input Write Enable Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE pulse. CE Gates the device’s outputs during a read cycle. RY/BY Read/Busy Indicates the status of the internal WSM. When LOW, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY HIGH indiOutput cates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY is always active and does not float when the chip is deselected or data outputs are disabled. VPP Block Erase, Byte Write, Lock Bit Configuration Power Supply For erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VPPLK, memory contents cannot be Supply altered. Block erase, byte write, and lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and should not be attemped. VCC Device Power Supply Internal detection configures the device for 2.7 V, 3.3 V, or 5 V operation. To switch from one voltage to another, ramp VCC down to GND and then ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write attempts to Supply the flash memory are inhibited. Device operations at invalid VCC voltage (see ‘DC Characteristics) produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with VCC < 3.0 V are not supported. GND Supply Ground NC Data Sheet Do not float any ground pins. Non-connect Lead is not internal connected; it may be driven or floated. 3 LH28F016SCT 16M Flash Memory OVERVIEW SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 2, to meet system performance and power expectations. 2.7 V VCC consumes approximately one-fifth the power of 5 V VCC, VPP at 3.3 V, and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK. The LH28F160SCT-L95 is a high-performance 16M SmartVoltage Flash memory organized as 2MB × 8 bits. The 2MB of data is arranged in thirty-two 64KB blocks which are indivdually eraseable, lockable, and unlockable in-system. The memory map is shown in Figure 3. 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 31 64KB BLOCK 30 64KB BLOCK 29 VCC VOLTAGE 64KB BLOCK 28 2.7 V (See Note) 64KB BLOCK 27 3.3 V 3.3 V, 5 V, 12 V 64KB BLOCK 26 5V 5 V, 12 V 64KB BLOCK 25 64KB BLOCK 24 64KB BLOCK 23 64KB BLOCK 22 64KB BLOCK 21 64KB BLOCK 20 64KB BLOCK 19 64KB BLOCK 18 64KB BLOCK 17 64KB BLOCK 16 64KB BLOCK 15 64KB BLOCK 14 64KB BLOCK 13 64KB BLOCK 12 64KB BLOCK 11 64KB BLOCK 10 64KB BLOCK 9 64KB BLOCK 8 64KB BLOCK 7 64KB BLOCK 6 64KB BLOCK 5 64KB BLOCK 4 64KB BLOCK 3 64KB BLOCK 2 64KB BLOCK 1 64KB BLOCK 0 28F016SCT-L95-3 Figure 3. Memory Map 4 Table 2. VCC and VPP Voltage Combinations Offered by SmartVoltage Technology 64KB BLOCK VPP VOLTAGE NOTE: Block erase, byte write and lock-bit configuration operations with VCC < 3 V are not supported. Internal VCC and VPP detection cicuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interfaces between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device’s 64KB blocks typically within 1 second (5 V V CC , 12 V VPP) independent of other blocks. Each block can be independently erased 100,000 times. (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read from or write data to any other block. Writing memory data is performed in byte increments typically within 6 µs (5 V VCC, 12 V VPP). Byte write suspend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits, thirty-two block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit confifuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM’s block erase, byte write, or lock-bit configuration operation is finished. Data Sheet 16M Flash Memory The RY/BY output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY minimizes both CPU overhead and system power consumption. When LOW, RY/BY indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY HIGH indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte is suspended, (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 95 ns (tAVQV) over the commerical temperature range (0°C to 70°C) and VCC supply voltage range of 4.75 V - 5.25 V. At lower VCC voltages, the access times are 100 ns (4.5 V - 5.5 V), 120 ns (3.0 V - 3.6 V) and 150 ns (2.7 V - 3.6 V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (address not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC. When CE and RP pins are at VCC, the ICC CMOS standby mode is enabled. When the RP pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during Reset. A reset time (tPHQV) is required from RP going HIGH until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP HIGH until writes to the CUI are recognized. With RP at GND, the WSM is reset and the status register is cleared. The device is available in 40-pin TSOP packaging. Pinout is as shown in Figure 1. PRINCIPLES OF OPERATION The LH28F016SCT SmartVoltage flash memory includes an on-chip Write State Machine (WSM) to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal process overhead with RAM-like interface timings. After initial device power-up or return from Reset mode (see ‘Bus Operations’ section), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. LH28F016SCT and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erase, byte writes, or lock-bit configurations are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimaization of the processor-memory interface. When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with the two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, and byte write operations. BUS OPERATION The local CPU reads and writes the flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Status register and identifier codes can be accessed through the Command User Interface (CUI), independent of the VPP voltage. High voltage on VPP enables successful block erase, byte writing, and lock-bit configuration. All functions associated with altering memory contents-block erase, byte write, lock-bit configuration, status, and identifier codes are accessed via the CUI Data Sheet 5 LH28F016SCT Read Information, identifier codes, or a status register can be read from any block, independent of the VPP voltage. RP can be either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device powerup or after exit from deep power-down mode, the device automatically resets to Read Array mode. Four control pins dictate the data flow in and out of the device: CE , OE, WE, RP, and RP. CE and OE must be driven active to obtain data at the outputs. CE is the device selection control and when active enables the selected memory device. OE is the data output (DQ7 DQ 0 ) control and when active, drives the selected memory data onto the I/O bus. WE must be at VIH or VHH. See Figure 15 for Read Cycle waveforms. Output Disable 16M Flash Memory information when accessed during block erase, byte write or block lock bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP input. For this application, RP is controlled by the same RESET signal that resets the system CPU. Read Identifier Codes The Read Identifier Codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and the master lock-bit setting. With OE at a logic-high level (VIH), the device outputs are disabled. Output pins DQ7 - DQ0 are placed in a high-impedance state. 1FFFFF Standby CE at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ7 - DQ0 outputs are placed in a high-impedance state independent of OE. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. Deep Power-down RESERVED FOR FUTURE IMPLEMENTATION 1F0004 1F0003 1F0002 BLOCK 31 LOCK CONFIGURATION CODE 1F0001 RESERVED FOR FUTURE IMPLEMENTATION BLOCK 31 1F0000 . . . 01FFFF RP at VIL initiates the deep power-down mode. In read modes, RP LOW deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP must be held LOW for a minimum of 100 ns. Time tPHQV is required after the return from power-down mode until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to Read Array mode and status register is set to 80H. During block erase, byte write, or lock bit configuration modes, RP at LOW will abort the operation. RY/BY remains LOW until the Reset operation is complete. Memory contents in the process of being altered are no longer valid; data may be partially erased or written. Time tPHWL is required after RP goes HIGH (VIH) before another command can be written. As with any automated device, it is important to assert RP during system reset. When the system comes out of Reset, it expects to read from the flash memory. Automated flash memories provide status 6 . . . (BLOCKS 2 THROUGH 30) RESERVED FOR FUTURE IMPLEMENTATION 010004 010003 010002 BLOCK 1 LOCK CONFIGURATION CODE 010001 RESERVED FOR FUTURE IMPLEMENTATION BLOCK 1 010000 00FFFF RESERVED FOR FUTURE IMPLEMENTATION 000004 000003 MASTER LOCK CONFIGURATION CODE 000002 BLOCK 0 LOCK CONFIGURATION CODE 000001 000000 DEVICE CODE MANUFACTURER CODE BLOCK 0 28F016SCT-L95-4 Figure 4. Device Identifier Code Memory Map Data Sheet 16M Flash Memory LH28F016SCT Write Writing commands to the CUI controls the reading of device data and identifier codes. They also control inspection and clearing of the status register. When VPP = VPP1/2/3 the CUI also controls block erase, byte write and block write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/Byte Write command requires the command and address of the location to be written. Set Block Lock Bit commands require the command and block address within the device (Block Lock) to be locked. The Clear Block Lock bits command requires the command and an address within the device. The CUI does not occupy an addressable memory location. It is written when WE and CE are active. The address and data needed to execute a command are latched on the rising edge of WE or CE (whichever goes HIGH first). Standard microprocessor write timing is used. Figures 16 and 17 illustrate WE and CE controlled write operations. Table 3. Bus Operations MODE RP CE OE WE ADDRESS VPP DQ7 - DQ0 RY/BY NOTES Read VIH or VHH VIL VIL VIH x x DOUT x 1, 2, 3, 8 Output Disable VIH or VHH VIL VIH VIH x x High-Z x 3 Standby VIH or VHH VIH x x x x High-Z x 3 VIL x x x x x High-Z VOH 4 VIL VIL VIH See Figure 4 x See Note 5 VOH 8 VIL VIH VIL x x DIN x 3, 6, 7, 8 Deep Power-down Read Identifier Codes VIH or VHH Write VIH or VHH NOTES: 1. x = don’t care. When VPP ≤ VPPLK, memory contents can be read, but not altered. Refer to DC Characteristics. 2. ‘x’ (don’t care) can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/32 for VPP. For VPPLK and VPPH1/2/3 voltages see DC Characteristics. 3. RY/BY is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. 4. RP at GND +0.2 V ensures the lowest deep power-down current. 5. See the Read Identifier Codes Command section. 6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and VCC = VCC2/3/4. Block erase, byte write, or lock-bit configuration with VCC < 3.0 V or VIH < RP < VHH produce spurious results and should not be attemped. 7. See Table 4 for valid DIN during a write operation. 8. Do not hold both OE and WE at VIL at the same time. Data Sheet 7 LH28F016SCT 16M Flash Memory COMMAND DEFINITIONS When VPP ≤ VPPLK, Read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Table 4. Command Definitions BUS CYCLES REQUIRED OPER.1 ADDR. 1 Write x FFH Read Identifier Codes ≥2 Write x Read Status Register 2 Write Clear Status Register 1 Write Block Erase 2 Byte Write 2 COMMAND Read Array/Reset FIRST BUS CYCLE 2 SECOND BUS CYCLE 3 NOTES OPER.1 ADDR.2 DATA3 90H Read IA ID x 70H Read x SRD x 50H Write BA 20H Write BA D0H 5 Write WA 40H or 10H Write WA WD 5, 6 DATA 4 Block Erase and Byte Write Suspend 1 Write x B0H 5 Block Erase and Byte Write Resume 1 Write x D0H 5 Set Block Lock-Bit 2 Write BA 60H Write BA 01H 7 Set Master Lock-Bit 2 Write x 60H Write x F1H 7 Clear Block Lock-Bits 2 Write x 60H Write x D0H 8 NOTES: 1. Bus operations are defined in Table 3. 2. x = don’t care; in this case, any valid address within the device. IA = Identifier Code Address, see Figure 4. BA = Address within the block being erased or locked. WA = Address of memory location to be written. 3. SRD = Data read from status register. For a description of the status register bits see Table 7. WD = Data to be written at location WA. Data is latched on the rising edge of WE or CE (whichever goes HIGH first). ID = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. For read identifier code data see ‘Read Identifier Codes Command’ section. 5. If the block is locked RP must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP is VIH will fail. 6. Either 40H or 10H is recognized by the WSM as the byte write setup. 7. If the master lock-bit is set, RP must be at VHH to set a block lock-bit. RP must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP is VIH. 8. If the master lock-bit is set, RP must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP is VIH. 9. Commands other than those shown in Table 4 are reserved by SHARP for future device implementations and should not be used. 8 Data Sheet 16M Flash Memory LH28F016SCT Read Array Command Read Status Register Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to Read Array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP must be VIH or VHH. The status register may be read to determine when a block erase, byte write or block lock bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE or CE whichever occurs first. OE or CE must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP must be VIH or VHH. Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Table 5 for identifier code values). To terminate the operation, write another valid command, such as a Read Array command. The Read Identifier Codes command functions independently of the VPP voltage and RP must be at VIH or VHH. After issuing the the Read Identifier Codes command, the information can be read: Table 5. Identifier Codes CODE ADDRESS DATA Manufacturer Code 00000 89 Device Code 00001 AA Block Lock Configuration x0002* Block is Unlocked DQ0 = 0 Block is Locked DQ0 = 1 DQ7 = DQ1 Reserved for Future Use Master Lock Configuration Block is Unlocked Device is Locked Reserved for Future Use 00003 DQ0 = 0 DQ0 = 1 DQ7 = DQ1 NOTE: *‘x’ Selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. Data Sheet Clear Status Register Command When status register bits SR.5, SR.4, SR.3, or SR.1 are set to ‘1’ by the WSM, they can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP can be VIH or VHH. This command does not function during block erase or byte write suspend modes. Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing plus an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the RY/BY pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. 9 LH28F016SCT This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to ‘1’. Also reliable block erasure can only occur when VCC = VCC2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to ‘1’. Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP = VHH. If block erase is attempted when the corresponding block lockbit is set and RP = VHH, SR.1 and SR.5 will be set to ‘1’. Block erase operations with VIH < RP < VHH produce spurious results and should not be attempted. Byte Write Command Word/Byte writes are executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect the completion of the byte write event by analyzing the RY/BY pin or status register bit SR.7. When the byte write is complete, status register bit SR.4 should be checked. If a byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for ‘1’ bits that do not successfully write to ‘0’. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when VCC = VCC2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against byte writes. If a byte write is attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to ‘1’. A successful byte write requires that the corresponding block lock bit be cleared or, if set, that the corresponding block lock-bit be cleared or, if set, that RP = VHH. If byte write is attempted when the corresponding block lock-bit is set and RP = VIH, SR.1 and SR.4 will be set to ‘1’. Byte write operations with VIH < RP < VHH produce spurious results and should not be attempted. 10 16M Flash Memory Block Erase Suspend Command The Block Erase Suspend command allows blockerase interruption to read or byte-write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to ‘1’). RY/BY will also transition to VOH. Specification tWHRh2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which are suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte Write Suspend command, a (multi) word/byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to ‘0’ and the RY/BY output will transition to VOL. However, SR.6 will remain ‘1’ to indicate the block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 7). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP must also remain at VIH or VHH. (the same RP level used for block erase). Block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. Data Sheet 16M Flash Memory Byte Write Suspend Command The Byte Write Suspend command allows for a byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to ‘1’). RY/BY will also transition to VOH. The timing of tWHRH1 defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which are suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After the Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY will return to VOL. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 8). VPP must remain at VPPH1/2/3 (the same VPP level used for byte write) while in byte write suspend mode. RP must also remain at VIH or VHH. (the same RP level used for write). Set Block and Master Lock Bit Commands A flexible block locking and unlocking scheme is implemented via a combination of block lock bits and a master lock bit. The block lock bits gate program and erase operations while the master lock bit gates block lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP pin. See Table 6 for a summanry of hardware and software write protection options. Data Sheet LH28F016SCT The set block lock bit is executed by a two-cycle command sequence. The set block or master lock bit setup along with appropriate block or device address is written followed by the set block lock bit confirm (and an address within the block to be locked) or the set master lock bit confirm (and any device address). The WSM then controls the set block lock bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 9). The CPU can detect the completion of the set lock bit event by analyzing the RY/BY pin output or status register bit SR.7. When the set lock bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that block lock bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to ‘1’. Also, reliable operations occur only when VCC = VCC2/3/4 and VPPW = VPPH1/2/3. In the absence of this high voltage, lock bit contents are protected against alteration. A successful set block lock bit operation also requires that the master lock bit be cleared or, if the master lock bit is set, that RP = VHH. If it is attempted with the master lock bit set and RP = VIH, SR.1 and SR.4 will be set to ‘1’ and the operation will fail. Set block lock bit operations while VIH < RP < VHH produce spurious results and should not be attempted. A successful set master lock bit operation requires that RP = VIH. If it is attempted with RP = VIH , SR.1 and SR.4 will be set to ‘1’ and the operation will fail. Set master lock bit operations with VIH < RP < VHH produce spurious results and should not be attempted. 11 LH28F016SCT 16M Flash Memory Clear Block Lock Bit Command All set block lock bits are cleared in parallel via the Clear Block Lock Bits command. With the master lock bit cleared, block lock bits can be cleared using only the Clear Block Lock Bits command. If the master lock bit is set, clearing block lock bits requires both the Clear Block Lock Bits command and VHH on the RP pin. See Table 6 for a summary of hardware and software write protection options. The Clear Block Lock Bits operation is executed by a two-cycle command sequence. First, a clear block lock bit setup code is written. After the command is written, the device automatically outputs status register data when read (see Figure 10). The CPU can detect completion of the clear block lock bit event by analyzing the RY/BY pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock bits are not accidentally cleared. An invalid Clear Block Lock bits command sequence will fail, and result in status register bits SR.4 and SR.5 being set to ‘1’. Also, a reliable clear block lock bits operation can only occur when VCC = VCC2/3/4 and VPP = VPP1/2/3. If a clear block lock bits operation is attempted while VPP ≤ VPPLK, it will fail. SR.3 and SR.5 will be set to ‘1’. In the absence of this high voltage, the block lock bits are protected against alteration. A successful clear block lock bits operation requires that the master lock bit is cleared or, if the master lock bit is set, that RP = VHH. If it is attempted with the master lock-bit set and RP = VIH, SR.1 and SR.5 will be set to ‘1’ and the operation will fail. A clear lock bits operation with VIH < RP < VHH produce spurious results and should not be attempted. If a clear block lock bits operation is aborted due to a VPP or VCC transition out of valid range or a RP active transition, block lock bit values are left in an unpredictable state. A repeat of the clear block lock bits operation is required to initialize block lock bit contents to known values. Once the master lock bit is set, it cannot be cleared. Table 6. Write Protection Methods OPERATION MASTER BLOCK LOCK BIT LOCK-BIT 0 Block Erase or Byte Write Set Block Lock Bit Set Master Lock Bit Clear Block Lock Bits 12 x 1 0 x 1 x x x 0 x 1 x RP EFFECT VIH or VHH Block Erase and Byte Write enabled VIH Block is locked. Block Erase and Byte Write disabled VHH Block Lock Bit override. Block Erase and Byte Write enabled VIH or VHH Set Block Lock Bit enabled VIH Master Lock Bit is set. Set Block Lock Bit disabled VHH Master Lock Bit override. Set Block Lock Bit enabled VIH Set Master Lock Bit disabled VHH Set Master Lock Bit enabled VIH or VHH Clear block lock bits enabled VIH Master Lock Bit is set. Clear Block Lock Bits disabled VHH Master Lock Bit override. Clear Block Lock Bits enabled Data Sheet 16M Flash Memory LH28F016SCT Status Register 7 6 5 4 3 2 1 0 WSMS ESS ECLBS BWSLBS VPPS BWSS DPS /// Table 7. Status Register Definitions REGISTER NUMBER REGISTER SYMBOL SR.7 WSMS SR.6 ESS SR.5 ECLBS SR.4 BWSLBS SR.3 DEFINITION Write State Machine Status 1 = Ready 0 = Busy NOTES 1 Erase Suspend Status 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed Erase and Clear Lock Bits Status 1 = Error in Block Erase, or Clear Block Lock Bits 0 = Successful Block Erase, or Clear Block Lock Bits 2 Byte Write and Set Lock Bit Status 1 = Error in Byte Write or Set Block Lock Bit 0 = Successful Byte Write or Set Master/Block Lock Bit 2 VPPS VPP Status 1 = VPP Low Detect, Operation Abort 0 = VPP OK 3 SR.2 BWSS Byte Write Suspend Status 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 DPS SR.0 /// Device Protect Status 1 = Block Lock Bit, Block lock bit and/or RP lock detected, operation abort 0 = Unlock 4 Reserved for Future Enhancements 5 NOTES: 1. Check RY/BY or SR.7 to determine block erase, byte write or block lock bit configuration completion. SR.6 - SR.0 are invalid while SR.7 = 0. 2. If both SR.5 and SR.4 =1 after a block erase, or block lock bit configuration attempt, an improper command sequence was entered. 3. SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after block erase, byte write, set block/master or lock bit or Clear Block lock bits command sequences. SR.3 does not report accurate feedback when VPP ≠ VPPH1/2/3. 4. SR.1 does not provide a continuous indication of master and block lock bit values. The WSM interrogates the master lock bit, block lock bit, and RP only after block erase, byte write, or lock bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set, master lock bit is set, and/or RP is not VHH. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock bit status. 5. SR.0 is reserved for future use and should be masked out when polling the status register. Data Sheet 13 LH28F016SCT 16M Flash Memory START WRITE 20H, BLOCK ADDRESS WRITE D0H, BLOCK ADDRESS BUS OPERATION COMMAND Write Erase Setup Data = 20H Addr = Within Block to be Erased Write Erase Confirm Data = D0H Addr = Within Block to be Erased Read READ STATUS REGISTER NO SR.7 = 0 SUSPEND BLOCK ERASE SUSPEND BLOCK ERASE LOOP YES 1 FULL STATUS CHECK IF DESIRED COMMENTS Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place the device into read array mode. BLOCK ERASE COMPLETE FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above) SR.3 = 1 BUS OPERATION 1 Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP = VIH, Block Lock-Bit is Set. Only required for systems implementing lock-bit configuration. Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error VPP RANGE ERROR DEVICE PROTECT ERROR 0 SR.4, 5 = 1 COMMAND SEQUENCE ERROR 0 SR.5 = 1 BLOCK ERASE ERROR COMMENTS Standby 0 SR.1 = COMMAND CSR.5, SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If an error is detected, clear the Status Register before attempting a retry or other error recovery operations. 0 BLOCK ERASE SUCCESSFUL 28F016SCT-L95-5 Figure 5. Automated Block Erase Flowchart 14 Data Sheet 16M Flash Memory LH28F016SCT START WRITE 40H, ADDRESS WRITE BYTE DATA and ADDRESS BUS OPERATION COMMAND Write Setup Byte Write Data = 40H Addr = Location to be Written Write Byte Write Data = Data to be Written Addr = Location to be Written Read READ STATUS REGISTER NO SR.7 = 0 SUSPEND BYTE WRITE SUSPEND BYTE WRITE LOOP YES 1 FULL STATUS CHECK IF DESIRED COMMENTS Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent byte writes. SR full status check can be done after each byte write, or after a sequence of byte writes. Write FFH after the last byte write operation to place the device into read array mode. BYTE WRITE COMPLETE FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above) SR.3 = 1 BUS OPERATION Standby Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP = VIH, Block Lock-Bit is Set. Only required for systems implementing lock-bit configuration Standby Check SR.4 1 = Data Write Error VPP RANGE ERROR 0 SR.1 = 1 DEVICE PROTECT ERROR 0 SR.4 = 1 0 BYTE WRITE ERROR COMMENTS COMMAND SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If an error is detected, clear the Status Register before attempting a retry or other error recovery operations. BYTE WRITE SUCCESSFUL 28F016SCT-L95-6 Figure 6. Automated Byte Write Flowchart Data Sheet 15 LH28F016SCT 16M Flash Memory START BUS OPERATION COMMAND WRITE B0H Write Erase Suspend READ STATUS REGISTER Read SR.7 = SR.6 = 0 BLOCK ERASE COMPLETED Data = B0H Addr = X Status Register Data Addr = X Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed 0 1 COMMENTS Write Erase Resume Data = D0H Addr = X 1 READ READ ARRAY DATA READ or BYTE WRITE? NO BYTE WRITE BYTE WRITE LOOP DONE? YES WRITE D0H WRITE FFH BLOCK ERASE RESUMED READ ARRAY DATA 28F016SCT-L95-7 Figure 7. Block Erase Suspend/Resume Flowchart 16 Data Sheet 16M Flash Memory LH28F016SCT START BUS OPERATION COMMAND WRITE B0H Write Byte Write Suspend READ STATUS REGISTER Read SR.7 = SR.2 = 0 BYTE WRITE COMPLETED 1 Data = B0H Addr = X Status Register Data Addr = X Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Byte Write Suspended 0 = Byte Write Completed 0 1 COMMENTS Write Read Array Data = FFH Addr = X Read Array locations other than that being written Read WRITE FFH Write Byte Write Resume Data = D0H Addr = X READ ARRAY DATA DONE READING NO YES WRITE D0H WRITE FFH BYTE WRITE RESUMED READ ARRAY DATA 28F016SCT-L95-8 Figure 8. Byte Write Suspend/Resume Flowchart Data Sheet 17 LH28F016SCT 16M Flash Memory START WRITE 60H, BLOCK/DEVICE ADDRESS WRITE 01H/F1H, BLOCK/DEVICE ADDRESS READ STATUS REGISTER SR.7 = BUS OPERATION COMMAND COMMENTS Write Set Block/Master Lock-Bit Setup Data = 60H Addr = Block Address (Block), Device Address (Master) Write Set Block or Master Lock-Bit Confirm Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Read Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby 0 1 Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place the device into read array mode. FULL STATUS CHECK IF DESIRED SET LOCK-BIT COMPLETE FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (See Above) BUS OPERATION Standby SR.3 = 1 VPP RANGE ERROR 0 SR.1 = Standby 1 DEVICE PROTECT ERROR 0 SR.4, 5 = 1 COMMAND SEQUENCE ERROR COMMAND COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP = VIH (Set Master Lock-Bit Operation) RP = VIH, Master Lock-Bit is Set (Set Block Lock-Bit Operation) Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.4 1 = Set Lock-Bit Error 0 SR.4 = 1 0 SET LOCK-BIT ERROR SR.5, SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the Status Register before attempting a retry or other error recovery operations. SET LOCK-BIT SUCCESSFUL 28F016SCT-L95-9 Figure 9. Set Block and Master Lock-bit Flowchart 18 Data Sheet 16M Flash Memory LH28F016SCT START BUS OPERATION COMMAND WRITE 60H Write Clear Block Lock-Bits Setup Write WRITE D0H SR.7 = Data = 60H Addr = X Clear Block Data = D0H Lock-Bits Confirm Addr = X Read READ STATUS REGISTER COMMENTS Status Register Data Check CSR.7 1 = WSM Ready 0 = WSM Busy Standby Write FFH after the Clear Block Lock-Bits operation to place the device into read array mode. 0 1 FULL STATUS CHECK IF DESIRED CLEAR BLOCK LOCK-BITS COMPLETE FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above) SR.3 = 1 BUS OPERATION 1 DEVICE PROTECT ERROR Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP = VIH Master Lock-Bit is Set Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Clear Block Lock-Bits Error 0 SR.4, 5 = 1 COMMAND SEQUENCE ERROR 1 CLEAR BLOCK LOCK-BITS ERROR 0 SR.5 = COMMENTS Standby VPP RANGE ERROR 0 SR.1 = COMMAND SR.5, SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register command. If an error is detected, clear the Status Register before attempting a retry or other error recovery operation. 0 CLEAR BLOCK LOCK-BITS SUCCESSFUL 28F016SCT-L95-10 Figure 10. Clear Block Lock-bits Flowchart Data Sheet 19 LH28F016SCT DESIGN CONSIDERATIONS Three-line Output Control Since this device will often be used in large memory arrays, SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: • Lowest possible memory power dissipation • Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE while OE should be connected to all memory devices and the system’s READ control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. RY/BY and Block Erase, Byte Write, and Block Lock Bit Configuration Polling RY/BY is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock bit configuration completion. It transitions LOW after block erase, byte write, or lock bit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY is also VOH when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE and OE. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 20 16M Flash Memory VPP Trace On Printed Circuit Boards Updating Flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. VCC, VPP, RP Transitions Block erase, full chip erase, (multi) word/byte writes and lock bit configurations are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, if VCC falls outside of a valid VCC1/2 range, or RP ≠ VIL. If a VPP error is detected, status register bit SR.3 is set to ‘1’ along with SR.4 or SR.5, depending on the attempted operation. If RP transitions to VIL during block erase, full chip erase, (multi) word/byte write or block lock bit configuration (RY/BY will remain LOW until the reset operation is complete) the operation will abort and the device will enter reset mode. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE transitions or WSM actions. Upon power-up, its state is read array mode after exiting from reset mode or after VCC transitions below VLKO. After block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after V PP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. Power-Up/Down Protection The device is designed to offer protection against accidental block erase, byte write or block lock bit configuration during power transitions. The device is indifferent as to which power supply (VPP or VCC) powers up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against accidental writes for VCC voltages above VLKO when VPP is active. Since both WE and CE must be LOW for a command write, driving either to VIH will inhibit writes. The CUI’s two-step command sequence architecture provides an added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP = VIL regardless of its control input states. Data Sheet 16M Flash Memory LH28F016SCT Power Dissipation When designing portable systems, designers will consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumpution even when system power needs to remain applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume far less power by lowering RP to V IL standby or sleep modes. If access is needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP is first raised to VIH. See ‘AC Characterstics, Read Only and Write Operations’ and Figures 15, 16, and 17 for more information. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER Operating Temperature CONDITION MIN. MAX. During Read, Block Erase, Byte Write, and Lock Bit Configuration 0°C 70°C Under Bias Storage Temperature Except VCC, VPP, and RP Voltage on any pin VCC Supply Voltage NOTE 1 -10°C 80°C -65°C 125°C -2.0 V 7.0 V 2 -2.0 V 7.0 V 2 VPP Supply Voltage During Block Erase, Byte Write and Lock Bit Configuration -2.0 V 14.0 V 2, 3 RP Voltage With respect to GND during Lock Bit Configuration Operations -2.0 V 14.0 V 2, 3 100 mA 4 Output Short Circuit Current NOTES: 1. ‘Operating temperature’ is for the commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 3. Maximum DC voltage on VPP and RP may overshoot to +14.0 V for periods < 20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. CAUTION Stressing the device beyond the ‘Absolute Maximum Ratings’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘Operating Conditions’ is not recommended and extended exposure beyond the ‘Operating Conditions’ may affect device reliability. Data Sheet 21 LH28F016SCT 16M Flash Memory OPERATING CONDITIONS SYMBOL PARAMETER TA Operating Temperature VCC1 CONDITION MIN. MAX. UNIT Ambient Temperature 0 +70° C VCC Supply Voltage (2.7 V to 3.6 V) 2.70 3.60 V VCC2 VCC Supply Voltage (3.3 V ±0.3 V)* 3.00 3.60 V VCC3 VCC Supply Voltage (5.0 V ±0.25 V) 4.75 5.25 V VCC4 VCC Supply Voltage (5.0 V ±0.50 V) 4.50 5.50 V NOTE: *Block erase, byte write and lock-bit configuration operations with VCC < 3.0 V should not be attempted. CAPACITANCE TA = +25°C, ƒ = 1 MHz SYMBOL PARAMETER CONDITION TYP. MAX. UNIT CIN Input Capacitance VIN = 0.0 V 6 8 pF COUT Output Capacitance VOUT = 0.0 V 8 12 pF NOTE: Sampled, not 100% tested. AC Input/Output Test Conditions TEST POINTS TEST POINTS 2.7 INPUT 1.35 1.35 OUTPUT 2.4 INPUT 0.0 0.45 NOTE: AC test inputs are driven at 2.7 V for a Logic ‘1’ and 0.0 V for a Logic ‘0’. Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns. 28F016SCT-L95-11 Figure 11. Transient Input/Output Reference Waveform for VCC = 2.7 V - 3.6 V 2.0 0.8 2.0 0.8 OUTPUT NOTES: 1. AC test inputs are driven at VOH (2.4 VTTL) for a Logic ‘1’ and VOL (0.45 VTTL) Logic ‘0’. Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends, at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. 2. VCC = 5 V ± 0.5 V. 28F016SCT-L95-13 Figure 13. Transient Input/Output Reference Waveform (Standard Speed Testing Configuration) TEST POINTS 3.0 INPUT 1.5 1.5 1.3 V OUTPUT 0.0 NOTES: 1. AC test inputs are driven at 3.0 V for a Logic ‘1’ and 0.0 V for a Logic ‘0’. Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. 2. VCC = 3.3 V ± 0.3 V and VCC = 5 V ± 0.25 V. 28F016SCT-L95-12 Figure 12. Transient Input/Output Reference Waveform (High Speed Testing Configuration) 1N914 RL = 3.3 kΩ DEVICE UNDER TEST OUT CL Table 8. Test Configuration 22 PARAMETER VALUE VCC = 3.3 V ±0.3 V, 2.7 V - 3.6 V 50 CL (pF) VCC = 5 V ±0.25 V 30 CL (pF) VCC = 5 V ±0.50 V 30 CL (pF) NOTE: CL Includes Jig Capacitance 28F016SCT-L95-14 Figure 14. Transient Equivalent Testing Load Circuit Data Sheet 16M Flash Memory LH28F016SCT Table 9. DC Characteristics SYMBOL PARAMETER ILI Input Load Current ILO Output Leakage Current ICCS VCC Standby Current VCC = 2.7 V VCC = 3.3 V ±0.5 20 VCC Deep PowerDown Current TEST CONDITIONS NOTES µA VCC = VCC MAX., VIN = VCC or GND 1 ±10 µA VCC = VCC MAX., VOUT = VCC or GND 1 100 100 µA CMOS Inputs VCC = VCC MAX., CE = RP = VCC ±0.2 V 2 mA TTL Level Inputs VCC = VCC MAX., CE = RP = VIH 2 20 µA RP = GND = ±0.2 V, IOUT (RY/BY) = 0 mA mA CMOS Inputs VCC = VCC MAX.,CE = GND ƒ = 5 MHz, (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA 12 mA TTL Inputs VCC = VCC MAX., CE = GND ƒ = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA mA VPP = 3.3 V ±0.3 V mA VPP = 5.0 V ±0.5 V ±1 ±0.5 20 0.2 20 6 ICCR ±0.5 ±0.5 0.1 ICCD VCC = 5 V MIN. MAX. MIN. MAX. MIN. MAX. 100 2 25 0.4 20 7 12 17 35 VCC Read Current 7 18 8 18 20 50 17 ICCW ICCE ICCWS ICCES VCC Byte Write or Set Lock Bit Current VCC Byte Write or Block Erase Suspend Current VPP Standby or Read Current IPPD VPP Deep PowerDown Current IPPW VPP Byte Write or Set Lock Bit Current 17 35 12 30 17 VCC Block Erase or Clear Block Lock Bits Current IPPS IPPR IPPWS IPPES Data Sheet VPP = 12.0 V ±0.6 V VPP = 3.3 V ±0.3 V 30 mA VPP = 5.0 V ±0.5 V 12 25 mA VPP = 12.0 V ±0.6 V 1 6 1 10 mA CE = VIH ±2 ±15 ±2 ±15 ±2 ±15 µA VPP ≤ VCC 10 200 10 200 10 200 µA VPP > VCC 0.1 5 0.1 5 0.1 5 µA RP = GND ±0.2 V mA VPP = 3.3 V ±0.3 V 40 40 mA VPP = 5.0 V ±0.5 V 15 15 mA VPP = 12.0 V ±0.6 V mA VPP = 3.3 V ±0.3 V 20 VPP Block Erase or Clear Lock-Bit Current VPP Byte Write or Block Erase Suspend Current mA mA 17 40 IPPE UNIT 10 20 20 mA VPP = 5.0 V ±0.5 V 15 15 mA VPP = 12.0 V ±0.6 V 200 µA VPP = VPPH1/2/3 200 10 1, 3, 6 1 1, 5, 6 1, 7 1, 7 1, 2 1 1 1, 7 1, 7 1 23 LH28F016SCT 16M Flash Memory Table 9. DC Characteristics (Cont’d) SYMBOL VIL PARAMETER Input LOW Voltage VIH Input HIGH Voltage VOL Output LOW Voltage VOH1 Output HIGH Voltage (TTL) VOH2 Output HIGH Voltage (CMOS) VCC = 2.7 V VCC = 3.3 V VCC = 5 V MIN. MAX. MIN. MAX. MIN. MAX. -0.5 0.8 2.0 VCC + 0.5 -0.5 0.8 2.0 VCC + 0.5 0.4 UNIT TEST CONDITIONS NOTES -0.5 0.8 V 7 2.0 VCC + 0.5 V 7 0.45 V VCC = VCC MIN., IOL = 5.8 mA (VCC = 5 V) IOL = 2.0 mA (VCC = 3.3 V, 2.7 V) 3, 7 3, 7 0.4 2.4 2.4 2.4 V VCC = VCC MIN., IOH = -2.5 mA (VCC = 5 V), IOH = -2.0 mA (VCC = 3.3 V), IOH = -1.5 mA (VCC = 2.7 V) 0.85 VCC 0.85 VCC 0.85 VCC V VCC = VCC MIN., IOH = -2.0 mA VCC -0.4 VCC -0.4 VCC ±0.4 V VCC = VCC MIN., IOH = -100 µA 3, 7 VPPLK VPP Lockout during Normal Operations VPPH1 VPP during Byte Write, Block Erase or Lock Bit Operations 3.0 3.6 VPPH2 VPP during Byte Write, Block Erase or Lock Bit Operations 4.5 5.5 4.5 5.5 V VPPH3 VPP during Byte Write, Block Erase or Lock Bit Operations 11.4 12.6 11.4 12.6 V VLKO VCC Lockout Voltage VHH RP Unlock Voltage 1.5 2.0 1.5 2.0 11.4 1.5 4, 7 V 2.0 12.6 V 11.4 V 12.6 V Set master lock bit; override master and block lock bit 8, 9 NOTES: 1. All current values are RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. 2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte codes are written while in erase suspend mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Includes RY/BY. 4. Block erases, byte writes and lock bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between VPPLK (MAX.) and VPPH1 (MIN.), between VPPH1 (MAX.) and VPPH2 (MIN.), between VPPH2 (MAX.) and VPPH3 (MIN.) and above VPPH3 (MAX.). 5. The Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in static operation. 6. CMOS inputs are either VCC ±0.2 V or GND ±0.2 V. TTL inputs are either VIL or VIH. 7. Sampled, not 100% tested. 8. Master lock bit set operations are inhibited when RP = VIH. Block lock bit configuration operations are inhibited when the master lock bit is set and RP = VIH. Block erases and byte writes are inhibited when the corresponding block lock bit is set and RP = VIH. Block erase, byte write, and lock bit configuration operations are not guaranteed with VCC < 3.0 V or VIH < RP < VHH and should not be attempted. 9. RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 24 Data Sheet 16M Flash Memory LH28F016SCT AC CHARACTERISTICS — READ ONLY OPERATIONS(4) VCC = 2.7 V - 3.6 V, TA = 0°C to +70°C (L150) VCC = 3.3 V ±0.3 V, TA = 0°C to +70°C (L120) SYMBOL PARAMETER LH28F016SC-L150 LH28F016SC-L120 MIN. UNIT MIN. ns 120 MAX. MAX. UNIT NOTES tAVAV Read Cycle Time tAVQV Address to Output Delay 150 ns 120 ns tELQV CE to Output Delay 150 ns 120 ns tPHQV RP HIGH to Output Delay 600 ns 600 ns tGLQV OE to Output Delay 50 ns 50 ns 1 tELQX CE to Output in Low-Z ns 2 tEHQZ CE HIGH to Output in High-Z ns 2 tGLQX OE to Output in Low-Z ns 2 tGHQZ OE HIGH to Output in High-Z ns 2 tOH Output Hold from Address, CE or OE Change, Whichever Occurs First ns 2 150 0 ns 55 0 ns 0 55 ns 20 0 ns 0 ns 20 ns 0 1 NOTES: 1. OE may be delayed up to tELQV - tGLQV after the falling edge of CE without impact on tELQV. 2. Sampled, not 100% tested. 3. BYTE mode reads will affect these timings. 4. See ‘AC Input/Output Reference Waveforms’ for maximum allowable input slew rate. VCC = 5 V ±0.5 V, 5 V ±0.25 V, TA = 0°C to +70°C SYMBOL PARAMETER LH28F016SC-L95 MIN. MAX. LH28F016SC-L100 UNIT MIN. ns 100 MAX. UNIT NOTES tAVAV Read Cycle Time tAVQV Address to Output Delay 95 ns 100 ns tELQV CE to Output Delay 95 ns 100 ns tPHQV RP HIGH to Output Delay 400 ns 400 ns tGLQV OE to Output Delay 40 ns 45 ns 1 tELQX CE to Output in Low-Z ns 2 tEHQZ CE HIGH to Output in High-Z ns 2 tGLQX OE to Output in Low-Z ns 2 tGHQZ OE HIGH to Output in High-Z ns 2 tOH Output Hold from Address, CE or OE Change, Whichever Occurs First ns 2 95 0 ns 55 0 10 0 0 ns ns 55 0 ns ns ns 10 0 1 NOTES: 1. OE may be delayed up to tELQV - tGLQV after the falling edge of CE without impact on tELQV. 2. Sampled, not 100% tested. 3. BYTE mode reads will affect these timings. 4. See ‘AC Input/Output Reference Waveforms’ for maximum allowable input slew rate. Data Sheet 25 LH28F016SCT 16M Flash Memory STANDBY ADDRESSES (A) DEVICE ADDRESS SELECTION VIH DATA VALID ADDRESS STABLE VIL tAVAV CE (E) VIH VIL tEHQZ OE (G) VIH VIL tGHQZ WE (W) VIH VIL tGLQV tELQV tGLQX tOH tELQX VOH DATA (D/Q) (DQ7 - DQ0) VOL HIGH-Z VALID OUTPUT HIGH-Z tAVQV VCC tPHQV VIH RP (P) VIL 28F016SCT-L95-15 Figure 15. AC Waveforms for Read Operations 26 Data Sheet 16M Flash Memory LH28F016SCT AC Characteristics WRITE OPERATIONS VCC = 2.7 V - 3.6 V, TA = -40°C to +85°C SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL LH28F016SC-L150 MIN. MAX. UNIT NOTES 150 ns RP HIGH Recovery to WE Going LOW 1 µs tELWL CE Setup to WE Going LOW 0 ns tWLWH WE Pulse Width 70 ns tAVWH Address Setup to WE Going HIGH 50 ns 2 tDVWH Data Setup to WE Going HIGH 50 ns 2 tWHDX Data Hold from WE HIGH 5 ns tWHAX Address Hold from WE HIGH 5 ns tWHEH CE Hold from WE HIGH 0 ns tWHWL WE Pulse Width HIGH 25 ns tWHGL Write Recovery Before Read 0 ns 1 NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase byte write or lock bit configuration. 3. VPP should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, full chip erase, (multi) word/byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. Read timing characteristics during block erase, full chip erase, word/byte write and lock bit configuration operations are the same as during read-only operations. Refer to ‘AC Characteristics’ for read-only operations. Data Sheet 27 LH28F016SCT 16M Flash Memory VCC = 3.3 V ±0.3 V, TA = -40°C to +85°C SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL LH28F016SC-L120 MIN. MAX. UNIT NOTES 120 ns RP HIGH Recovery to WE Going LOW 1 µs tELWL CE Setup to WE Going LOW 0 ns tWLWH WE Pulse Width 70 ns tPHHWH RP VHH Setup to WE Going HIGH 100 tVPWH VCCW Setup to WE Going HIGH 100 ns 1 tAVWH Address Setup to WE Going HIGH 50 ns 2 tDVWH Data Setup to WE Going HIGH 50 ns 2 tWHDX Data Hold from WE HIGH 5 ns tWHAX Address Hold from WE HIGH 5 ns tWHEH CE Hold from WE HIGH 0 ns tWHWL WE Pulse Width HIGH 25 ns tWHRL WE High to RY/BY Going LOW or SR.7 Going ‘0’ tWHGL Write Recovery before Read 0 ns tQVVL VCCW Hold from Valid SRD, RY/BY High-Z 0 ns 1, 3 tQVPH WP VIH Hold from Valid SRD, RY/BY High-Z 0 ns 1, 3 100 1 ns NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase byte write or lock bit configuration. 3. VPP should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, full chip erase, (multi) word/byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. Read timing characteristics during block erase, full chip erase, word/byte write and lock bit configuration operations are the same as during read-only operations. Refer to ‘AC Characteristics’ for read-only operations. 28 Data Sheet 16M Flash Memory LH28F016SCT VCC = 5 V ±0.5 V (L100), 5 V ±0.25 V (L95), TA = -40°C to +85°C SYMBOL PARAMETER LH28F016SC-L95 MIN. MAX. LH28F016SC-L100 MIN. MAX. UNIT NOTES tAVAV Write Cycle Time 95 100 ns tPHWL RP HIGH Recovery to WE Going LOW 1 1 µs tELWL CE Setup to WE Going LOW 0 0 ns tWLWH WE Pulse Width 50 50 ns tPHHWH RP VHH Setup to WE Going HIGH 100 100 tVPWH VCCW Setup to WE Going HIGH 100 100 ns 1 tAVWH Address Setup to WE Going HIGH 40 40 ns 2 tDVWH Data Setup to WE Going HIGH 40 40 ns 2 tWHDX Data Hold from WE HIGH 5 5 ns tWHAX Address Hold from WE HIGH 5 5 ns tWHEH CE Hold from WE HIGH 0 0 ns tWHWL WE Pulse Width HIGH 25 25 ns tWHRL WE High to RY/BY Going LOW or SR.7 Going ‘0’ tWHGL Write Recovery before Read 0 0 ns tQVVL VCCW Hold from Valid SRD, RY/BY High-Z 0 0 ns 1, 3 tQVPH WP VIH Hold from Valid SRD, RY/BY High-Z 0 0 ns 1, 3 90 90 1 ns NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase byte write or lock bit configuration. 3. VPP should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, full chip erase, (multi) word/byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. Read timing characteristics during block erase, full chip erase, word/byte write and lock bit configuration operations are the same as during read-only operations. Refer to ‘AC Characteristics’ for read-only operations. Data Sheet 29 LH28F016SCT 16M Flash Memory 1 ADDRESSES (A) VIH VIL 2 3 AIN AIN tAVAV 4 5 6 tAVWH tWHAX VIH CE (E) VIL tELWL tWHEH OE (G) tWHGL VIH VIL tWHWL tWHQV1,2,3,4 VIH WE (W) VIL tWLWH tDVWH tWHDX DATA (D/Q) VIH HIGH-Z VIL DIN DIN VALID SRD tWHRL tPHWL RY/BY (R) DIN VOH VOL tPHHWH tQVPH tVPWH tQVVL VHH VIH RP (P) VIL VPPH3,2,1 VPP(V) VPPLK VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. 28F016SCT-L95-16 Figure 16. AC Waveforms for WE-Controlled Write Operations 30 Data Sheet 16M Flash Memory LH28F016SCT ALTERNATIVE CE-CONTROLLED WRITES VCC = 2.7 V - 3.6 V, TA = -40°C to +85°C SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL LH28F016SC-L150 MIN. MAX. UNIT NOTES 150 ns RP HIGH Recovery to CE Going LOW 1 µs tWLEL WE Setup to CE Going LOW 0 ns tELEH CE Pulse Width 70 ns tAVEH Address Setup to CE Going HIGH 50 ns 2 tDVEH Data Setup to CE Going HIGH 50 ns 2 tEHDX Data Hold from CE HIGH 5 ns tEHAX Address Hold from CE HIGH 5 ns tEHWH WE Hold from CE HIGH 0 ns tEHEL CE Pulse Width HIGH 25 ns tEHGL Write Recovery before Read 0 ns 1 NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase, byte write or lock bit configuration. 3. VCCW should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. In systems where CE defines the write pulse width (within a longer WE timing waveform), all setup, hold, and inactive WE times should be measured relative to the CE waveform. Data Sheet 31 LH28F016SCT 16M Flash Memory VCC = 3.3 V ±0.3 V, TA = -40°C to +85°C SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL LH28F016SC-L120 MIN. MAX. UNIT NOTES 120 ns RP HIGH Recovery to CE Going LOW 1 µs tWLEL WE Setup to CE Going LOW 0 ns tELEH CE Pulse Width 70 ns tPHHEH RP VHH Setup to CE Going HIGH 100 ns tVPEH VPP Setup to CE Going HIGH 100 ns tAVEH Address Setup to CE Going HIGH 50 ns 2 tDVEH Data Setup to CE Going HIGH 50 ns 2 tEHDX Data Hold from CE HIGH 5 ns tEHAX Address Hold from CE HIGH 5 ns tEHWH WE Hold from CE HIGH 0 ns tEHEL CE Pulse Width HIGH 25 ns tEHRL CE HIGH to RY/BY Going LOW tEHGL Write Recovery before Read 0 ns tQVVL VPP Hold from Valid SRD, RY/BY HIGH 0 ns tQVPH RP VHH Hold from Valid SRD, RY/BY HIGH 0 ns 100 1 ns NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase, byte write or lock bit configuration. 3. VCCW should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. In systems where CE defines the write pulse width (within a longer WE timing waveform), all setup, hold, and inactive WE times should be measured relative to the CE waveform. 32 Data Sheet 16M Flash Memory LH28F016SCT VCC = 5 V ±0.5 V (L100), 5 V ±0.25 V (L95), TA = -40°C to +85°C SYMBOL PARAMETER LH28F016SC-L95 LH28F016SC-L100 MIN. MAX. MIN. MAX. UNIT NOTES tAVAV Write Cycle Time 95 100 ns tPHEL RP HIGH Recovery to CE Going LOW 1 1 µs tWLEL WE Setup to CE Going LOW 0 0 ns tELEH CE Pulse Width 50 50 ns tPHHEH RP VHH Setup to CE Going HIGH 100 100 ns 1 tVPEH VCCW Setup to CE Going HIGH 100 100 ns 1 tAVEH Address Setup to CE Going HIGH 40 40 ns 2 tDVEH Data Setup to CE Going HIGH 40 40 ns 2 tEHDX Data Hold from CE HIGH 5 5 ns tEHAX Address Hold from CE HIGH 5 5 ns tEHWH WE Hold from CE HIGH 0 0 ns tEHEL CE Pulse Width HIGH 25 25 ns tEHRL CE HIGH to RY/BY Going LOW tEHGL Write Recovery before Read 0 0 ns tQVVL VCCW Hold from Valid SRD, RY/BY HIGH 0 0 ns 1, 3 tQVPH RP VHH Hold from Valid SRD, RY/BY HIGH 0 0 ns 1, 3 90 90 1 ns NOTES: 1. Sampled, not 100% tested. 2. Refer to Table 4 for valid AIN and DIN for block erase, byte write or lock bit configuration. 3. VCCW should be held at VPPH1/2/3, (and if necessary, RP should be held at VHH) until determination of block erase, byte write or lock bit configuration success (SR.1, SR.3, SR.4, SR.5 = 0). 4. In systems where CE defines the write pulse width (within a longer WE timing waveform), all setup, hold, and inactive WE times should be measured relative to the CE waveform. Data Sheet 33 LH28F016SCT 16M Flash Memory 1 VIH ADDRESSES (A) VIL 2 3 AIN AIN tAVAV 4 5 6 tAVEH tEHAX VIH WE (W) VIL tWLEL tEHWH tEHGL VIH OE (G) VIL tEHEL tEHQV1,2,3,4 VIH CE (E) VIL tELEH tDVEH tEHDX VIH DATA (D/Q) HIGH-Z VIL DIN DIN DIN tEHRL tPHEL VALID SRD VOH RY/BY (R) VOL tPHHEH tQVPH tVPEH tQVVL VHH VIH RP (P) VIL VPPH3,2,1 VPP(V) VPPLK VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. 28F016SCT-L95-17 Figure 17. AC Waveforms for CE-controlled Write Operations 34 Data Sheet 16M Flash Memory LH28F016SCT RESET OPERATIONS Table 10. Reset AC Specifications SYMBOL VCC = 2.7 V PARAMETER VCC = 5.0 V MIN. MAX. MIN. MAX. MIN. MAX. tPLPH RP Pulse LOW Time tPLRH RP LOW to Reset during Block Erase, Byte Write or Lock bit Configuration t235VPH VCC 2.7 V to RP HIGH VCC 3.0 V to RP HIGH VCC 4.5 V to RP HIGH 100 100 100 20 100 NOTES: 1. If RP is tied to VCC, this specification does not apply. 2. An RP asserted reset will complete within 100 ns unless a block erase, lock bit, or chip erase operation is being performed. RY/BY (R) VCC = 3.3 V 100 12 100 UNIT NOTES ns 1 µs 2, 3 ns 2, 4 3. A reset time, tPHQV, is required from the later of RY/BY or RP going HIGH until outputs are valid. 4. When the device is powered up, holding RP LOW a minimum 100 ns is required after VCC reaches nominal voltage and stabilizes. VOH VOL RP (P) VIH VIL tPLPH (A) Reset During Read Array Mode RY/BY (R) VOH VOL tPLRH RP (P) VIH VIL tPLPH (B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration 2.7 V/3.3 V/5 V VCC VIL t235VPH RP (P) VIH VIL (C) RP Rise time 28F016SCT-L95-18 Figure 18. AC Waveform for Reset Operation Data Sheet 35 LH28F016SCT 16M Flash Memory BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK BIT CONFIGURATION PERFORMANCE VCC = 3.3 V ±0.3 V, TA = -40°C to +85°C SYMBOL tWHQV1, tEHQV1 PARAMETER Byte Write Time VPP = 3.3 V VPP = 5 V VPP = 12 V TYP. MAX. TYP. MAX. TYP. MAX. 19 300 10 150 UNIT NOTES 7 125 µs 1 Block Write Time 1.2 4 0.7 2 0.5 1.5 s 1 tWHQV2, tEHQV2 Block Erase Time 0.8 6 0.4 5 0.3 4 s 1 tWHQV3, tEHQV3 Set Lock Bit Time 21 300 13.3 150 11.6 125 µs 1 tWHQV4, tEHQV4 Clear Block Lock Bits Time 1.8 6 1.2 5 1.1 4 s 1 tWHRH1, tEHRH1 Byte Write Suspend Latency Time to Read 7.1 10 6.6 9.3 7.4 10.4 µs 1 tWHRH2, tEHRH2 Erase Suspend Latency Time to Read 15.2 21.1 12.3 17.2 12.3 17.2 µs 1 NOTES: 1. Excludes system-level overhead. 2. A latency time is required from issuing the suspend command (WE or CE going HIGH) until RY/BY going high-Z or SR.7 going HIGH. 3. Sampled but not 100% tested. 4. Typical values measured at TA = +25°C and VCC at nominal. Assumes corresponding lock bits are not set. Subject to change based on device characterization. VCC = 5 V ±0.5 V, 5 V ±0.25 V, TA = -40°C to +85°C SYMBOL tWHQV1, tEHQV1 PARAMETER Byte Write Time VPP = 5 V VPP = 12 V TYP. MAX. TYP. MAX. 8 150 6 100 UNIT NOTES µs 1 Block Write Time 0.5 1.5 0.4 1 s 1 tWHQV2, tEHQV2 Block Erase Time 0.4 5 0.3 4 s 1 tWHQV3, tEHQV3 Set Lock-Bit Time 12 150 10 100 µs 1 tWHQV4, tEHQV4 Clear Block Lock-Bits Time 1.1 5 1 4 s 1 tWHRH1, tEHRH1 Byte Write Suspend Latency Time to Read 5.6 7 5.2 7.5 µs 1 tWHRH2, tEHRH2 Erase Suspend Latency Time to Read 9.4 13.1 9.8 12.6 s 1 NOTES: 1. Excludes system-level overhead. 2. A latency time is required from issuing the suspend command (WE or CE going HIGH) until RY/BY going high-Z or SR.7 going HIGH. 3. Sampled but not 100% tested. 4. Typical values measured at TA = +25°C and VCC at nominal. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 36 Data Sheet 16M Flash Memory LH28F016SCT ORDERING INFORMATION LH28F016SCHT-L95 Product line designator for all SHARP Flash products Access Speed (ns) 95 = 95 ns (5 V, 30 pF), 100 ns (5 V) Device Density 016 = 16M Package T = 40-Lead TSOP R = 40-Lead TSOP (Reverse Bend) Architecture S = Regular Block Power Supply Type C = SmartVoltage Technology Operating Temperature Blank = 0˚C to +70˚C H = -40˚C to +85˚C 28F016SCT-L95-19 Data Sheet 37 LH28F160S3 16M Flash Memory SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735 ©2003 by SHARP Corporation Reference Code SMA03029