PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S5HNS-L70
Flash Memory
16M (2MB × 8 / 1MB × 16))
(Model No.: LHF16KAP)
Spec No.: EL12X108A
Issue Date: February 2, 2001
sharp
LHF16KAP
●Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
●When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev. 2.0
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LHF16KAP
1
CONTENTS
PAGE
PAGE
1 INTRODUCTION ...................................................... 3
5 DESIGN CONSIDERATIONS .................................30
1.1 Product Overview ................................................ 3
5.1 Three-Line Output Control .................................30
5.2 STS and Block Erase, Full Chip Erase, (Multi)
2 PRINCIPLES OF OPERATION ................................ 6
Word/Byte Write and Block Lock-Bit Configuration
2.1 Data Protection ................................................... 7
Polling................................................................30
5.3 Power Supply Decoupling ..................................30
3 BUS OPERATION.................................................... 7
5.4 VPP Trace on Printed Circuit Boards ..................30
3.1 Read ................................................................... 7
5.5 VCC, VPP, RP# Transitions.................................31
3.2 Output Disable .................................................... 7
5.6 Power-Up/Down Protection................................31
3.3 Standby ............................................................... 7
5.7 Power Dissipation ..............................................31
3.4 Deep Power-Down .............................................. 7
3.5 Read Identifier Codes Operation ......................... 8
6 ELECTRICAL SPECIFICATIONS...........................32
3.6 Query Operation.................................................. 8
6.1 Absolute Maximum Ratings ...............................32
3.7 Write.................................................................... 8
6.2 Operating Conditions .........................................32
6.2.1 Capacitance .................................................32
4 COMMAND DEFINITIONS ....................................... 8
6.2.2 AC Input/Output Test Conditions ..................33
4.1 Read Array Command....................................... 11
6.2.3 DC Characteristics........................................34
4.2 Read Identifier Codes Command ...................... 11
6.2.4 AC Characteristics - Read-Only Operations .36
4.3 Read Status Register Command....................... 11
6.2.5 AC Characteristics - Write Operations..........39
4.4 Clear Status Register Command....................... 11
6.2.6 Alternative CE#-Controlled Writes ................41
4.5 Query Command............................................... 12
6.2.7 Reset Operations .........................................43
4.5.1 Block Status Register .................................. 12
6.2.8 Block Erase, Full Chip Erase, (Multi)
4.5.2 CFI Query Identification String..................... 13
Word/Byte Write and Block Lock-Bit
4.5.3 System Interface Information....................... 13
Configuration Performance...........................44
4.5.4 Device Geometry Definition ......................... 14
4.5.5 SCS OEM Specific Extended Query Table .. 14
7 ADDITIONAL INFORMATION ................................45
4.6 Block Erase Command...................................... 15
7.1 Ordering Information ..........................................45
4.7 Full Chip Erase Command ................................ 15
4.8 Word/Byte Write Command............................... 16
8 PACKAGE AND PACKING SPECIFICATION........46
4.9 Multi Word/Byte Write Command ...................... 16
4.10 Block Erase Suspend Command..................... 17
4.11 (Multi) Word/Byte Write Suspend Command... 17
4.12 Set Block Lock-Bit Command.......................... 18
4.13 Clear Block Lock-Bits Command..................... 18
4.14 STS Configuration Command ......................... 19
Rev. 2.0
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LHF16KAP
2
LH28F160S5HNS-L70
16M-BIT (2MBx8/1MBx16)
Smart 5 Flash MEMORY
■ Smart 5 Technology
5V VCC
5V VPP
■ Common Flash Interface (CFI)
Universal & Upgradable Interface
■ Scalable Command Set (SCS)
■ High Speed Write Performance
32 Bytes x 2 plane Page Buffer
2µs/Byte Write Transfer Rate
■ High Speed Read Performance
70ns(5V±0.25V), 90ns(5V±0.5V)
■ Operating Temperature
-40°C to +85°C
■ Enhanced Automated Suspend Options
Write Suspend to Read
Block Erase Suspend to Write
Block Erase Suspend to Read
■ High-Density Symmetrically-Blocked
Architecture
Thirty-two 64K-byte Erasable Blocks
■ SRAM-Compatible Write Interface
■ User-Configurable x8 or x16 Operation
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Erase/Write Lockout during Power
Transitions
■ Extended Cycling Capability
100,000 Block Erase Cycles
3.2 Million Block Erase Cycles/Chip
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Automated Write and Erase
Command User Interface
Status Register
■ Industry-Standard Packaging
56-Lead SSOP
■ ETOXTM* V Nonvolatile Flash
Technology
■ CMOS Process
(P-type silicon substrate)
■ Not designed or rated as radiation
hardened
SHARP’s LH28F160S5HNS-L70 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S5HNS-L70 offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F160S5HNS-L70 is conformed to the flash Scalable Command Set (SCS) and the Common Flash
Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device
data transfer rates and minimize device and system-level implementation costs.
The LH28F160S5HNS-L70 is manufactured on SHARP’s 0.35µm ETOXTM* V process technology. It come in
industry-standard package: the 56-Lead SSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 2.0
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LHF16KAP
1 INTRODUCTION
This datasheet contains LH28F160S5HNS-L70
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S5HNS-L70 is a high-performance
16M-bit Smart 5 Flash memory organized as
2MBx8/1MBx16. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 5 technology provides a choice of VCC and
VPP combinations, as shown in Table 1, to meet
system performance and power expectations. 5V VCC
provides the highest read performance. VPP at 5V
eliminates the need for a separate 12V converter,
while VPP=5V maximizes erase and write
performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives
complete data protection when VPP≤VPPLK.
Table 1. VCC and VPP Voltage Combinations
Offered by Smart 5 Technology
VCC Voltage
VPP Voltage
5V
5V
Internal
VCC and VPP detection Circuitry
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.34s (5V VCC, 5V
VPP) independent of other blocks. Each block can be
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 9.24µs (5V VCC, 5V VPP). A multi
word/byte write has high speed write performance of
2µs/byte (5V VCC, 5V VPP). (Multi) Word/byte write
suspend mode enables the system to read data or
3
execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 70ns (tAVQV) over the extended
temperature range (-40°C to +85°C) and VCC supply
voltage range of 4.75V-5.25V. At lower VCC voltage,
the access time is 90ns (4.5V-5.5V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical ICCR current is 1 mA at 5V VCC.
When either CE0# or CE1#, and RP# pins are at VCC,
the ICC CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tPHQV) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.
Rev. 2.0
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LHF16KAP
4
DQ0-DQ15
Input
Buffer
Output
Buffer
I/O Logic
Idenrifier
Register
Page
Buffer
Status
Register
VCC
BYTE#
CE#
Data
Register
Output
Multiplexer
Query
ROM
WE#
Command
Register
OE#
RP#
WP#
Multiplexer
Data
Comparator
A0-A20
Input
Buffer
Y
Decoder
Address
Latch
X
Decoder
Y Gating
STS
Write State
Machine
Program/Erase
Voltage Switch
VPP
VCC
32
64KByte
Blocks
GND
Address
Counter
Figure 1. Block Diagram
CE0#
A12
A13
A14
A15
NC
CE1#
NC
A20
A19
A18
A17
A16
VCC
GND
DQ6
DQ14
DQ7
DQ15
STS
OE#
WE#
WP#
DQ13
DQ5
DQ12
DQ4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 LEAD SSOP
PINOUT
1.8mm x 16mm x 23.7mm
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VPP
RP#
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
DQ2
DQ10
DQ3
DQ11
GND
Figure 2. SSOP 56-Lead Pinout
Rev. 2.0
sharp
Symbol
Type
A0-A20
INPUT
DQ0-DQ15
INPUT/
OUTPUT
CE0#,
CE1#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
STS
OPEN
DRAIN
OUTPUT
WP#
INPUT
BYTE#
INPUT
VPP
SUPPLY
VCC
SUPPLY
GND
NC
SUPPLY
LHF16KAP
5
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A0: Byte Select Address. Not used in x16 mode(can be floated).
A1-A4: Column Address. Selects 1 of 16 bit lines.
A5-A15: Row Address. Selects 1 of 2048 word lines.
A16-A20 : Block Address.
DATA INPUT/OUTPUTS:
DQ0-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory
array, status register, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQ8-DQ15:Inputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=VIL). Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE0# or CE1# VIH deselects the device and reduces power consumption
to standby levels. Both CE0# and CE1# must be VIL to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.
WRITE PROTECT: Master control for block locking. When VIL, Locked blocks can not be
erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE: BYTE# VIL places device in x8 mode. All data is then input or output on
DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode , and turns off the A0
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With VPP≤VPPLK, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
VPP (see DC Characteristics) produce spurious results and should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
not float any power pins. With VCC≤VLKO, all write attempts to the flash memory are
inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce
spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 2.0
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LHF16KAP
6
2 PRINCIPLES OF OPERATION
1FFFFF
The LH28F160S5HNS-L70 Flash memory includes
an on-chip WSM to manage block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
VPP voltage. High voltage on VPP enables successful
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. All functions
associated with altering memory contentsblock
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, status, query and
identifier codesare accessed via the CUI and
verified through the status register.
Commands
are
written
using
standard
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
64K-byte Block
31
64K-byte Block
30
64K-byte Block
29
64K-byte Block
28
64K-byte Block
27
64K-byte Block
26
64K-byte Block
25
64K-byte Block
24
64K-byte Block
23
64K-byte Block
22
64K-byte Block
21
64K-byte Block
20
64K-byte Block
19
64K-byte Block
18
64K-byte Block
17
64K-byte Block
16
64K-byte Block
15
64K-byte Block
14
64K-byte Block
13
64K-byte Block
12
64K-byte Block
11
64K-byte Block
10
64K-byte Block
9
64K-byte Block
8
64K-byte Block
7
64K-byte Block
6
64K-byte Block
5
64K-byte Block
4
64K-byte Block
3
64K-byte Block
2
64K-byte Block
1
64K-byte Block
0
000000
Figure 3. Memory Map
Rev. 2.0
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LHF16KAP
7
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to VPPH1.
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
When VPP≤VPPLK, memory contents cannot be
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration
command
sequences,
provides
protection from unwanted operations even when high
voltage is applied to VPP. All write functions are
disabled when VCC is below the write lockout voltage
VLKO or when RP# is at VIL. The device’s block
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, query structure, or status register independent
of the VPP voltage. RP# must be at VIH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CE0#, CE1#), OE#, WE#,
RP# and WP#. CE0#, CE1# and OE# must be driven
active to obtain data at the outputs. CE0#, CE1# is
the device selection control, and when active enables
the selected memory device. OE# is the data output
(DQ0-DQ15) control and when active drives the
selected memory data onto the I/O bus. WE# and
RP# must be at VIH. Figure 17, 18 illustrates a read
cycle.
3.3 Standby
Either CE0# or CE1# at a logic-high level (VIH) places
the device in standby mode which substantially
reduces device power consumption. DQ0-DQ15
outputs are placed in a high-impedance state
independent of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
Rev. 2.0
sharp
LHF16KAP
8
3.5 Read Identifier Codes Operation
3.6 Query Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowestorder data output (DQ0-DQ7) only.
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VCC=VCC1/2 and VPP=VPPH1, the CUI additionally
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
1FFFFF
Reserved for
Future Implementation
1F0006
1F0005
1F0004
1F0003
Block 31 Status Code
Reserved for
Future Implementation
1F0000
1EFFFF
Block 31
(Blocks 2 through 30)
020000
01FFFF
4 COMMAND DEFINITIONS
Block 1 Status Code
Reserved for
Future Implementation
010000
00FFFF
Block 1
Reserved for
Future Implementation
000006
000005
000004
000003
000002
000001
000000
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
Reserved for
Future Implementation
010006
010005
010004
010003
3.7 Write
When the VPP voltage ≤ VPPLK, Read operations from
the status register, identifier codes, query, or blocks
are enabled. Placing VPPH1 on VPP enables
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Block 0 Status Code
Device Code
Manufacturer Code
Block 0
Figure 4. Device Identifier Code Memory Map
Rev. 2.0
sharp
Mode
Read
Output Disable
LHF16KAP
Notes
1,2,3,9
3
Standby
3
Deep Power-Down
Read Identifier
Codes
4
Query
9
Write
3,7,8,9
Mode
Read
Output Disable
9
Notes
1,2,3,9
3
Standby
3
Deep Power-Down
Read Identifier
Codes
4
Query
9
9
Table 3. Bus Operations(BYTE#=VIH)
RP#
CE0#
CE1#
OE#
WE# Address
VIH
VIL
VIL
VIL
VIH
X
VIH
VIL
VIL
VIH
VIH
X
VIH
VIH
VIH
VIH
VIL
X
X
X
VIL
VIH
VIL
X
X
X
X
X
See
VIH
VIL
VIL
VIL
VIH
Figure 4
See Table
VIH
VIL
VIL
VIL
VIH
7~11
VIH
VIL
VIL
VIH
VIL
X
Table 3.1. Bus Operations(BYTE#=VIL)
RP#
CE0#
CE1#
OE#
WE# Address
VIH
VIL
VIL
VIL
VIH
X
VIH
VIL
VIL
VIH
VIH
X
VIH
VIH
VIH
VIH
VIL
X
X
X
VIL
VIH
VIL
X
X
X
X
X
See
VIH
VIL
VIL
VIL
VIH
Figure 4
See Table
VIH
VIL
VIL
VIL
VIH
7~11
VIH
VIL
VIL
VIH
VIL
X
9
VPP
X
X
DQ0-15
DOUT
High Z
STS
X
X
X
High Z
X
X
High Z
High Z
X
Note 5
High Z
X
Note 6
High Z
X
DIN
X
VPP
X
X
DQ0-7
DOUT
High Z
STS
X
X
X
High Z
X
X
High Z
High Z
X
Note 5
High Z
X
Note 6
High Z
Write
3,7,8,9
X
DIN
X
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1 for VPP. See DC Characteristics for
VPPLK and VPPH1 voltages.
3. STS is VOL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power-down mode.
4. RP# at GND±0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when VPP=VPPH1 and VCC=VCC1/2.
8. Refer to Table 4 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
Rev. 2.0
sharp
LHF16KAP
10
Table 4. Command Definitions(10)
Bus Cycles Notes
First Bus Cycle
Req’d
Oper(1) Addr(2) Data(3)
1
Write
X
FFH
4
Write
X
90H
≥2
Write
X
98H
≥2
2
Write
X
70H
1
Write
X
50H
2
5
Write
BA
20H
2
Write
X
30H
2
5,6
Write
WA
40H
Second Bus Cycle
Command
Oper(1) Addr(2) Data(3)
Read Array/Reset
Read Identifier Codes
Read
IA
ID
Query
Read
QA
QD
Read Status Register
Read
X
SRD
Clear Status Register
Block Erase Setup/Confirm
Write
BA
D0H
Full Chip Erase Setup/Confirm
Write
X
D0H
Word/Byte Write Setup/Write
Write
WA
WD
Alternate Word/Byte Write
2
5,6
Write
WA
10H
Write
WA
WD
Setup/Write
Multi Word/Byte Write
≥4
9
Write
WA
E8H
Write
WA
N-1
Setup/Confirm
Block Erase and (Multi)
1
5
Write
X
B0H
Word/byte Write Suspend
Confirm and Block Erase and
1
5
Write
X
D0H
(Multi) Word/byte Write Resume
Block Lock-Bit Set Setup/Confirm
2
7
Write
BA
60H
Write
BA
01H
Block Lock-Bit Reset
2
8
Write
X
60H
Write
X
D0H
Setup/Confirm
STS Configuration
2
Write
X
B8H
Write
X
00H
Level-Mode for Erase and Write
(RY/BY# Mode)
STS Configuration
2
Write
X
B8H
Write
X
01H
Pulse-Mode for Erase
STS Configuration
2
Write
X
B8H
Write
X
02H
Pulse-Mode for Write
STS Configuration
2
Write
X
B8H
Write
X
03H
Pulse-Mode for Erase and Write
NOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 14 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.
4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, WP# must be at VIH to enable block erase or (multi) word/byte write operations. Attempts
to issue a block erase or (multi) word/byte write to a locked block while RP# is VIH.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. A block lock-bit can be set while WP# is VIH.
8. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block
lock-bits.
9. Following the Third Bus Cycle, inputs the write address and write data of ’N’ times. Finally, input the confirm
command ’D0H’.
10. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 2.0
sharp
LHF16KAP
11
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
for reads until another command is written. Once the
internal WSM has started a block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration, the device will not recognize the Read
Array command until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend and (Multi) Word/byte Write Suspend
command. The Read Array command functions
independently of the VPP voltage and RP# must be
VIH.
The status register may be read to determine when a
block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration is complete and whether
the operation completed successfully(see Table 14).
It may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is written.
The status register contents are latched on the falling
edge of OE# or CE#(Either CE0# or CE1#),
whichever occurs. OE# or CE#(Either CE0# or CE1#)
must toggle to VIH before further reads to update the
status register latch. The Read Status Register
command functions independently of the VPP voltage.
RP# must be VIH.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the
command write, read cycles from addresses shown in
Figure 4 retrieve the manufacturer, device, block lock
configuration and block erase status (see Table 5 for
identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command
functions independently of the VPP voltage and RP#
must be VIH. Following the Read Identifier Codes
command, the following information can be read:
Table 5. Identifier Codes
Code
Address
Data
00000
Manufacture Code
B0
00001
00002
Device Code
D0
00003
X0004(1)
Block Status Code
X0005(1)
DQ0=0
•Block is Unlocked
DQ0=1
•Block is Locked
•Last erase operation
DQ1=0
completed successfully
•Last erase operation did
DQ1=1
not completed successfully
DQ2-7
•Reserved for Future Use
NOTE:
1. X selects the specific block status code to be
read. See Figure 4 for the device identifier code
memory map.
The extended status register may be read to
determine multi word/byte write availability(see Table
14.1). The extended status register may be read at
any time by writing the Multi Word/Byte Write
command. After writing this command, all subsequent
read operations output data from the extended status
register, until another valid command is written. Multi
Word/Byte Write command must be re-issued to
update the extended status register latch.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 14). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurs during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied VPP Voltage. RP# must be VIH. This
command is not functional during block erase, full
chip erase, (multi) word/byte write block lock-bit
configuration, block erase suspend or (multi)
word/byte write suspend modes.
Rev. 2.0
sharp
LHF16KAP
4.5 Query Command
Query database can be read by writing Query
command (98H). Following the command write, read
cycle from address shown in Table 7~11 retrieve the
critical information to write, erase and otherwise
control the flash component. A0 of query offset
address is ignored when X8 mode (BYTE#=VIL).
Query data are always presented on the low-byte
data output (DQ0-DQ7). In x16 mode, high-byte
(DQ8-DQ15) outputs 00H. The bytes not assigned to
any information or reserved for future use are set to
"0". This command functions independently of the
VPP voltage. RP# must be VIH.
12
Table 6. Example of Query Structure Output
Mode
Offset Address
Output
DQ15~8 DQ7~0
A 5, A 4, A 3, A 2, A 1, A 0
1 , 0 , 0 , 0 , 0 , 0 (20H) High Z
"Q"
"Q"
X8 mode 1 , 0 , 0 , 0 , 0 , 1 (21H) High Z
1, 0 , 0 , 0 , 1 , 0 (22H) High Z
"R"
1 , 0 , 0 , 0 , 1 , 1 (23H) High Z
"R"
A 5, A 4, A 3, A 2, A 1
X16 mode 1 , 0 , 0 , 0 , 0 (10H)
00H
"Q"
1 , 0 , 0 , 0 , 1 (11H)
00H
"R"
4.5.1 Block Status Register
This field provides lock configuration and erase status for the specified block. These informations are only available
when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status
bit will be set to "1". If bit 1 is "1", this block is invalid.
Table 7. Query Block Status Register
Offset
(Word Address)
(BA+2)H
Length
01H
Description
Block Status Register
bit0 Block Lock Configuration
0=Block is unlocked
1=Block is Locked
bit1 Block Erase Status
0=Last erase operation completed successfully
1=Last erase operation not completed successfully
bit2-7 reserved for future use
Note:
1. BA=The beginning of a Block Address.
Rev. 2.0
sharp
LHF16KAP
13
4.5.2 CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface
specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are)
supported.
Table 8. CFI Query Identification String
Offset
(Word Address)
10H,11H,12H
Length
03H
13H,14H
02H
15H,16H
02H
17H,18H
02H
19H,1AH
02H
Description
Query Unique ASCII string "QRY"
51H,52H,59H
Primary Vendor Command Set and Control Interface ID Code
01H,00H (SCS ID Code)
Address for Primary Algorithm Extended Query Table
31H,00H (SCS Extended Query Table Offset)
Alternate Vendor Command Set and Control Interface ID Code
0000H (0000H means that no alternate exists)
Address for Alternate Algorithm Extended Query Table
0000H (0000H means that no alternate exists)
4.5.3 System Interface Information
The following device information can be useful in optimizing system interface software.
Table 9. System Information String
Offset
(Word Address)
1BH
Length
01H
1CH
01H
1DH
01H
1EH
01H
1FH
01H
20H
01H
21H
01H
22H
01H
23H
01H
24H
01H
25H
01H
26H
01H
Description
VCC Logic Supply Minimum Write/Erase voltage
27H (2.7V)
VCC Logic Supply Maximum Write/Erase voltage
55H (5.5V)
VPP Programming Supply Minimum Write/Erase voltage
27H (2.7V)
VPP Programming Supply Maximum Write/Erase voltage
55H (5.5V)
Typical Timeout per Single Byte/Word Write
03H (23=8µs)
Typical Timeout for Maximum Size Buffer Write (32 Bytes)
06H (26=64µs)
Typical Timeout per Individual Block Erase
0AH (0AH=10, 210=1024ms)
Typical Timeout for Full Chip Erase
0FH (0FH=15, 215=32768ms)
Maximum Timeout per Single Byte/Word Write, 2N times of typical.
04H (24=16, 8µsx16=128µs)
Maximum Timeout Maximum Size Buffer Write, 2N times of typical.
04H (24=16, 64µsx16=1024µs)
Maximum Timeout per Individual Block Erase, 2N times of typical.
04H (24=16, 1024msx16=16384ms)
Maximum Timeout for Full Chip Erase, 2N times of typical.
04H (24=16, 32768msx16=524288ms)
Rev. 2.0
sharp
LHF16KAP
14
4.5.4 Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 10. Device Geometry Definition
Offset
(Word Address)
27H
Length
01H
28H,29H
02H
2AH,2BH
02H
2CH
01H
2DH,2EH
02H
2FH,30H
02H
Description
Device Size
15H (15H=21, 221=2097152=2M Bytes)
Flash Device Interface description
02H,00H (x8/x16 supports x8 and x16 via BYTE#)
Maximum Number of Bytes in Multi word/byte write
05H,00H (25=32 Bytes )
Number of Erase Block Regions within device
01H (symmetrically blocked)
The Number of Erase Blocks
1FH,00H (1FH=31 ==> 31+1=32 Blocks)
The Number of "256 Bytes" cluster in a Erase block
00H,01H (0100H=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block)
4.5.5 SCS OEM Specific Extended Query Table
Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional
vendor-specific Query table(s) may be used to specify this and other types of information. These structures are
defined solely by the flash vendor(s).
Table 11. SCS OEM Specific Extended Query Table
Offset
(Word Address)
31H,32H,33H
34H
35H
36H,37H,
38H,39H
3AH
3BH,3CH
3DH
3EH
3FH
Length
Description
03H
PRI
50H,52H,49H
01H
31H (1) Major Version Number , ASCII
01H
30H (0) Minor Version Number, ASCII
04H
0FH,00H,00H,00H
Optional Command Support
bit0=1 : Chip Erase Supported
bit1=1 : Suspend Erase Supported
bit2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock Supported
bit4=0 : Queued Erase Not Supported
bit5-31=0 : reserved for future use
01H
01H
Supported Functions after Suspend
bit0=1 : Write Supported after Erase Suspend
bit1-7=0 : reserved for future use
02H
03H,00H
Block Status Register Mask
bit0=1 : Block Status Register Lock Bit [BSR.0] active
bit1=1 : Block Status Register Valid Bit [BSR.1] active
bit2-15=0 : reserved for future use
01H
VCC Logic Supply Optimum Write/Erase voltage(highest performance)
50H(5.0V)
01H
VPP Programming Supply Optimum Write/Erase voltage(highest performance)
50H(5.0V)
reserved Reserved for future versions of the SCS Specification
Rev. 2.0
sharp
LHF16KAP
4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
confirm.
This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
can only occur when VCC=VCC1/2 and VPP=VPPH1. In
the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while VPP≤VPPLK, SR.3 and SR.5 will be set to "1".
Successful block erase requires that the
corresponding block lock-bit be cleared or if set, that
WP#=VIH. If block erase is attempted when the
corresponding block lock-bit is set and WP#=VIL,
SR.1 and SR.5 will be set to "1".
15
erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0 to
Block 31 block by block. This command sequence
requires
appropriate
sequencing.
Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle full chip erase sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect full
chip erase completion by analyzing the output data of
the STS pin or status register bit SR.7.
When the full chip erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued. If error is detected on a block
during full chip erase operation, WSM stops erasing.
Reading the block valid status by issuing Read ID
Codes command or Query command informs which
blocks failed to its erase.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status register
bits SR.4 and SR.5 being set to "1". Also, reliable full
chip erasure can only occur when VCC=VCC1/2 and
VPP=VPPH1. In the absence of this high voltage, block
contents are protected against erasure. If full chip
erase is attempted while VPP≤VPPLK, SR.3 and SR.5
will be set to "1". When WP#=VIH, all blocks are
erased independent of block lock-bits status. When
WP#=VIL, only unlocked blocks are erased. In this
case, SR.1 and SR.5 will not be set to ‘‘1‘‘. Full chip
erase can not be suspended.
4.7 Full Chip Erase Command
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A full chip
Rev. 2.0
sharp
LHF16KAP
4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
SR.7.
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains in
read status register mode until it receives another
command.
Reliable word/byte writes can only occur when
VCC=VCC1/2 and VPP=VPPH1. In the absence of this
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
VPP≤VPPLK, status register bits SR.3 and SR.4 will be
set to "1". Successful word/byte write requires that
the corresponding block lock-bit be cleared or, if set,
that WP#=VIH. If word/byte write is attempted when
the corresponding block lock-bit is set and WP#=VIL,
SR.1 and SR.4 will be set to "1". Word/byte write
operations with VIL
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