LH52256CH

LH52256C/CH FEATURES • 32,768 × 8 bit organization • Access time: 70 ns (MAX.) • Supply current: Operating: 45 mA (MAX.) 10 mA (MAX.) (tRC, tWC = 1 µs) Standby: 40 µA (MAX.) • Data retention current: 1.0 µA (MAX.) (VCCDR = 3 V, TA = 25 °C) • Wide operating voltage range: 4.5 V ± 5 .5 V • Operating temperature: Commerical temperature 0°C to +70 °C Industrial temperature -40° to +85°C • Fully-static operation • Three-state outputs • Not designed or rated as radiation hardened • Package: 28-pin, 600-mil DIP 28-pin, 450-mil SOP 28-pin, 300-mil SK-DIP 28-pin, 8 × 3 mm2 TSOP (Type I) • N-type bulk silicon DESCRIPTION The LH52256C is a Static RAM organized as 32,768 × 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology. CMOS 256K (32K × 8) Static RAM PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 52256C-1 TOP VIEW Figure 1. Pin Connections 28-PIN TSOP (Type I) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 NOTE: Reverse bend available on request. 52256C-8 Figure 2. TSOP (Type I) Pin Connections 1 LH52256C/CH CMOS 256K (32K × 8) Static RAM A8 25 A14 1 A13 26 A12 2 A7 3 ROW DECORDER A6 4 A5 5 A4 6 11 I/O1 12 I/O2 COLUMN I/O CIRCUIT COLUMN DECODER 8 OUTPUT BUFFERS 13 I/O3 15 I/O4 16 I/O5 17 I/O6 18 I/O7 19 I/O8 A3 7 MEMORY ARRAY (512 x 512) 28 VCC 14 GND 8 INPUT DATA CONTROL WE 27 OE 22 CE 20 10 9 8 21 24 23 A0 A1 A2 A10 A9 A11 52256C-2 Figure 3. LH52256C Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A14 CE WE OE Address inputs Chip enable Write enable Output enable I/O1 - I/O8 VCC GND Data inputs and outputs Power supply Ground 2 CMOS 256K (32K × 8) Static RAM LH52256C/CH TRUTH TABLE CE WE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE H L L L X H H L X L H X Standby Read Output disable Write High impedance Data output High impedance Data input Standby (ISB ) Active (ICC) Active (ICC) Active (ICC) 1 1 1 1 NOTE: 1. X = Don’t care, L = Low, H = High ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage Input voltage Operating temperature Storage temperature VCC VIN TOPR TSTG –0.5 to +7.0 –0.5 to VCC + 0.5 0 to +70 –65 to +150 V V °C °C 1 1, 2   NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. Undershoot of -3.0 V is allowed width of pulse below 50 ns. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70 °C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Supply voltage Input voltage VCC VIH VIL 4.5 2.2 –0.5 5.0 5.5 VCC + 0.5 0.8 V V V   1   NOTE: 1. Undershoot of -3.0 V is allowed width of pulse below 50 ns. 3 LH52256C/CH CMOS 256K (32K × 8) Static RAM DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input leakage current Output leakage current Operating supply current ILI ILO ICC ICC1 VIN = 0 V to VCC CE = VIH or OE = VIH VI/O = 0 V to VCC Minimum cycle, VIN = VIL or VIH II/O = 0 mA, CE = VIL tRC, tWC = 1 µ s, VIN = VIL or VIH, II/O = 0 mA, CE = VIL CE ≥ VCC – 0.2 V CE = VIH IOL = 2.1 mA IOH = -1.0 mA –1.0 –1.0   25 1.0 1.0 45.0 µA µA      2.4 mA  0.6 10.0 40.0 3.0 0.4 µA mA V Standby current ISB ISB1    Output voltage VOL VOH  NOTE: Typical values at VCC = 5.0 V, TA = 25° C AC ELECTRICAL CHARACTERISTICS AC Test Conditions PARAMETER MODE NOTE Input pulse level Input rise and fall time Input and output timing Ref. level Output load NOTE: 1. Including scope and jig capacitance. 0.6 V to 2.4 V 10 ns 1.5 V 1 TTL + CL (100 pF)    1 READ CYCLE (TA = 0°C to +70 °C, VCC = 4.5 V to 5.5 V) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time CE access time Output enable to output valid Output hold from address change CE Low to output active OE Low to output active CE High to output in High impedance OE High to output in High impedance tRC tAA tACE tOE tOH tLZ tOLZ tHZ tOHZ 70  70 70 35 ns ns ns ns ns ns ns ns ns      1 1 1 1    10 10 5 0 0    30 30 NOTES: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. 4 CMOS 256K (32K × 8) Static RAM LH52256C/CH WRITE CYCLE (TA = 0°C to +70 °C, VCC = 4.5 V to 5.5 V) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Write cycle time CE Low to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Input data setup time Input data hold time WE High to output active WE Low to output in High impedance OE High to output in High impedance tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ 70 45 45 0 35 0 30 0 5 0 0          30 30 ns ns ns ns ns ns ns ns ns ns ns         1 1 1 NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. CAPACITANCE (TA = 25°C, f = 1MHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Input capacitance I/O capacitance CIN CI/O VIN = 0 V VI/O = 0 V     7 10 pF pF 1 1 NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS (TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Data retention supply voltage VCCDR CE ≥ VCCDR – 0.2 V VCCDR = 3.0 V TA = 25°C TA = 40°C CE ≥ VCCDR – 0.2 V 2.0  0.3 5.5 1.0 3.0 15 V     Data retention supply current ICCDR  µA  Chip enable setup time Chip enable hold time NOTE: 1. t RC = Read cycle time. 2. Typical values at TA = 25°C tCDR tR   0 tRC     ns ns  1 5 LH52256C/CH CMOS 256K (32K × 8) Static RAM tRC ADDRESS tAA tACE CE tLZ tOE tHZ OE tOLZ tOHZ tOH DOUT NOTE: WE is HIGH for Read Cycle. DATA VALID 52256C-3 Figure 4. Read Cycle 6 CMOS 256K (32K × 8) Static RAM LH52256C/CH tWC ADDRESS OE tAW tCW (NOTE 2) tWR (NOTE 4) CE tAS (NOTE 3) tWP (NOTE 1) tWR (NOTE 4) WE tOHZ (NOTE 6) DOUT tDW (NOTE 5) tDH DIN NOTES: 1. A write occurs during the overlap of a LOW CE, and a LOW WE. A write begins at the latest transition among CE going LOW, and WE going LOW. A write ends at the earliest transition among CE going HIGH, and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going LOW to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state. DATA VALID 52256C-4 Figure 5. Write Cycle (OE Controlled) 7 LH52256C/CH CMOS 256K (32K × 8) Static RAM tWC ADDRESS tAW tCW (NOTE 2) tWR (NOTE 4) CE tAS (NOTE 3) tWP (NOTE 1) tWR (NOTE 4) WE tWZ tOW (NOTE 7) (NOTE 6) DOUT tDW DIN (NOTE 5) tDH DATA VALID NOTES: 1. A write occurs during the overlap of a LOW CE, and a LOW WE. A write begins at the latest transition among CE going LOW, and WE going LOW. A write ends at the earliest transition among CE going HIGH, and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going LOW to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state. 52256C-5 Figure 6. Write Cycle (OE Low Fixed) CE CONTROL DATA RETENTION MODE VCC 4.5 V 2.2 V VCCDR CE ≥ VCCDR - 0.2 V CE 0V 52256C-6 tCDR tR Data Retention Timing Chart CE Controlled 8 CMOS 256K (32K × 8) Static RAM LH52256C/CH PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 36.30 [1.429] 35.70 [1.406] 14 0° TO 15° 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] 28DIP-2 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457] 0.50 [0.020] 0.30 [0.012] 28 10.60 [0.417] 1 18.20 [0.717] 17.80 [0.701] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 9 LH52256C/CH CMOS 256K (32K × 8) Static RAM 28SDIP (SDIP28-P-400) 28 15 DETAIL 8.80 [0.346] 8.40 [0.331] 0° TO 15° 0.30 [0.012] 0.20 [0.008] 4.05 [0.159] 3.65 [0.144] 4.60 [0.181] 4.20 [0.205] 3.50 [0.138] 3.00 [0.118] 1.78 [0.070] TYP. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN 10.16 [0.400] TYP. 1 25.75 [1.014] 25.25 [0.994] 14 DIMENSIONS IN MM [INCHES] 28SDIP 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 28 0.55 [0.022] TYP. 15 12.00 [0.472] 11.60 [0.457] 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 1 8.20 [0.323] 7.80 [0.307] 14 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] 28TSOP DETAIL 0 - 10° DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 10 CMOS 256K (32K × 8) Static RAM LH52256C/CH ORDERING INFORMATION LL - ## X LH52256C X Device Type Operating Package Speed Power Temp Low-Low-power standby 70 Access Time (ns) Blank 28-pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) Blank 0° to +70°C H -4° to +85°C CMOS 32K x 8 Static RAM Example: LH52256C-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 600-mil DIP) 52256C-7 11