LH5316P00B

LH5316P00B FEATURES • 2,097,152 × 8 b it organization (Byte mode: BYTE = VIL) 1,048,576 × 16 bit organization (Word mode: BYTE = VIH) • Access time: 120 ns (MAX.) • Supply current: – Operating: 70 mA (MAX.) – Standby: 100 µA (MAX.) • TTL compatible I/O • Three-state output • Single +5 V power supply • Static operation • Package: 44-pin, 600-mil SOP • Item related with COCOM regulation: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate) DESCRIPTION The LH5316P00B is a 16M-bit mask-programmable ROM organized as 2,097,152 × 8 bits (Byte mode) or 1,048,576 × 16 bits (Word mode) that can be selected by a B YTE input pin. It is fabricated using silicon-gate CMOS process technology. CMOS 16M (2M × 8/1M × 16) MROM PIN CONNECTIONS 44-PIN SOP TOP VIEW NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (NOTE) D7 D14 D6 D13 D5 D12 D4 VCC NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode. The input state of BYTE pin can not be changed during operation. The BYTE pin must be set to either GND or VCC. 5316P00B-1 Figure 1. Pin Connections 1 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM A19 43 A18 2 A17 3 A16 34 A15 35 ADDRESS DECODER A14 36 A13 37 A12 38 A11 39 A10 40 A9 41 A8 42 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 MEMORY MATRIX (2,097,152 x 8) (1,048,576 x 16) DATA SELECTOR/OUTPUT BUFFER ADDRESS BUFFER 31 29 27 25 D15 D14 D13 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 24 21 19 17 15 D5 D4 D3 D2 D1 D0 COLUMN SELECTOR CE 12 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER OE 14 OE BUFFER BYTE 33 BYTE/WORD SWITCHOVER CIRCUIT ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND 5316P00B-2 Figure 2. LH5316P00B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A-1 - A19 D0 - D15 BYTE CE Address input Data output ×8bit / ×16 bit (Byte/word) mode select input Chip enable input OE VCC GND NC Output enable input Power supply Ground No connection 2 CMOS 16M (2M x 8/1M x 16) MROM LH5316P00B TRUTH TABLE CE OE BYTE A-1 (D15) DATA OUTPUT D0 - D7 D8 - D15 ADDRESS INPUT LSB MSB SUPPLY CURRENT H L L L L X H L L L X X H L L X X  L H High-Z High-Z D 0 - D7 D0 - D7 D8 - D15 High-Z High-Z D8 - D15 High-Z High-Z   A0 A-1 A-1   A19 A19 A19 Standby (ISB) Operating Operating Operating Operating NOTES: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT TOPR TSTG -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 -65 to +150 V V V °C °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC ELECTICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage Input ‘Low’ voltage Output ‘High’ voltage Output ‘Low’ voltage Input leakage current Output leakage current Operating current V IH VIL VOH VOL | ILI | | ILO | ICC1 ICC2   I OH = -400 µ A I OL = 2 .0 mA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 120 ns t RC = 1 µs CE = VIH CE = VCC - 0.2 V f = 1 MHz, t A = 2 5° C 2.2 -0.3 2.4          VCC + 0.3 0.8  0.4 10 10 70 55 2 100 10 10 V V V V µA µA mA mA µA pF pF      1 2     Standby current Input capacitance Output capacitance ISB1 ISB2 CIN COUT NOTES: 1. CE = VIH, OE = VIH, output is open 2. VIN = VIH, VIL, C E = VIL, output is open 3 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM AC ELECTICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time tRC tAA tACE tOE tOH tCHZ tOHZ 120    5    120 120 60  60 60 ns ns ns ns ns ns      1 Output floating time ns NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input signal fall time Input reference level Output reference level Output load condition 0.6 V to 2.4 V 10 ns 10 ns 1.5 V 1.5 V 1TTL + 100 pF CAUTION It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. 4 CMOS 16M (2M x 8/1M x 16) MROM LH5316P00B tRC A-1 - A19 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ D0 - D7 NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. DATA VALID 5316P00B-3 Figure 3. Byte Mode (BYTE = VIL) tRC A0 - A19 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ (D0 - D15) NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. DATA VALID 5316P00B-4 Figure 4. Word Mode (BYTE = VIH) 5 LH5316P00B CMOS 16M (2M x 8/1M x 16) MROM PACKAGE DIAGRAM 44SOP (SOP044-P-0600) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 44 23 13.40 [0.528] 13.00 [0.512] 16.40 [0.646] 15.60 [0.614] 14.40 [0.567] 1 28.40 [1.118] 28.00 [1.102] 22 SEE DETAIL 0.20 [0.008] 0.10 [0.004] 2.9 [0.114] 2.5 [0.098] DETAIL 0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] 0 - 10° 0.80 [0.031] 44SOP ORDERING INFORMATION LH5316P00B Device Type N Package 44-pin, 600-mil SOP (SOP044-P-600) CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM Example: LH5316P00N (CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) 5316P00B-5 6