LH532100B

LH532100B FEATURES • 262,144 words × 8 bit organization • Access time: 150 ns (MAX.) • Low-power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • Mask-programmable OE/OE and OE1/OE1/DC • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) 32-pin, 8 × 20 mm2 TSOP (Type I) 32-pin, 400-mil TSOP (Type II) • JEDEC standard EPROM pinout (DIP) CMOS 2M (256K × 8) MROM DESCRIPTION The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 32-PIN DIP 32-PIN SOP OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC DC A17 A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3 532100B-1 TOP VIEW Figure 1. Pin Connections for DIP and SOP Packages GND 32-PIN QFJ D6 D5 D4 D3 TOP VIEW D2 D1 20 19 18 17 16 15 14 D7 CE A10 OE/OE A11 A9 A8 A13 A14 21 22 23 24 25 26 27 28 29 30 31 32 VCC DC A17 13 12 11 10 9 8 7 6 5 1 OE1/OE1/DC D0 A0 A1 A2 A3 A4 A5 A6 A7 2 A16 3 A15 4 A12 532100B-7 Figure 2. Pin Connections QFJ (PLCC) Package 1 LH532100B CMOS 2M MROM 32-PIN TSOP (Type I) TOP VIEW 32-PIN TSOP (Type II) TOP VIEW A11 A9 A8 A13 A14 A17 DC VCC OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE/OE A10 CE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3 532100B-2 OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC DC A17 A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3 NOTE: Reverse bend available on request. 532100B-3 Figure 3. Pin Connections for TSOP (Type I) Package Figure 4. Pin Connections for TSOP (Type II) Packages 2 CMOS 2M MROM LH532100B A17 30 A16 A15 A14 A13 2 3 29 28 ADDRESS DECODER ADDRESS BUFFER A12 4 A11 25 A10 23 A9 A8 A7 A6 26 27 5 6 MEMORY MATRIX (262,144 x 8) A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 COLUMN SELECTOR SENSE AMPLIFIER CE/CE 22 CE BUFFER TIMING GENERATOR OUTPUT BUFFER OE/OE 24 OE1/OE1/DC 1 OE BUFFER 32 16 VCC GND NOTE: Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II). 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 532100B-4 Figure 5. LH532100B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A0 – A17 D0 – D7 CE OE/OE Address input Data output Chip Enable input Output Enable input 1 OE1/OE1/DC VCC GND Output Enable input/ Don’t Care connection Power supply (+5 V) Ground 1 NOTE: 1. Active levels of OE/OE and OE1/ OE1/DC are mask-programmable. Selecting DC allows the outputs to be active for both high and low levels applied to this pin. It is recommended to apply either a HIGH or a LOW to the DC pin. TRUTH TABLE CE OE/OE OE1/ OE1 MODE D0 – D7 SUPPLY CURRENT H L L L NOTE: X = H or L X L/H X H/L X X L/H H/L Non selected Non selected Non selected Selected High-Z High-Z High-Z DOUT Standby (ISB) Operating (ICC) Operating (ICC) Operating (ICC) 3 LH532100B CMOS 2M MROM ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT Topr Tstg – 0.3 to +7.0 – 0.3 to VCC + 0.3 – 0.3 to VCC + 0.3 0 to +70 – 65 to +150 V V V °C °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Input ‘Low’ voltage Input ‘High’ voltage Output ‘Low’ voltage Output ‘High’ voltage Input leakage current Output leakage current VIL VIH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 I OL = 2 .0 mA I OH = – 400 µA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = tRC ( MIN.) t RC = 1 µ s t RC = tRC ( MIN.) t RC = 1 µ s CE = V IL, CE = VIH CE = 0.2 V, CE = V CC – 0.2 V f = 1 MHz T A = 25° C –0.3 2.2 2.4 0.8 VCC + 0.3 0.4 10 10 50 45 45 40 3 100 10 10 V V V V µA µA mA mA mA µA pF pF 1 2 3 Operating current Standby current ISB2 Input capacitance Output capacitance CIN COUT NOTES: 1. CE/OE/ OE1 = VIH, OE/OE1 = VIL 2. VIN = VIH or VIL, C E = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, C E = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 150 150 150 10 10 70 70 70 ns ns ns ns ns ns ns 1 NOTE: 1. This is the time required for the outputs to become high-impedance. 4 CMOS 2M MROM LH532100B AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition 0.6 V to 2.4 V 10 ns 1.5 V 0.8 V and 2.2 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A17 tAA (NOTE) CE tACE (NOTE) OE/OE1 OE/OE1 tOE (NOTE) tOHZ tOH tCHZ D0 - D7 NOTE: The output data becomes valid when the last intervals tAA, tACE, or tOE have concluded. DATA VALID 532100B-5 Figure 6. Timing Diagram 5 LH532100B CMOS 2M MROM PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 41.30 [1.626] 40.70 [1.602] 16 0.30 [0.012] 0.20 [0.008] 0° TO 15° 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 15.24 [0.600] TYP. DIMENSIONS IN MM [INCHES] 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 1.40 [0.055] 17 0.50 [0.020] 0.30 [0.012] 32 11.50 [0.453] 11.10 [0.437] 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 1 20.80 [0.819] 20.40 [0.803] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT DIMENSIONS IN MM [INCHES] 32SOP 32-pin, 525-mil SOP 6 CMOS 2M MROM LH532100B 32TSOP (Type I) (TSOP032-P-0820) 0.30 [0.012] 0.10 [0.004] 32 0.50 [0.020] TYP. 17 18.60 [0.732] 18.20 [0.717] 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 1 8.20 [0.323] 7.80 [0.307] 16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.15 [0.006] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP 32-pin, 8 × 20 mm TSOP (Type I) 32TSOP (Type II) (TSOP032-P-0400) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 2 32 17 10.40 [0.409] 12.30 [0.484] 10.00 [0.394] 11.30 [0.445] 11.00 [0.433] 10.60 [0.417] 1 21.20 [0.835] 20.80 [0.819] 16 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.4375 [0.017] 0.20 [0.008] 0.00 [0.000] 0.15 [0.006] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP400 32-pin, 400-mil TSOP (Type II) 7 LH532100B CMOS 2M MROM 32QFJ (QFJ032-P-R450) 29 21 30 20 1 11.40 [0.449] 12.50 [0.492] 12.30 [0.484] 10.90 [0.429] 10.10 [0.398] 4 14 5 14.00 [0.551] 15.10 [0.594] 14.90 [0.587] 13 0.25 [0.010] 1.20 [0.047] 1.20 [0.047] 3.50 [0.138] 2.30 [0.091] 3.10 [0.122] 1.90 [0.075] 1.27 [0.050] TYP. 0.56 [0.022] 0.36 [0.014] 13.50 [0.531] 12.70 [0.500] MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT 32QFJ450 32-pin, 450-mil QFJ (PLCC) ORDERING INFORMATION LH532100B Device Type X Package D N U T S SR 32-pin, 600-mil DIP (DIP032-P-0600) 32-pin, 525-mil SOP (SOP032-P-0525) 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450) 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) 32-pin, 400-mil TSOP (Type II) (TSOP032-P-0400) 32-pin, 400-mil TSOP (Type II) Reverse bend (TSOP032-P-0400) CMOS 2M (256K x 8) Mask-Programmable ROM Example: LH532100BD (CMOS 2M (256K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP) 532100B-6 8