LH5P832

LH5P832 FEATURES • 32,768 × 8 bit organization • Access time: 100/120 ns (MAX.) • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal counter (controlled by OE/RFSH pin) • Self refresh is executed by internal timer • Single +5 V power supply • Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP DESCRIPTION The LH5P832 is a 256K bit Pseudo-Static RAM organized as 32,768 × 8 bits. It is fabricated using silicon-gate CMOS process technology. The LH5P832 uses convenient on-chip refresh circuitry with a DRAM memory cell for pseudo static operation. This simplifies external clock inputs, while providing the same simple, non-multiplexed pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, many 32K × 8 SRAM sockets can be filled with the LH5P832 with little or no changes. The advantage is the cost savings realized with the lower cost PSRAM. CMOS 256K (32K × 8) Pseudo-Static RAM The LH5P832 PSRAM has the ability to fill the gap between DRAM and SRAM by offering low cost, low standby power, and a simple interface. Three methods of refresh control are provided for maximum versatility. A ‘CE-Only’ refresh cycle refreshes the addressed row of memory cells transparently. All 256 rows must be refreshed or accessed every four milliseconds. ‘Auto Refresh’ automatically cycles through a different row on every OE/RFSH clock pulse, accomplishing the row refreshes without the need to supply row addresses externally. ‘Self Refresh’ further simplifies the refresh requirements by eliminating the need for address inputs and clock pulses entirely. An automatic timer senses time periods when memory accesses have ceased, and provides full refresh of all rows of memory without any external assistance. PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC R/W A13 A8 A9 A11 OE/RFSH A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 5P832-1 TOP VIEW Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages 1 LH5P832 CMOS 256K (32K × 8) Pseudo-Static RAM 14 GND 28 VCC A14 1 A13 26 A12 2 A11 23 A10 21 A9 24 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 ROW ADDRESS BUFFER EXT/INT ADDRESS MUX ROW DECODER SENSE AMPS COLUMN ADDRESS BUFFER VBB BIAS-GENERATOR COLUMN DECODER I/O SELECTOR DATA IN BUFFER 11 I/O1 12 I/O2 13 I/O3 15 I/O4 16 I/O5 17 I/O6 REFRESH ADDRESS COUNTER MEMORY ARRAY 256 ROWS 128 COLUMNS DATA OUT BUFFER 18 I/O7 19 I/O8 CE 20 CLOCK GENERATOR AUTO-REFRESH CONTROLLER OE/ RFSH SELF-REFRESH TIMER 22 R/W 27 5P832-2 Figure 2. LH5P832 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME R/W OE/RFSH I/O1 - I/O8 A0 - A7 Read/Write input Output Enable/Refresh input Data inputs and outputs Row address inputs A8 - A14 CE VCC GND Column Address inputs Chip Enable input Power supply Ground TRUTH TABLE CE R/W OE/RFSH MODE I/O1 - I/O 8 ICC NOTE L L L H H H NOTES: 1. X = H or L L H H X X X X L H L L H Write Read CE-Only Refresh Auto Refresh Self Refresh Standby Data in Data out High-Z High-Z High-Z High-Z Operating (ICC1) Operating (ICC1) Operating (ICC1) Operating (ICC1) Self Refresh (ICC3) Standby (ICC2) 1 1, 2 1, 3 1 2. O E Pulsewidth < 8 µs 3. OE Pulsewidth ≥ 8 µs 2 CMOS 256K (32K × 8) Pseudo-Static RAM LH5P832 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Applied voltage on any pin Output short circuit current Power dissipation Operating temperature Storage temperature NOTE: 1. Referenced to GND VT IO PD Topr Tstg -1.0 to +7.0 50 600 0 to +70 -55 to +150 V mA mW °C °C 1 RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage Input voltage VCC VIH VIL 4.5 2.4 -1.0 5.0 5.5 VCC + 0.3 +0.8 V V V CAPACITANCE (VCC = 5.0 V ±10%, TA = 0 to +70°C, f = 1 MHz) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT Input capacitance Input/output capacitance A0 - A14, R/W CE, OE/RFSH I/O1 - I/O8 CIN1 CIN2 COUT1 8 5 12 pF pF pF DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Operating current Operating current Standby current Self refresh average current CPU internal cycle average current CPU internal cycle average current Input leakage current Output leakage current Output High voltage Output Low voltage ICC1 ICC1 ICC2 ICC3 ICC4 ICC4 ILI ILO VOH VOL tRC = 160 ns tRC = 190 ns CE = VIH , O E/RFSH = V IH CE = VIH , O E/RFSH = V IL tRC = 160 ns tRC = 190 ns 0 V ≤ V IN ≤ 6 .5 V 0 V ≤ V OUT ≤ V CC + 0.3 V IOUT = -1 mA IOUT = 4 mA -10 -10 2.4 65 55 3 3 65 55 10 10 0.4 mA mA mA mA mA mA µA µA V V 1, 2 1, 2 1 1 1, 2 1, 2 3 NOTES: 1. Specified values are with outputs open. 2. I CC1 and ICC4 depend on the cycle time. 3. The output pins are in high-impedance state. AC TEST CONDITIONS PARAMETER MODE NOTE Input voltage amplitude Input rise/fall time Timing reference level Output load conditions NOTE: 1. Includes scope and jig capacitance. 0.6 to 2.4 V 5 ns 1.5 V 1TTL gate, CL = 100 pF 1 3 LH5P832 CMOS 256K (32K × 8) Pseudo-Static RAM AC CHARACTERISTICS READ AND WRITE CYCLES 1,2 (VCC = 5.0 V ±10%, TA = 0 to 70°C) PARAMETER SYMBOL MIN. 160 ns MAX. MIN. 190 ns MAX. UNIT NOTE Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command hold time Read command setup time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Output enable from end of write Chip disable to output in High-Z Output disable to output in High-Z Write enable to output in High-Z OE setup time OE hold time OE lead time Write command pulse width Write command setup time Write command hold time Data setup time from write Data setup time from CE Data hold time from write Data hold time from C E Transition time (rise and fall) Refresh time interval tRC tRMW tCE tP tAS tAH tRCH tRCS tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tOEL tWCP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF 160 225 100 50 0 20 0 0 100 40 10 0 0 0 0 0 10 0 10 60 60 60 40 40 0 0 3 35 4 30 30 30 10,000 190 280 120 60 0 30 0 0 120 50 10 0 0 0 0 0 10 0 10 85 85 85 50 50 0 0 3 35 4 35 35 35 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 2 2 2 3 3 REFRESH CYCLE Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) CE delay time from refresh active (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh) tFC tRFD tFAP tFP tFCE tFAS tFRS 160 50 60 30 190 8,000 190 8,000 190 60 80 30 225 8,000 225 8,000 ns ns ns ns ns ns ns NOTES: 1. At least 200 µs of pause time after power on should be given for proper device operation. CE and O E/ RFSH must be fixed at VIH for 200 µs from the VDD reached to the specified voltage level and followed by at least 8 dummy cycles. 2. AC characteristics are measured at tT = 5 ns. 3. Measured with a load circuit equivalent to 1TTL loads and 100 pF. 4 CMOS 256K (32K × 8) Pseudo-Static RAM LH5P832 tRC tCE CE VIH VIL tAS V A0 - A14 VIH IL tAH ADDRESS tP tOEH OE/ RFSH VIH VIL tRCS VIH VIL tOEL tOES tRCH R/W tCEA tOEA tCHZ tOHZ DATA OUT VOH I/O1 - I/O8 VOL tOLZ tCLZ 5P832-3 Figure 3. Read Cycle tRC tCE CE VIH VIL tAS A0 - A14 VIH VIL tAH ADDRESS tP tOES OE/ RFSH VIH VIL tWCH tWCS tWCP V R/W VIH IL tDSW tDSC I/O1 - I/O8 VIH VIL DATA - IN tOEH tDHW tDHC 5P832-4 Figure 4. Write Cycle 5 LH5P832 CMOS 256K (32K × 8) Pseudo-Static RAM tRMW tCE CE VIH VIL tAS A0 - A14 VIH VIL tAH ADDRESS tP tOEH OE/ VIH RFSH VIL tRCS tWCP R/W VIH VIL tDSW tDSC VIH VIL I/O1 - I/O8 VOH VOL tOLZ tCLZ tCEA tOEA tWHZ tOHZ DATA OUT tOES tWCS tDHW tDHC DATA - IN tWLZ tCHZ 5P832-5 Figure 5. Read/Write Cycle tRC tCE CE VIH VIL tAS A0 - A7 VIH VIL tAH tP ADDRESS tOES OE/ VIH RFSH VIL V R/W VIH IL I/O1 - I/O8 VOH VOL NOTE: A8 - A14 = Don't Care HIGH-Z tOEH tRCS tRCH 5P832-6 Figure 6. CE Only Refresh Cycle 6 CMOS 256K (32K × 8) Pseudo-Static RAM LH5P832 V CE VIH IL tRFD tFAP tFC tFP tFAP tFCE OE/ VIH RFSH VIL I/O1 - I/O8 VOH VOL NOTE: A0 - A14, R/W = Don't Care HIGH-Z 5P832-7 Figure 7. Auto Refresh Cycle V CE VIH IL tRFD tFAS tFRS OE/ VIH RFSH VIL I/O1 - I/O8 VOH VOL NOTE: A0 - A14, R/W = Don't Care HIGH-Z 5P832-8 Figure 8. Self Refresh Cycle 7 LH5P832 CMOS 256K (32K × 8) Pseudo-Static RAM PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 36.30 [1.429] 35.70 [1.406] 14 0° TO 15° 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] 28DIP-2 28-Pin, 600-mil DIP 28SK-DIP (DIP028-P-0300) 28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP. DETAIL 0° TO 15° DIMENSIONS IN MM [INCHES] 28DIP-1 28-Pin, 300-mil SK-DIP 8 CMOS 256K (32K × 8) Pseudo-Static RAM LH5P832 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457] 0.50 [0.020] 0.30 [0.012] 28 10.60 [0.417] 1 18.20 [0.717] 17.80 [0.701] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-Pin, 450-mil SOP ORDERING INFORMATION LH5P832 Device Type X Package - ## Speed 10 100 Access Time (ns) 12 120 Blank 28-pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SKDIP (SKDIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) CMOS 256K (32K x 8) Pseudo Static RAM Example: LH5P832N-12 (CMOS 256K (32K x 8) Pseudo Static RAM, 120 ns, 28-pin, 450-mil SOP) 5P832-9 9