LH5PV16256

LH5PV16256 FEATURES • 262,144 words × 16 bit organization • Power supply: +3.0 ± 0.15 V • Access time: 120 ns (MAX.) • Cycle time: 190 ns (MIN.) • Power consumption (MAX.): 126 mW (Operating) 94.5 µW (Standby = CMOS input level) 220.5 µW (Self-refresh = CMOS input level) • LVTTL compatible I/O • Available for address refresh, auto-refresh, and self-refresh modes • 2,048 refresh cycles/32 ms • Address non-multiple • Available for byte write mode using UWE and LWE pins • Package: 44-pin, TSOP (Type II) • Process: Silicon-gate CMOS • Operating temperature: 0 - 70°C • Not designed or rated as radiation hardened CMOS 4M (256K × 16) Pseudo-Static RAM DESCRIPTION The LH5PV16256 is a 4M bit Pseudo-Static RAM with a 262,144 words × 16 bit organization. PIN CONNECTIONS 44-PIN TSOP (Type II) TOP VIEW LWE UWE A0 A1 A2 A3 A4 A5 A6 A17 CS A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 VCC VCC RFSH I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE GND 5PV16256S-1 Figure 1. Pin Connections 1 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM UWE 2 LWE 1 23 GND 44 GND 35 VCC 34 VCC A7 21 A8 20 A9 19 A10 18 A11 17 A 0 COLUMN A12 16 A6 ADDRESS 15 A13 BUFFER A14 14 A15 13 A16 12 A17 10 ROW A6 9 ADDRESS A5 8 A7 - BUFFER A4 7 A17 A3 6 REFRESH A2 5 ADDRESS COUNTER A1 4 A0 3 VBB GENERATOR 25 I/O0 COLUMN DECODER 26 I/O1 27 I/O2 28 I/O3 I/O SELECTOR DATA IN BUFFER 29 I/O4 30 I/O5 31 I/O6 32 I/O7 36 I/O8 EXT/INT ADDRESS MUX. ROW DECODER MEMORY ARRAY 8M DATA OUT BUFFER 37 I/O9 38 I/O10 39 I/O11 40 I/O12 41 I/O13 42 I/O14 43 I/O15 SENSE AMPS CS 11 CE 22 CLOCK GENERATOR REFRESH CONTROLLER REFRESH TIMER RFSH 33 OE 24 5PV16256S-2 Figure 2. LH5PV16256 Block Diagram PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION A7 - A17 A0 - A6 UWE, LWE OE RFSH CE Row address input Column address input Upper/lower write enable input Output enable input Refresh input Chip enable input CS I/O8 - I/O15 I/O0 - I/O7 VCC GND Chip select input Upper byte data input/output Lower byte data input/output Power supply Ground 2 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 TRUTH TABLE CE CS RFSH OE UWE LWE MODE I/O0 - 7 I/O8 - 15 L H H L H H H L H L H X X X Write Word Read Lower byte write Upper byte write Word write Invalid Auto refresh CS standby Standby Output data Input data Don’t care Input data High-Z High-Z High-Z High-Z Output data Don’t care Input data Input data High-Z High-Z High-Z High-Z L H H X L L H H L H X L X L H H X X X X X X NOTES: H = High L = Low X = Don’t care REQUIREMENTS 2WE control Please do not separate the UWE and LWE operation timing intentionally in the same write cycles. Each of the UWE/LWE should satisfy the timing specifications individually. Refresh after self-refresh or data retention mode • If address refresh is used during normal read/write cycles, the first address refresh must be executed within 15 µs after self-refresh or data retention mode ends and the address refresh must be executed continuously for 2,048 refresh cycles. • If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 µs after self-refresh or data retention mode ends. • If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 µs after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for 2,048 refresh cycles. Bypass capacitor for power supply noise reduction Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between V CC and GND to absorb power supply noise due to the peak current. 3 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage Output short circuit current Power dissipation Operating temperature Storage temperature VT IO PD TOPR TSTG -0.5 to +4.6 50 600 0 to +70 -65 to +150 V mA mW °C °C 1     NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Supply voltage Input voltage VCC GND VIH VIL 2.85 0 2.0 -0.3 3.0 0   3.15 0 VCC + 0.3 0.8 V V V V 1 1   NOTE: 1. The supply voltage with all VCC pins must be on the same level. The supply voltage with all GND pins must be on the same level. PIN CAPACITANCE (TA = 0 to +70 °C, f = 1 MHz, VCC = 3.0 V ± 0.15 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT A0 - A17 Input capacitance UWE, LWE OE, RFSH CE, CS Input/output capacitance I/O0 - I/O15 CIN1 CIN2 CIN3 COUT1     8 8 8 10 pF pF pF pF DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Operating current in normal operation Standby current ICC1 ICC2 tRC = tRC (MIN.) CE, RFSH = VIH (MIN.) CE, RFSH = VCC - 0.2 V CE = VIH (MIN.) RFSH = VIL (MAX.) CE = VCC - 0.2 V, RFSH = 0.2 V 0 V ≤ VIN ≤ 6.5 V 0 V on all other pins 0 V ≤ VOUT ≤ V CC + 0.3 V Input/output pins in High-Z state IOUT = -1 mA IOUT = -100 µ A IOUT = 1 mA IOUT = 100 µ A       -10 -10 2.4 VCC - 0.2   2.2 40 1 30 1 70 10 10   0.4 0.2 3.15 mA mA mA mA mA µA µA V V V V V 1, 2 1 1 1 1        Self-refresh average current ICC3 Input leakage current Output leakage current ILI ILO VOH VOL VR Output HIGH voltage Output LOW voltage Data retention voltage NOTES: 1. The input/output pins are in high impedance state. 2. I CC1 depends on the cycle time. 4 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 AC ELECTRICAL CHARACTERISTICS 1,2,7 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER SYMBOL MIN. MAX. UNIT NOTES Random read, write cycle time Random modify write cycle time CE pulse width CE precharge time Address setup time Row address hold time from C E Column address hold time from C E CS setup time from CE CS hold time from C E Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Write disable to output in Low-Z Chip disable to output in High-Z Output disable to output in High-Z WE to output in High-Z Write command pulse width Write command setup time Write command hold time Data setup time from write disable Data setup time from chip disable Data hold time from write disable Data hold time from chip disable Data hold time from column address Column address hold time from chip disable Column address hold time from write disable Transition time (rise and fall) Output disable setup time Output disable hold time Refresh time interval (2048 cycle) Auto refresh cycle time Refresh delay time from C E Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) CE delay time from refresh enable (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh) VCC r ecovery time from data retention Refresh setup hold time Refresh disable hold time Chip disable delay time from RFSH tRC tRMW tCE tP tAS tRAH tCAH tCSS tCSH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tWCP tWCS tWCH tDSW tDSC tDHW tDHC tOH tAHC tAHW tT tODS tODH tREF tFC tRFD tFAP tFP tFCE tFAS tFRS tR tFS tRDH tRDD 190 250 120 60 0 30 120 0 30 0 0   20 0 0 0 0 0 35 35 120 30 30 0 30 0 20 0 3 0 15  190 90 80 40 190 8,000 600 5 0 15 15   10,000         120 60    30 30 30  10,000 10,000        50   32   1,000         ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ms ns ns ns     3 3    11 9 4 4   11   9, 13 13 10, 13 12, 13 5, 12, 13 5 5, 11, 13 5  5 5, 13    6 6  8   8      5 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM NOTES: 1. AC characteristics are measured at t T = 5 ns. 2. AC characteristics are measured at the following condition: 3. Row address signals are latched in the memory at the falling edge of CE. INPUT 2.2 V 0.8 V 2.4 V 0.4 V 2.0 V 0.8 V 5PV16256S-13 OUTPUT Figure 3. AC Characteristics 4. Measured with a load equivalent to 50 pF. 5. Input data is latched in the memory at the earlier rising edge of CE and UWE/LWE. One of (t AHW , tDSW, tDHW ) and (tAHC, tDSC, tDHC) needs to be satisfied. The other is "Don’t care." 6. Address refresh or auto refresh is needed to be executed 2,048 times within 32 ms. 7. In order to initialize the internal circuits, an initial pause of 500 µs with C E = RFSH = VIH is required after power-up, and followed by at least 8 dummy cycles. When supply voltage falls down below the recommended supply voltage by temporarily power-down, a waiting time is required at VCC = 0 V f or more than 400 ms before power-up, and a pause of 500 µ s with CE = R FSH = VIH and 8 dummy cycles are also necessary after power-up. 8. Auto refresh and self refresh are defined by R FSH pulse width during C E = VIH. If R FSH pulse width is shorter than tFAP ( MAX.), the cycle is an auto refresh cycle and memory cells are refreshed by an internal counter. If RFSH pulse width is longer than t FAS (MIN.), the cycle is a self refresh cycle and memory cells are refreshed by an internal clock generator automatically. 9. t RCH and tWHZ are determined by the earlier falling edge of UWE and LWE. 10. t WCS is determined by the later falling edge of UWE and LWE. 11. t RCS, tWLZ, and t DHW are determined by the later rising edge of UWE and LWE. 12. t WCH and tDSW are determined by the earlier rising edge of UWE and LWE. 13. t WHZ, tWCP, tWCS, tWCH, tDSW, tDHW, tWLZ, and t AHW should be satisfied by both UWE and LWE. 14. The transition time of the supply voltage in data retention mode is less than 0.05 V/ms. 15. The width of data retention period is more than tFAS (MIN.) like self-refresh cycle. 16. All input pins are required to be higher than -0.3 V. 17. RFSH must be lower than 0.2 V during the data retention period. 18. CE and CS must be higher than VCC - 0.2 V during the data retention period. 6 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP VIH VIL tCSS VIH VIL tRDH tCSH tCE tP CE CS RFSH VIH VIL tAS tRAH A7 - A17 VIH VIL ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL VIH VIL tRCS UWE, LWE VIH VIL COLUMN ADDRESS INPUT OE tRCH tCEA tOEA tOH tCHZ tOHZ I/O0 - I/O15 VOH VOL tOLZ tCLZ VALID-DATA OUTPUT 5PV16256S-3 Figure 4. Read Cycle 7 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM tRC tP VIH VIL tCSS VIH VIL tRDH VIH VIL tAS A7 - A17 VIH VIL tRAH tRDD tCSH tCE tP CE CS RFSH ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL COLUMN ADDRESS INPUT tAHW OE VIH VIL tWCH tWCS tWCP UWE, LWE VIH VIL tDSW VIH VIL tWHZ tDHW VALID-DATA INPUT tOLZ tWLZ tCHZ I/O0 - I/O15 tCLZ VOH VOL tOHZ 5PV16256S-4 Figure 5. Write Cycle (1) (OE Clock) 8 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP VIH VIL tCSS VIH VIL tCSH tCE tP CE CS RFSH VIH VIL tAS tRAH A7 - A17 VIH VIL ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL V OE IH VIL COLUMN ADDRESS INPUT tAHC tWCS VIH VIL tDSC VIH VIL I/O0 - I/O15 VOH VOL 5PV16256S-5 UWE, LWE tDHC VALID-DATA INPUT tCLZ tWHZ Figure 6. Write Cycle (2) (OE = Low , CE Control) 9 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM tRMW tP VIH VIL tCSS VIH VIL tRDH tCSH tCE tP CE CS RFSH VIH VIL tAS tRAH A7 - A17 VIH VIL ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL COLUMN ADDRESS INPUT tAHC tAHW OE VIH VIL tRCS tWCP VIH VIL tDSW tDSC VIH VIL tCEA tWHZ tOHZ tDHW tDHC tWCS UWE, LWE VALID-DATA INPUT I/O0 - I/O15 tOEA VOH VOL tOLZ tCLZ VALID-DATA OUTPUT 5PV16256S-6 Figure 7. Read-Modify-Write Cycle 10 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP tCE tP CE VIH VIL tCSS VIH VIL tRDH tCSH CS RFSH VIH VIL tAS tRAH A7 - A17 VIH VIL ROW ADDRESS INPUT tODS tODH OE VIH VIL tRCS VIH VIL VOH VOL OPEN tRCH UWE, LWE I/O0 - I/O15 NOTE: A0 - A6 = Don't Care 5PV16256S-7 Figure 8. Address Refresh Cycle 11 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM CE VIH VIL tCSS VIH VIL tRFD tFP VIH VIL tFAP tFC tFP tFAP tFCE tCSH CS RFSH I/O0 - I/O15 VOH VOL OPEN NOTE: A0 - A17, UWE, LWE and OE = Don't Care 5PV16256S-8 Figure 9. Auto Refresh Cycle CE VIH VIL CS VIH VIL tRFD tFC tFP VIH VIL OPEN tFAS tFRS RFSH I/O0 - I/O15 VOH VOL NOTE: A0 - A17, UWE, LWE and OE = Don't Care 5PV16256S-9 Figure 10. Self Refresh Cycle 12 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 VCC 3.0 V VR tFS tRFD tFP VIH VIL VIH VIL VIH VIL DATA RETENTION PERIOD tFRS tR RFSH RFSH ≤ 0.2 V CE ≥ VCC -0.2 V CE CS ≥ VCC -0.2 V CS NOTE: Ao - A17, UWE, LWE and OE = Don't Care 5PV16256S-10 Figure 11. Data Retention Mode tRC tP VIH VIL tCSS VIH VIL tRFD tCSH tCE tP CE CS RFSH I/O0 - I/O15 VIH VIL VOH VOL OPEN NOTE: A0 - A17, UWE, LWE and OE = Don't Care 5PV16256S-11 Figure 12. CS Standby Mode 13 LH5PV16256 CMOS 4M (256 × 16) Pseudo-Static RAM PACKAGE DIAGRAM 44TSOP (Type II) (TSOP44-P-400) 0.38 [0.015] 0.22 [0.009] 0.80 [0.031] TYP. 0.15 [0.006] M 44 23 10.40 [0.409] 10.00 [0.394] 12.10 [0.476] 11.50 [0.453] 11.00 [0.433] 10.60 [0.417] 1 18.60 [0.732] 18.20 [0.716] 22 0.125 [0.005] 0.12 [0.005] 1.10 [0.043] 0.90 [0.035] DETAIL 1.20 [0.047] MAX. 1.10 [0.043] 0.90 [0.035] 0.10 [0.004] MAXIMUM LIMIT MINIMUM LIMIT 0.15 [0.006] 0.05 [0.002] 0.15 [0.006] 0.05 [0.002] 0 - 10° DIMENSIONS IN MM [INCHES] 44TSOP ORDERING INFORMATION LH5PV16256 Device Type S Package - ## Speed 12 120 Access Time (ns) 44-pin, 400-mil TSOP (Type II) (TSOP44-P-400) CMOS 4M (256K x 16) Pseudo-Static RAM Example: LH5PV16256S-12 (CMOS 4M (256K x 16) Pseudo-Static RAM, 120 ns, 44-pin, 400-mil TSOP) 5PV16256S-12 14