LH6V4256

LH6V4256 FUNCTION • 262,144 words × 4 bit • Access time: 100 ns (MAX) • Cycle time: 190 ns (MIN) • Fast page mode cycle time: 60 ns (MIN) • Power supply: +3.3 V ±0.3 V • Power consumption (MAX): Operating: 126 mW Standby: 0.54 mW • Built-in latch circuit for row-address, column-address, and input data • OE = Don’t care in early write operation • RAS only refresh, hidden refresh, and CAS before RAS refresh capability • On-chip refresh counter • 512 refresh cycle/8 ms • Packages: 20-pin, 300-mil DIP 26-pin, 300-mil SOJ 28-pin, 8 × 13 mm2 TSOP (Type I) CMOS 1M (256K × 4) Dynamic RAM DESCRIPTION The LH6V4256 is a 262,144 word × 4-bit dynamic RAM which allows fast page mode access. The LH6V4256 is fabricated on SHARP’s advanced CMOS double-level polysilicon gate technology. With its input multiplexed and packaged in the standard 20-pin DIP, 26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to realize memory systems with low power dissipation and large memory capacity. The LH6V4256 operates on a single +3.3 V power supply and the built-in biasing voltage generator circuit. PIN CONNECTIONS 20-PIN DIP I/O1 I/O2 WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS I/O 4 I/O3 CAS OE A8 A7 A6 A5 A4 6V4256-1 TOP VIEW Figure 1. Pin Connections for DIP Package 2-14 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 26-PIN SOJ I/O1 I/O2 WE RAS NC 1 2 3 4 5 26 25 24 23 22 VSS I/O4 I/O3 CAS OE TOP VIEW 28-PIN TSOP (Type I) TOP VIEW NC OE CAS I/O3 I/O4 VSS NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC A8 A7 A6 A5 A4 NC NC VCC A3 A2 A1 A0 NC A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 NC I/O1 I/O2 WE RAS NC 6V4256-2 6V4256-3 Figure 2. Pin Connections for SOJ Package Figure 3. Pin Connections for TSOP Package 2-15 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM I/O1 1 I/O2 2 I/O3 18 I/O4 19 OE 16 OE CLOCK GENERATOR DATA IN BUFFER DATA OUT BUFFER VBB GENERATOR WE 3 R/W CLOCK GENERATOR 10 VCC CAS 17 CAS CLOCK GENERATOR SENSE AMP. I/O GATE COLUMN DECODER 20 VSS RAS 4 RAS CLOCK GENERATOR MEMORY ARRAY 1,048,576 BITS ROW ADDRESS COUNTER REFRESH CONTROL ROW DECODER ADDRESS BUFFER 6 A0 7 A1 8 A2 9 A3 11 A4 12 A5 13 A6 14 A7 15 A8 6V4256-4 NOTE: Pin numbers apply to the 20-pin DIP. Figure 4. LH6V4256 Block Diagram PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION A0 – A8 RAS CAS WE OE Address input Row address strobe Column address strobe Write enable Output enable I/O1 – I/O4 VCC VSS NC Data input/output Power supply (+3.3 V) Power supply (0 V) No connection 2-16 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 I/O1 10 I/O2 11 I/O3 4 I/O4 5 OE 2 OE CLOCK GENERATOR DATA IN BUFFER DATA OUT BUFFER VBB GENERATOR WE 12 R/W CLOCK GENERATOR 20 VCC CAS 3 CAS CLOCK GENERATOR SENSE AMP. I/O GATE COLUMN DECODER 6 VSS RAS 13 RAS CLOCK GENERATOR MEMORY ARRAY 1,048,576 BITS ROW ADDRESS COUNTER REFRESH CONTROL ROW DECODER ADDRESS BUFFER 16 A0 17 A1 18 A2 19 A3 23 A4 24 A5 25 A6 26 A7 27 A8 6V4256-5 NOTE: Pin numbers apply to the 28-pin TSOP (Type I). Figure 5. LH6V4256 Block Diagram 2-17 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT NOTE Applied voltage on all pins Output short circuit current Power dissipation Operating temperature Storage temperature NOTE: – 0.5 to +5.5 50 1.0 0 to +70 – 65 to +150 V mA W °C °C 1 1. The maximum applicable voltage on any pin with respect to VSS. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage Input voltage VCC VSS VIH VIL 3.0 0 2. 3 – 0.3 3.3 0 3.6 0 VCC + 0.3 0.6 V V V V CAPACITANCE (TA = 0 to +70 °C, f = 1 MHz, VCC = 3.3 V ±0.3 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT Input capacitance Input/output capacitance A0 – A8 RAS, OE, CAS, W E I/O 1 – I/O 4 CIN1 CIN2 COUT1 6 7 7 pF pF pF DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT NOTE Average supply current in normal operation Supply current in standby mode RAS = CAS ≥ V CC – 0.2 V ICC1 ICC2 ICC3 ICC4 ICC5 ILI ILO VOH VOL –10 –10 2.15 35 0.15 30 35 35 10 10 mA mA mA mA mA µA µA V 1, 2, 3 1 1, 2 1, 2, 3 1, 2, 3 Average supply current in fast page mode Average supply current in CAS before R AS refresh cycle Average supply current in RAS only refresh cycle Input leakage current Output leakage current Output ‘High’ Voltage Output ‘Low’ Voltage NOTES: 0 V ≤ VIN ≤ 4.8 V 0 V except on test pins 0 V ≤ VOUT ≤ 4 .8 V Output in high-impedance state IOUT = – 2 0 0 µ A IOUT = 1 mA 0.4 V 1. Specified values are with outputs open. 2. ICC1, ICC3, ICC4, and ICC5 depend on cycle time. 3. Cycle time is 190 ns. Address transition is once at RAS = VIH and once at RAS = VIL. 2-18 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4 (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) READ CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE Random read or write cycle time Access time from RAS Access time from column address Access time from CAS Access time from OE Row address setup time Row address hold time Column address setup time Column address hold time (RAS) Column address delay time (RAS) Column address lead time (RAS) RAS pulse width RAS precharge time CAS precharge time (RAS ↓ ) CAS delay time (RAS) CAS lead time (RAS) CAS pulse width CAS hold time OE lead time (RAS) Output data disable time (CAS) Output data disable time (OE) Output data hold time (CAS) Output data hold time (OE) Read command setup time ( CAS) Read command hold time (CAS) Read command hold time (RAS ↑) Read command hold time (RAS ↓) Transition time (rise and fall) Refresh time interval tRC tRAC tAA tCAC tOEA tASR tRAH tASC tCAH tRAD tRAL tRAS tRP tCRP tRCD tRSL tCAS tCSH tROL tOFF tOEZ tSOH tOOH tRCS tRCH tRRHP tRRHN tT tREF 190 100 50 40 35 0 15 0 20 20 50 100 80 0 25 30 40 100 0 30 30 0 0 0 10 10 115 3 35 8 10,000 60 10,000 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 8 8 8 7 6 5 5 5 5 NOTES: 1. For proper memory function, at least 200 µs of pause time should be kept after power on, followed by several dummy cycles. When RAS = VIH is continued for more than 8 ms, the same dummy cycles should be given. Usually eight ordinary refresh cycles should be given. 2. The required VCC current (I CC) during power on depends on the input levels of R AS. If RAS = VIL during power on, the device goes into an active cycle, and ICC exhibits large current transients. It is recommended that R AS tracks with VCC or be held at a valid VIH during power on. 3. AC characteristics assume tT = 5 ns. 4. AC characteristics assume the following condition (see figure at right). 5. Load condition for 1TTL + 30 pF. 6. t RAD (MAX) is the maximum point for tRAD w here t RAC (MAX) is ensured, and does not represent a limit of operation. If tRAD ≥ tRAD (MAX), the access time comes under the control of tAA. 7. t RCD (MAX) is the maximum point for t , where tRAC ( MAX) is RCD ensured and does not represent a limit of operation. If tRCD ≥ tRCD (MAX), the access time comes under the control of tCAC. 8. The operation is ensured when either tRRHN, tRRHP, or tRCH is satisfied. INPUT LEVEL OUTPUT JUDGMENT LEVEL 2.3 V 0.6 V 2.15 V 0.4 V 6V4256-6 2-19 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM FAST PAGE MODE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE Fast page mode cycle time CAS precharge time CAS precharge access time Read-write cycle time (page mode) tPC tCP tCACP tPRWC 60 10 55 125 ns ns ns ns 1 NOTE: 1. t RWC, tRWD, t AWD, t CWD, and tPRWC are not restrictive operating parameters and does not represent a limit of operation. WRITE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE EARLY WRITE Write command setup time (CAS) Write command hold time (CAS) Data input setup time Data input hold time CAS setup time Write command lead time (RAS) Write command lead time (CAS) Write pulse width (WE) OE hold time (WE) tWCS tWCH tDS tDH tCWS tRWL tCWL tWP tOEH 0 15 0 20 0 30 25 15 20 ns ns ns ns ns ns ns ns ns 1 1 OE CONTROLLED NOTE: 1. t WCS and tCWS are not restrictive operating parameters. If tWCS ≥ t WCS (MIN), the cycle is an early write cycle and data out buffers remain inactive until C AS rises again. READ-WRITE CYCLE/READ-MODIFY-WRITE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read-write cycle time WE delay time (RAS) Column address delay time (WE) WE delay time (CAS) OE delay time tRWC tRWD tAWD tCWD tOED 260 135 85 65 25 ns ns ns ns ns 1 1 1 1 NOTE: 1. t RWC, tRWD, t AWD, t CWD, and tPRWC are not restrictive operating parameters and does not represent a limit of operation. CAS BEFORE RAS REFRESH CYCLE/HIDDEN REFRESH CYCLE PARAMETER SYMBOL MIN. MAX. UNIT CAS setup time (RAS) CAS hold time ( RAS) RAS • CAS precharge time (RAS ↑) RAS • CAS precharge time (RAS ↓) WE precharge time ( RAS) tCSR tCHR tRPCP tRPCN tWRP 0 20 10 115 0 ns ns ns ns ns 2-20 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 tRC tRAS VIH VIL tCAS tRCD VIH VIL tRCS tCSH tRAD tASR VIH VIL tRAH COLUMN ADDRESS tRRHP tRRHN VIH VIL tASC tCAH tROL VIH VIL tOEA tAA tCAC tRAC I/O1 - I/O4 VOH VOL tOFF tSOH tOEZ tOOH tRAL tRCH tRSL tCRP tRP RAS CAS A0 - A8 ROW ADDRESS WE OE VALID DATA-OUT 6V4256-7 Figure 6. Read Cycle 2-21 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM tRC tRAS VIH VIL tRAD tRCD VIH VIL tCSH tASR VIH VIL tRAH tASC tCAH tRSL tCAS tCRP tRP RAS CAS A0 - A8 ROW ADDRESS COLUMN ADDRESS tWCS tWCH WE VIH VIL tDS tDH I/O1 - I/O4 VIH VIL VALID DATA-IN NOTE: OE = Don't Care 6V4256-8 Figure 7. Write Cycle (Early Write) 2-22 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 tRC tRAS VIH VIL tCSH tRCD tCAS tCWL VIH VIL tRAD tASR tRAH tASC tCAH tCRP tRP RAS CAS A0 - A8 VIH VIL ROW ADDRESS COLUMN ADDRESS tCWS tRWL tWP WE VIH VIL tOEH VIH VIL tOED tOEZ VIH VIL tDS tDH OE I/O1 - I/O4 VALID DATA-IN 6V4256-9 Figure 8. Write Cycle (OE Controlled Write) 2-23 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM tRWC tRAS VIH VIL tRCD VIH VIL tCSH tRAD tRAH tASR VIH VIL tASC tCAH tCRP tRP RAS CAS A0 - A8 ROW ADDRESS COLUMN ADDRESS tRWD tAWD tRCS VIH WE V IL tOEH VIH OE V IL tOEA tCAC tAA tRAC tOED tOEZ tOOH tDH tDS tCWD tRWL tCWL tWP I/O1 - I/O4 VI/OH VI/OL VALID DATA-OUT VALID DATA-IN 6V4256-10 Figure 9. Read/Write Cycle 2-24 tRAS tRAD tRAL tRP RAS tPC tPC tCAS tCP tRSL tCP tCAS tRCD tCAS VIH VIL tCRP CMOS 1M (256K × 4 ) Dynamic RAM CAS tCSH tCAH tASR tRAH tASC COLUMN ADDRESS COLUMN ADDRESS VIH VIL tCACP tASC tCAH tASC tCAH tCACP A0 - A8 tRCS VIH VIL ROW ADDRESS COLUMN ADDRESS tRRHP WE VIH VIL tROL tAA tAA tAA Figure 10. Fast Page Mode Read Cycle tCAC tOEA tRAC tOFF tCAC tOFF tCAC VALID DATA-OUT (1) VALID DATA-OUT (2) OE VIH VIL tOEZ I/O1 - I/O4 VOH VIL VALID DATA OUT (3) 6V4256-11 LH6V4256 2-25 2-26 tRAS tRAD tRP tRCD tCAS tCP tCAS tCP tPC tPC tCAS tRSL tCRP tCSH tASC tASR tRAH tCAH tASC tCAH tASC tCAH ROW ADDRESS tWCS tWCH COLUMN ADDRESS COLUMN ADDRESS tWCS COLUMN ADDRESS tDS tDH tDS tDH tDS tDH VALID DATA-IN (1) VALID DATA-IN (2) VALID DATA-IN (3) 6V4256-12 LH6V4256 RAS VIH VIL CAS VIH VIL Figure 11. Fast Page Mode Write Cycle A0 - A8 VIH VIL VIH WE V IL I/O1 - I/O4 VIH VIL CMOS 1M (256K × 4) Dynamic RAM NOTE: OE = Don't Care tRAS tCSH tRAD tRP VIH RAS VIL tRCD tCAS tCP tCAS tCP tCAS tPRWC tPRWC tRSL VIH CAS VIL tRAH tASR tASC tASC tCAH tCAH tASC tCAH CMOS 1M (256K × 4 ) Dynamic RAM VIH A0 - A8 V IL ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tAWD tRCS tCWD tWP tCWL tAWD tCWL tCWD tWP tAWD tCWD tCWL tRWL tWP VIH WE VIL tCACP tCACP Figure 12. Fast Page Mode Read/Write Cycle tDS tCAC tAA tOEA tRAC tOED tOEZ tOOH tDH tOEA tCAC tAA tDS tOEZ tDH tOOH tOED DATA OUT DATA IN DATA OUT DATA IN VIH OE VIL tOOH tOED tOEA tCAC tAA tOEZ tDS tDH VI/OH I/O1 - I/O4 V I/OL DATA OUT DATA IN 6V4256-13 LH6V4256 2-27 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM tRC tRAS VIH VIL tASR VIH VIL tRAH tRP RAS A0 - A 8 ROW ADDRESS NOTE: CAS = 'H,' WE, OE = Don't Care 6V4256-14 Figure 13. RAS Only Refresh Cycle tRC tRAS VIH RAS VIL tCSR tCHR tRPCN VIH CAS VIL tRPCP tRP NOTE: WE, OE, A0 - A8 = Don't Care 6V4256-15 Figure 14. CAS Before RAS Refresh Cycle 2-28 tRC tRAS tRP tRAS tRP tRC V RAS VIH IL tRCD tRSL tCHR tCRP V CAS VIH IL tRAD tASR tRAH tASC ROW ADDRESS COLUMN ADDRESS tRCS tRRHP tRRHN tWRP tCAH tRAL CMOS 1M (256K × 4 ) Dynamic RAM A0 - A 8 VIH VIL V WE VIH IL tROL Figure 15. Hidden Refresh Cycle tOEA tCAC tAA tRAC VALID DATA-OUT V OE VIH IL tOFF tOEZ V I/O1 - I/O4 VI/OH I/OL LH6V4256 2-29 6V4256-16 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM PACKAGE DIAGRAMS 20DIP (DIP020-P-0300A) 20 11 7.05 [0.278] 6.65 [0.262] 1 24.75 [0.974] 24.25 [0.955] 10 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 0.51 [0.020] MIN 2.54 [0.100] TYP. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 7.62 [0.300] TYP. 0.30 [0.012] 0.20 [0.008] 0° TO 15° DIMENSIONS IN MM [INCHES] 20DIP-3 20-pin, 300-mil DIP 26SOJ (SOJ026-P-0300) 26 22 18 14 0.25 [0.010] 0.15 [0.006] 7.90 [0.311] 8.50 [0.335] 7.50 [0.295] 8.30 [0.327] 7.00 [0.276] 6.60 [0.260] 1 5 17.40 [0.685] 17.00 [0.669] 9 13 0.20 [0.008] 1.10 [0.043] 3.70 [0.146] 1.70 [0.067] 3.30 [0.130] 0.50 [0.020] 1.27 [0.050] TYP. 0.53 [0.021] 0.33 [0.013] MAXIMUM LIMIT MINIMUM LIMIT DIMENSIONS IN MM [INCHES] 26SOJ-2 26-pin, 300-mil SOJ 2-30 CMOS 1M (256K × 4 ) Dynamic RAM LH6V4256 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 28 0.55 [0.022] TYP. 15 12.00 [0.472] 11.60 [0.457] 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 1 8.20 [0.323] 7.80 [0.307] 14 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] 28TSOP DETAIL 0 - 10° DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28-pin, 8 × 13 mm2 TSOP (Type I) ORDERING INFORMATION LH6V4256 Device Type X Package - ## Speed 10 100 Access Time (ns) D 20-Pin, 300-mil DIP (DIP020-P-0300A) K 26-Pin, 300-mil SOJ (SOJ026-P-0300) T 28-Pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 1M (256K x 4) Dynamic RAM Example: LH6V4256D-10 (CMOS 1M (256K x 4) Dynamic RAM, 100 ns, 20-Pin, 300-mil DIP) 6V4256-17 2-31