LH79524/LH79525 (A.1)
System-on-Chip
Data Sheet
FEATURES
• I2C Module
• Highly Integrated System-on-Chip
• Integrated Codec Interface Support Features (I2S)
• High Performance: 76.205 MHz CPU Speed,
50.803 MHz maximum AHB clock (HCLK)
• Watchdog Timer
• Vectored Interrupt Controller
– 16 Standard and 16 Vectored IRQ Interrupts
– Interrupts Individually Configurable as IRQ or FIQ
• 32-bit ARM720T™ RISC Core
– LH79524: 32-bit External Data Bus
– 208 CABGA package
– LH79525: 16-bit External Data Bus
– 176 LQFP package
• Three UARTs
– 16-entry FIFOs for Rx and Tx
– IrDA SIR Support on all UARTs
• Three 16-bit Timers with PWM capability
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
• 8KB Cache with Write Back Buffer
• MMU (Windows CE™ Enabled)
• 16KB On-Chip SRAM
• Flexible, Programmable Memory Interface
– SDRAM Interface
– 512 MB External Address Space
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
– SRAM/Flash/ROM Interface
– 15-bit External Address Bus
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
• Multi-stream DMA Controller
– Four 32-bit Burst-Based Data Streams
• Clock and Power Management
– 32.768 kHz Oscillator for Real Time Clock
– 10 - 20 MHz Oscillator and On-chip PLL
– Active, Standby, Sleep, Stop1, and Stop2 Modes
– Externally-supplied Clock Options
• On-Chip Boot ROM
– Allows Booting from 8-, 16-, or 32-bit Devices
– NAND Flash Boot
• On-Chip regulator allows single 3.3 V supply
• Low Power Modes
– Active Mode: 85 mA (MAX.)
– Standby Mode: 50 mA (MAX.)
– Sleep Mode: 3.8 mA (TYP.)
– Stop Mode 1: 420 μA (TYP.)
– Stop Mode 2: 25 μA (TYP.)
DESCRIPTION
• USB Device
– Compliant with USB 2.0 Specifications (Full Speed)
– Four Endpoints
• Ethernet MAC, with MII and MDIO Interfaces
– IEEE 802.3 Compliant
– 10 and 100 Mbit/s Operation
• Analog-to-Digital Converter/Brownout Detector
– 10-bit ADC
– Pen Sense Interrupt
– Integrated Touch Screen Controller (TSC)
Data Sheet for Rev. A.1 Silicon
• Programmable General Purpose I/O Signals
– LH79524: 108 available pins on 14 ports
– LH79525: 86 available pins on 12 ports
• Programmable Color LCD Controller
– 16 (LH79524) or 12 (LH79525) Bits-per-Pixel
– Up to 800 × 600 resolution
– STN, Color STN, HR-TFT, AD-TFT, TFT
– TFT: Supports 64 k (LH79524) or 4 k (LH79525)
Direct Colors or 256 Colors selected from a
Palette of 64 k Colors; 15 Shades of Gray
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mbit/s
– Compatible with Common Interface Schemes
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital Inputs (excludes oscillator pins)
– XTALIN and XTAL32IN pins are 1.8 V ± 10%
The LH79524/LH79525, powered by an ARM720T,
is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and
applications. The SoC has a fully static design, power
management unit, and low voltage operation (1.8 V
Core, 3.3 V I/O). With the on-chip voltage regulator, a
single 3.3 V supply can be used as well. Robust peripherals and a low-power RISC core provide high performance at a reasonable price.
Devices containing lead-free solder formulations have different reflow
temperatures than leaded-solder formulations. When using both
solder formulations on the same PC board, consider the effect of
different reflow temperatures on the overall PCB assembly process.
ARM720T is a trademark of Advanced RISC Machines, LTD.
Version 1.0
1
LH79524/LH79525
System-on-Chip
10 - 20 MHz
LH79524/LH79525
32.768 kHz
OSCILLATOR,
PLL(2), POWER
MANAGEMENT, and
RESET CONTROL
ARM720T
REAL TIME
CLOCK
GENERAL
PURPOSE I/O
CONDITIONED
EXTERNAL
INTERRUPTS
I/O
CONFIGURATION
CACHE
INTERNAL
INTERRUPTS
VECTORED
INTERRUPT
CONTROLLER
ETHERNET
MAC
INTERNAL
16KB SRAM
SYNCHRONOUS
SERIAL PORT
SSP - I2S
CONVERTER
(WITH CODEC
INTERFACE)
BOOT
CONTROLLER
BOOT
ROM
COUNTER/
TIMER (3)
4 CHANNEL
DMA
CONTROLLER
EXTERNAL
MEMORY
CONTROLLER
ADVANCED
PERIPHERAL
BUS BRIDGE
USB
DEVICE
COLOR
LCD
CONTROLLER
TEST
SUPPORT
LINEAR
REGULATOR
ADVANCED
LCD
INTERFACE
ADVANCED HIGH
PERFORMANCE
BUS (AHB)
WATCHDOG
TIMER
I2C
16550
UART (3) w/SIR
10 CHANNEL
10-BIT ADC
(WITH TSC and
BROWNOUT
DETECTOR)
ADVANCED
PERPHERAL
BUS (APB)
LH79525-1
Figure 1. LH79524/LH79525 Block Diagram
2
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
SIGNAL DESCRIPTIONS
Table 1. LH79524 Pin Descriptions
CABGA
PIN
SIGNAL NAME
T12
A0
R11
A1
T11
A2
P10
A3
R10
A4
T10
A5
P9
A6
R9
A7
T9
A8
T8
A9
R8
A10
P8
A11
T7
A12
R7
A13
P7
A14
T6
A15
M15
D0
N16
D1
L13
D2
M14
D3
N15
D4
TYPE
DESCRIPTION
O
External Address Bus
I/O
External Data Bus
P16
D5
M13
D6
N14
D7
F14
SDCLK
O
SDRAM Clock
G15
SDCKE
O
SDRAM Clock Enable
D13
DQM0
E13
DQM1
E14
DQM2
O
Data Mask Output to SDRAMs
G14
DQM3
G16
nDCS0
O
SDRAM Chip Select
H14
nDCS1
O
SDRAM Chip Select
H15
nRAS
O
Row Address Strobe
H16
nCAS
O
Column Address Strobe
L16
nCS0/PM0
L15
nCS1/PM1
M16
nCS2/PM2
O
Static Memory Chip Select; multiplexed with GPIO Port M[3:0] (output only)
L14
nCS3/PM3
O
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[7:4] (output only)
J15
nBLE0/PM4
J14
nBLE1/PM5
K16
nBLE2/PM6
K15
nBLE3/PM7
Data Sheet for Rev. A.1 Silicon
Version 1.0
3
LH79524/LH79525
System-on-Chip
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
4
SIGNAL NAME
K14
nOE
TYPE
O
DESCRIPTION
Static Memory Output Enable
J16
nWE
O
Static Memory Write Enable
A16
USBDN
I/O
USB Data Negative (Differential Pair output, single ended and Differential pair input)
A15
USBDP
I/O
E2
AN0/UL/X+
I
ADC Input 0, 4-wire touch screen Upper Left, 5-wire touch screen X+
F2
AN1/UR/X–
I
ADC Input 1, 4-wire touch screen Upper Right, 5-wire touch screen X–
G2
AN2/LL/Y+/PJ3
I
ADC Input 2, 4-wire touch screen Lower Left, 5-wire touch screen Y+; multiplexed
with GPIO Port J3 (input only)
H2
AN3/LR/Y–/PJ0
I
ADC Input 3, 4-wire touch screen Upper Right, 5-wire touch screen Y–;
multiplexed with GPIO Port J0 (input only)
H3
AN4/WIPER/PJ1
I
ADC Input 4, 5-wire touch screen Wiper input; multiplexed with GPIO Port J1
(input only)
F1
AN5/PJ5/INT5
I
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
USB Data Positive (Differential Pair output, single ended and Differential pair input)
F3
AN6/PJ7/INT7
I
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
E1
AN7/PJ6/INT6
I
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
G3
AN8/PJ4
I
ADC Input 8; multiplexed with GPIO Port J4 (input only)
G1
AN9/PJ2
I
ADC Input 9; multiplexed with GPIO Port J2 (input only)
J3
CTCLK/INT4/BATCNTL
I/O
Timer[2:0] External Clock input; muxed with External Int 4 and Battery Control
N1
PA0/INT2/UARTRX2/
UARTIRRX2
I/O
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
M2
PA1/INT3/UARTTX2/
UARTIRTX2
I/O
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
L3
PA2/CTCAP0A/
CTCMP0A
I/O
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0
Capture A input and Counter/Timer 0 Compare A output
M1
PA3/CTCAP0B/
CTCMP0B
I/O
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0
Capture B input and Counter/Timer 0 Compare B output
L2
PA4/CTCAP1A/
CTCMP1A
I/O
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1
Capture A input and Counter/Timer 1 Compare A output
L1
PA5/CTCAP1B/
CTCMP1B
I/O
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1
Capture B input and Counter/Timer 1 Compare B output
K3
PA6/CTCAP2A/
CTCMP2A/SDA
I/O
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2
Capture A input, Counter/Timer 2 Compare A output, I2C Bus Data (open drain)
K2
PA7/CTCAP2B/
CTCMP2B/SCL
I/O
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2
Capture B input, Counter/Timer 2 Compare B output, I2C Bus Clock (open drain)
R2
PB0/nDACK/
nUARTCTS0
I/O
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
R1
PB1/DREQ/
nUARTRTS0
I/O
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
P2
PB2/SSPFRM/I2SWS
I/O
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I2S Frame Output
N3
PB3/SSPCLK/I2SCLK
I/O
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I2S Clock
M4
PB4/SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
I/O
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I2S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
P1
PB5/SSPTX/I2STXD/
UARTTX1/UARTIRTX1
I/O
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I2S Data
Out, UART1 Data Out, and UART1 IR Data Out
N2
PB6/INT0/UARTRX0/
UARTIRRX0
I/O
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
SIGNAL NAME
TYPE
DESCRIPTION
M3
PB7/INT1/UARTTX0/
UARTIRTX0
I/O
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmitted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
N7
PC0/A16
I/O
General Purpose I/O Signal — Port C0; multiplexed with Address A16
R6
PC1/A17
I/O
General Purpose I/O Signal — Port C1; multiplexed with Address A17
T5
PC2/A18
I/O
General Purpose I/O Signal — Port C2; multiplexed with Address A18
P6
PC3/A19
I/O
General Purpose I/O Signal — Port C3; multiplexed with Address A19
R5
PC4/A20
I/O
General Purpose I/O Signal — Port C4; multiplexed with Address A20
T4
PC5/A21
I/O
General Purpose I/O Signal — Port C5; multiplexed with Address A21
P5
PC6/A22/nFWE
I/O
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
R4
PC7/A23/nFRE
I/O
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
P15
PD0/D8
I/O
General Purpose I/O Signal — Port D0; multiplexed with Data D8
P14
PD1/D9
I/O
General Purpose I/O Signal — Port D1; multiplexed with Data D9
N13
PD2/D10
I/O
General Purpose I/O Signal — Port D2; multiplexed with Data D10
T15
PD3/D11
I/O
General Purpose I/O Signal — Port D3; multiplexed with Data D11
N12
PD4/D12
I/O
General Purpose I/O Signal — Port D4; multiplexed with Data D12
T14
PD5/D13
I/O
General Purpose I/O Signal — Port D5; multiplexed with Data D13
P12
PD6/D14
I/O
General Purpose I/O Signal — Port D6; multiplexed with Data D14
T13
PD7/D15
I/O
General Purpose I/O Signal — Port D7; multiplexed with Data D15
B12
PE0/LCDLP/
LCDHRLP
I/O
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
D11
PE1/LCDDCLK
I/O
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
B13
PE2/LCDPS
I/O
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
C13
PE3/LCDCLS
I/O
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
D12
PE4/LCDDSPLEN/
LCDREV
I/O
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
B16
PE5/LCDVDDEN
I/O
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
B15
PE6/LCDVEEN/
LCDMOD
I/O
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
D14
PE7/nWAIT/nDEOT
I/O
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of
Transfer
A8
PF0/LCDVD6
I/O
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
A9
PF1/LCDVD7
I/O
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
B9
PF2/LCDVD8
I/O
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
C9
PF3/LCDVD9
I/O
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
B10
PF4/LCDVD10
I/O
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
A11
PF5/LCDVD11
I/O
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
B11
PF6/LCDEN/LCDSPL
I/O
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
A12
PF7/LCDFP/LCDSPS
I/O
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver
Counter reset
A5
PG0/ETHERTXEN
I/O
General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable
B6
PG1/ETHERTXCLK
I/O
General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock
A6
PG2/LCDVD0
I/O
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
C7
PG3/LCDVD1
I/O
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
B7
PG4/LCDVD2
I/O
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
Data Sheet for Rev. A.1 Silicon
Version 1.0
5
LH79524/LH79525
System-on-Chip
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
A7
6
SIGNAL NAME
PG5/LCDVD3
TYPE
I/O
DESCRIPTION
General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3
C8
PG6/LCDVD4
I/O
General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4
B8
PG7/LCDVD5
I/O
General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5
C4
PH0/ETHERRX3
I/O
General Purpose I/O Signals — Port H0; multiplexed with Ethernet Receive
Channel 3
A3
PH1/ETHERRXDV
I/O
General Purpose I/O Signals — Port H1; multiplexed with Ethernet Data Valid
B4
PH2/ETHERRXCLK
I/O
General Purpose I/O Signals — Port H2; multiplexed with Ethernet Receive Clock
C5
PH3/ETHERTXER
I/O
General Purpose I/O Signals — Port H3; multiplexed with Ethernet Transmit Error
D6
PH4/ETHERTX0
I/O
General Purpose I/O Signals — Port H4; multiplexed with Ethernet Transmit
Channel 0
A4
PH5/ETHERTX1
I/O
General Purpose I/O Signals — Port H5; multiplexed with Ethernet Transmit
Channel 1
B5
PH6/ETHERTX2
I/O
General Purpose I/O Signals — Port H6; multiplexed with Ethernet Transmit
Channel 2
C6
PH7/ETHERTX3
I/O
General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit
Channel 3
D3
PI0/ETHERMDC
I/O
General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
Data Clock
B1
PI1/ETHERMDIO
I/O
General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management
Data I/O
B2
PI2/ETHERCOL
I/O
General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect
D4
PI3/ETHERCRS
I/O
General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
C3
PI4/ETHERRXER
I/O
General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
A1
PI5/ETHERRX0
I/O
General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive
Channel 0
A2
PI6/ETHERRX1
I/O
General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
B3
PI7/ETHERRX2
I/O
General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive
Channel 2
R16
PK0/D16
I/O
General Purpose I/O Signals — Port K0; multiplexed with data bit D16
M12
PK1/D17
I/O
General Purpose I/O Signals — Port K1; multiplexed with data bit D17
T16
PK2/D18
I/O
General Purpose I/O Signals — Port K2; multiplexed with data bit D18
R15
PK3/D19
I/O
General Purpose I/O Signals — Port K3; multiplexed with data bit D19
P13
PK4/D20
I/O
General Purpose I/O Signals — Port K4; multiplexed with data bit D20
R14
PK5/D21
I/O
General Purpose I/O Signals — Port K5; multiplexed with data bit D21
R13
PK6/D22
I/O
General Purpose I/O Signals — Port K6; multiplexed with data bit D22
N11
PK7/D23
I/O
General Purpose I/O Signals — Port K7; multiplexed with data bit D23
C1
PL0/LCDVD14
I/O
General Purpose I/O Signals — Port L0; multiplexed with LCD Video Data bit 14
C2
PL1/LCDVD15
I/O
General Purpose I/O Signals — Port L1; multiplexed with LCD Video Data bit 15
A10
PL2/LCDVD12
I/O
General Purpose I/O Signals — Port L2; multiplexed with LCD Video Data bit 12
C10
PL3/LCDVD13
I/O
General Purpose I/O Signals — Port L3; multiplexed with LCD Video Data bit 13
C12
PL4/D28
I/O
General Purpose I/O Signals — Port L4; multiplexed with Data bit D28
A14
PL5/D29
I/O
General Purpose I/O Signals — Port L5; multiplexed with Data bit D29
B14
PL6/D30
I/O
General Purpose I/O Signals — Port L6; multiplexed with Data bit D30
C14
PL7/D31
I/O
General Purpose I/O Signals — Port L7; multiplexed with Data bit D31
C11
PN0/D26
I/O
General Purpose I/O Signals — Port N0; multiplexed with Data bit D26
A13
PN1/D27
I/O
General Purpose I/O Signals — Port N1; multiplexed with Data bit D27
R12
PN2/D24
I/O
General Purpose I/O Signals — Port N2; multiplexed with Data bit D24
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
P11
SIGNAL NAME
PN3/D25
TYPE
I/O
DESCRIPTION
General Purpose I/O Signals — Port N3; multiplexed with Data bit D25
J2
nRESETIN
I
Reset Input
H1
nRESETOUT
O
Reset Output
C16
XTALIN
I
Crystal Input
C15
XTALOUT
O
Crystal Output
D16
XTAL32IN
I
32.768 kHz Crystal Oscillator Input
D15
K1
XTAL32OUT
O
32.768 kHz Crystal Oscillator Output
CLKOUT
O
Clock Out (selectable from the internal bus clock or 32.768 kHz crystal)
D2
nTRST
I
JTAG Test Reset Input
P4
TMS
I
JTAG Test Mode Select Input
T3
TCK
I
JTAG Test Clock Input
T1
TDI
I
JTAG Test Serial Data Input
P3
TDO
O
JTAG Test Data Serial Output
T2
TEST1
I
Tie HIGH for Normal Operation; pull LOW to enable Embedded ICE Debugging
R3
TEST2
I
Tie HIGH for Normal Operation; pull HIGH to enable Embedded ICE Debugging
E3
LINREGEN
I
Linear Regulator Enable
D5, E4,
E5, H13, VDDC
N5
Power Core Power Supply
D10, F4,
VSSC
J13, N4
Ground Core GND
D7, D8,
D9, F13,
G4,
G13, H4,
VDD
J4, K4,
K13, L4,
N6, N8,
N9, N10
Power Input/Output Power Supply
E12, G8,
G9, H7,
H8, H9,
H10, J7, VSS
J8, J9,
J10, K8,
K9, M5
Ground Input/Output GND
D1
VDDA0
Power Analog Power Supply for Analog-to-Digital Converter
F16
VDDA1
Power Analog Power Supply for the USB PLL
E16
VDDA2
Power Analog Power Supply for System PLL
J1
VSSA0
Ground Analog GND for Analog-to-Digital Converter
F15
VSSA1
Ground Analog GND for the USB PLL
E15
VSSA2
Ground Analog GND for System PLL
Data Sheet for Rev. A.1 Silicon
Version 1.0
7
LH79524/LH79525
System-on-Chip
Table 2. LH79524 Numerical Pin List
CABGA
NO.
FUNCTION
AT RESET
A1
PI5
ETHERRX0
8 mA
A2
PI6
ETHERRX1
8 mA
8
MULTIPLEXED
FUNCTION(S)
Table 2. LH79524 Numerical Pin List (Cont’d)
OUTPUT
DRIVE NOTES
CABGA
NO.
FUNCTION
AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE NOTES
1
C13
PE3
LCDCLS
8 mA
1
1
C14
PL7
D31
8 mA
1
A3
PH1
ETHERRXDV
8 mA
1
C15
XTALOUT
4
A4
PH5
ETHERTX1
8 mA
1
C16
XTALIN
5
A5
PG0
ETHERTXEN
8 mA
1
D1
VDDA0
A6
PG2
LCDVD0
8 mA
1
D2
nTRST
A7
PG5
LCDVD3
8 mA
1
D3
PI0
ETHERMDC
8 mA
1
A8
PF0
LCDVD6
8 mA
1
D4
PI3
ETHERCRS
8 mA
1
ETHERTX0
8 mA
1
2, 6
A9
PF1
LCDVD7
8 mA
1
D5
VDDC
A10
PL2
LCDVD12
8 mA
1
D6
PH4
A11
PF5
LCDVD11
8 mA
2
D7
VDD
A12
PF7
LCDFP/LCDSPS
8 mA
1
D8
VDD
A13
PN1
D27
8 mA
1
D9
VDD
A14
PL5
D29
8 mA
1
D10
VSSC
D11
PE1
LCDDCLK
8 mA
1
D12
PE4
LCDDSPLEN/
LCDREV
8 mA
1
D13
DQM0
A15
USBDP
3
A16
USBDN
3
B1
PI1
ETHERMDIO
8 mA
2
B2
PI2
ETHERCOL
8 mA
1
B3
PI7
ETHERRX2
8 mA
1
B4
PH2
ETHERRXCLK
8 mA
1
B5
PH6
ETHERTX2
8 mA
1
B6
PG1
ETHERTXCLK
8 mA
1
B7
PG4
LCDVD2
8 mA
1
B8
PG7
LCDVD5
8 mA
1
B9
PF2
LCDVD8
8 mA
2
B10
PF4
LCDVD10
8 mA
2
B11
PF6
LCDEN/LCDSPL
8 mA
1
B12
PE0
LCDLP/LCDHRLP
8 mA
1
B13
PE2
LCDPS
8 mA
1
D14
PE7
D15
XTAL32OUT
D16
XTAL32IN
E1
AN7
E2
AN0/UL/X+
E3
LINREGEN
E4
VDDC
E5
VDDC
8 mA
nWAIT/nDEOT
8 mA
4
5
PJ6/INT6
E12
VSS
E13
DQM1
8 mA
E14
DQM2
8 mA
E15
VSSA2
E16
VDDA2
F1
AN5
B14
PL6
D30
8 mA
1
B15
PE6
LCDVEEN/
LCDMOD
8 mA
1
B16
PE5
LCDVDDEN
8 mA
1
F2
AN1/UR/X-
C1
PL0
LCDVD14
8 mA
1
F3
AN6
C2
PL1
LCDVD15
8 mA
1
F4
VSSC
C3
PI4
ETHERRXER
8 mA
1
F13
VDD
C4
PH0
ETHERRX3
8 mA
1
F14
SDCLK
C5
PH3
ETHERTXER
8 mA
1
F15
VSSA1
PJ5/INT5
PJ7/INT7
12 mA
C6
PH7
ETHERTX3
8 mA
1
F16
VDDA1
C7
PG3
LCDVD1
8 mA
1
G1
AN9
C8
PG6
LCDVD4
8 mA
1
G2
AN2/LL/Y+
PJ3
C9
PF3
LCDVD9
8 mA
2
G3
AN8
PJ4
C10
PL3
LCDVD13
8 mA
1
G4
VDD
C11
PN0
D26
8 mA
1
G8
VSS
C12
PL4
D28
8 mA
1
G9
VSS
Version 1.0
2, 6
PJ2
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 2. LH79524 Numerical Pin List (Cont’d)
CABGA
NO.
FUNCTION
AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE NOTES
Table 2. LH79524 Numerical Pin List (Cont’d)
CABGA
NO.
FUNCTION
AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE NOTES
G13
VDD
L4
VDD
G14
DQM3
8 mA
L13
D2
G15
SDCKE
8 mA
L14
nCS3
PM3
8 mA
G16
nDCS0
8 mA
L15
nCS1
PM1
8 mA
H1
nRESETOUT
8 mA
L16
nCS0
H2
AN3/LR/Y-
H3
PJ0
VDD
H7
VSS
H8
VSS
H9
VSS
H10
VSS
H13
VDDC
H14
nDCS1
8 mA
H15
nRAS
8 mA
H16
nCAS
8 mA
J1
VSSA0
J2
nRESETIN
2, 6
INT4/BATCNTL
8 mA
2, 6
INT3/UARTTX2/
UARTIRTX2
8 mA
1, 6
M3
PB7
INT1/UARTTX0/
UARTIRTX0
8 mA
1, 6
M4
PB4
SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
8 mA
2
D17
8 mA
1
M5
VSS
M12
PK1
M13
D6
8 mA
1
M14
D3
8 mA
1
8 mA
1
M15
D0
M16
nCS2
N1
N2
PM2
8 mA
PA0
INT2/UARTRX2/
UARTIRRX2
8 mA
1, 6
PB6
INT0/UARTRX0/
UARTIRRX0
8 mA
1, 6
SSPCLK/I2SCLK
8 mA
1
A16
8 mA
1
J7
VSS
J8
VSS
J9
VSS
N3
PB3
J10
VSS
N4
VSSC
J13
VSSC
N5
VDDC
J14
nBLE1
PM5
8 mA
N6
VDD
J15
nBLE0
PM4
8 mA
N7
PC0
J16
nWE
8 mA
N8
VDD
K1
CLKOUT
K3
PA6
CTCAP2A/
CTCMP2A/SDA
K4
VDD
K8
VSS
K9
VSS
8 mA
2, 6
8 mA
2, 6
K13
VDD
K14
nOE
K15
nBLE3
PM7
8 mA
K16
nBLE2
PM6
8 mA
L1
PA5
CTCAP1B/
CTCMP1B
8 mA
CTCAP1A/
CTCMP1A
8 mA
L2
L3
PA4
PA2
8 mA
CTCAP0A/
CTCMP0A
Data Sheet for Rev. A.1 Silicon
8 mA
1, 6
1, 6
1, 6
1, 6
PA1
VDD
PA7
8 mA
M2
CTCLK
K2
8 mA
PA3
J4
8 mA
PM0
M1
J3
CTCAP2B/
CTCMP2B/SCL
1
CTCAP0B/
CTCMP0B
AN4/WIPER PJ1
H4
8 mA
N9
VDD
N10
VDD
N11
PK7
D23
8 mA
1
N12
PD4
D12
8 mA
1
N13
PD2
D10
8 mA
1
N14
D7
8 mA
1
N15
D4
8 mA
1
N16
D1
8 mA
1
P1
PB5
SSPTX/I2STXD/
UARTTX1/
UARTIRTX1
8 mA
1
P2
PB2
SSPFRM/I2SWS
8 mA
2
P3
TDO
P4
TMS
P5
PC6
A22/nFWE
8 mA
1
P6
PC3
A19
8 mA
1
P7
A14
Version 1.0
4 mA
2, 6
8 mA
9
LH79524/LH79525
System-on-Chip
Table 2. LH79524 Numerical Pin List (Cont’d)
CABGA
NO.
FUNCTION
AT RESET
P8
A11
P9
A6
P10
A3
P11
PN3
MULTIPLEXED
FUNCTION(S)
D25
OUTPUT
DRIVE NOTES
Table 2. LH79524 Numerical Pin List (Cont’d)
CABGA
NO.
FUNCTION
AT RESET
8 mA
T4
PC5
A21
8 mA
1
8 mA
T5
PC2
A18
8 mA
1
8 mA
T6
A15
8 mA
1
T7
A12
8 mA
T8
A9
8 mA
8 mA
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE NOTES
P12
PD6
D14
8 mA
1
P13
PK4
D20
8 mA
1
T9
A8
8 mA
A5
8 mA
P14
PD1
D9
8 mA
1
T10
P15
PD0
D8
8 mA
1
T11
A2
8 mA
8 mA
1
T12
A0
8 mA
T13
PD7
D15
8 mA
1
T14
PD5
D13
8 mA
1
T15
PD3
D11
8 mA
1
T16
PK2
D18
8 mA
1
P16
D5
R1
PB1
DREQ/
nUARTRTS0
8 mA
2
PB0
nDACK/
nUARTCTS0
8 mA
2
R2
R3
TEST2
R4
PC7
A23/nFRE
8 mA
1
R5
PC4
A20
8 mA
1
R6
PC1
A17
8 mA
1
R7
A13
8 mA
R8
A10
8 mA
R9
A7
8 mA
R10
A4
8 mA
R11
A1
8 mA
R12
PN2
D24
8 mA
1
R13
PK6
D22
8 mA
1
R14
PK5
D21
8 mA
1
R15
PK3
D19
8 mA
1
R16
PK0
D16
8 mA
1
T1
TDI
2, 6
T2
TEST1
2, 6
T3
TCK
2, 6
10
2, 6
NOTES:
1. Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
2. Internal pull-up. The internal pullup and pulldown resistance on all
digital I/O pins is 50KΩ.
3. USB Inputs/outputs are tristated.
4. Output is for crystal oscillator only, no drive capability.
5. Crystal Oscillator Inputs should be driven to a maximum of
1.8 V ± 10%.
6. Input with Schmitt Trigger.
7. Output Drive Values are MAX. See ‘DC Specifications’.
8. All unused analog pins, and XTAL32IN (if unused) should be tied
to ground through a 33KΩ resistor.
Table 3. TESTx PIN FUNCTION
MODE
TEST1
TEST2
nBLE0
Embedded ICE
0
1
1
Normal
1
1
x
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 4. LH79525 Pin Descriptions
PIN NO.
SIGNAL NAME
80
A0
79
A1
78
A2
77
A3
76
A4
74
A5
73
A6
72
A7
71
A8
70
A9
69
A10
67
A11
65
A12
63
A13
62
A14
61
A15
99
D0
98
D1
97
D2
96
D3
95
D4
94
D5
93
D6
91
D7
TYPE
DESCRIPTION
O
External Address Bus
I/O
External Data Bus
117
SDCLK
O
SDRAM Clock
116
SDCKE
O
SDRAM Clock Enable
119
DQM0
118
DQM1
O
Data Mask Output to SDRAMs
115
nDCS0
O
SDRAM Chip Select
114
nDCS1
O
SDRAM Chip Select
113
nRAS
O
Row Address Strobe
112
nCAS
O
Column Address Strobe
104
nCS0/PM0
103
nCS1/PM1
102
nCS2/PM2
O
Static Memory Chip Select; multiplexed with GPO Port M[3:0]
100
nCS3/PM3
110
nBLE0/PM4
109
nBLE1/PM5
O
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[5:4]
106
nOE
O
Static Memory Output Enable
111
nWE
O
Static Memory Write Enable
130
USBDN
I/O
USB Data Negative (Differential Pair output, single ended and Differential input)
131
USBDP
I/O
USB Data Positive (Differential Pair output, single ended and Differential input)
11
AN0/UL/X+
I
ADC Input 0, 4 wire touch screen Upper Left, 5 wire touch screen X+
14
AN1/UR/X–
I
ADC Input 1, 4 wire touch screen Upper Right, 5 wire touch screen X–
17
AN2/LL/Y+/PJ3
I
ADC Input 2, 4 wire touch screen Lower Left, 5 wire touch screen Y+; multiplexed with
GPIO Port J3 (input only)
Data Sheet for Rev. A.1 Silicon
Version 1.0
11
LH79524/LH79525
System-on-Chip
Table 4. LH79525 Pin Descriptions (Cont’d)
PIN NO.
12
SIGNAL NAME
TYPE
DESCRIPTION
I
ADC Input 3, 4 wire touch screen Upper Right, 5 wire touch screen Y–; multiplexed
with GPIO Port J0 (input only)
20
AN3/LR/Y–/PJ0
19
AN4/WIPER/PJ1
I
ADC Input 4, 5 wire touch screen Wiper input; multiplexed with Port J1 (input only)
15
AN5/PJ5/INT5
I
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
12
AN6/PJ7/INT7
I
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
13
AN7/PJ6/INT6
I
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
16
AN8/PJ4
I
ADC Input 8; multiplexed with GPIO Port J4 (input only)
18
AN9/PJ2
I
ADC Input 9; multiplexed with GPIO Port J2 (input only)
25
CTCLK/INT4/
BATCNTL
I/O
Timer[2:0] External Clock input; multiplexed with Battery Control and Interrupt 4
36
PA0/UARTRX2/
UARTIRRX2/INT2
I/O
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
35
PA1/UARTTX2/
UARTIRRX2/INT3
I/O
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
34
PA2/CTCAP0A/
CTCMP0A
I/O
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0 Capture A
input and Counter/Timer 0 Compare A output
32
PA3/CTCAP0B/
CTCMP0B
I/O
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0 Capture B
input and Counter/Timer 0 Compare B output
31
PA4/CTCAP1A/
CTCMP1A
I/O
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1 Capture A
input and Counter/Timer 1 Compare A output
30
PA5/CTCAP1B/
CTCMP1B
I/O
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1 Capture B
input and Counter/Timer 1 Compare B output
29
PA6/CTCAP2A/
CTCMP2A/SDA
I/O
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2 Capture A
input, Counter/Timer 2 Compare A output, and I2C Bus Data (open drain)
28
PA7/CTCAP2B/
CTCMP2B/SLC
I/O
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2 Capture B
input, Counter/Timer 2 Compare B output, and I2C Bus Clock (open drain)
44
PB0/nDACK/
nUARTCTS0
I/O
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
43
PB1/DREQ/
nUARTRTS0
I/O
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
42
PB2/SSPFRM/
I2SWS
I/O
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I2S Frame Output
41
PB3/SSPCLK/
I2SCLK
I/O
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I2S Clock
40
PB4/SSPRX/
I2SRXD/UARTRX1/
UARTIRRX1
I/O
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I2S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
39
PB5/SSPTX/
I2STXD/UARTTX1/
UARTIRTX1
I/O
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I2S Data Out,
UART1 Data Out, and UART1 IR Data Out
38
PB6/INT0/
UARTRX0/
UARTIRRX0
I/O
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
37
PB7/INT1/
UARTTX0/
UARTIRTX0
I/O
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmitted
Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1
60
PC0/A16
I/O
General Purpose I/O Signal — Port C0; multiplexed with Address A16
59
PC1/A17
I/O
General Purpose I/O Signal — Port C1; multiplexed with Address A17
58
PC2/A18
I/O
General Purpose I/O Signal — Port C2; multiplexed with Address A18
56
PC3/A19
I/O
General Purpose I/O Signal — Port C3; multiplexed with Address A19
55
PC4/A20
I/O
General Purpose I/O Signal — Port C4; multiplexed with Address A20
54
PC5/A21
I/O
General Purpose I/O Signal — Port C5; multiplexed with Address A21
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 4. LH79525 Pin Descriptions (Cont’d)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
53
PC6/A22/nFWE
I/O
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
52
PC7/A23/nFRE
I/O
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
90
PD0/D8
I/O
General Purpose I/O Signal — Port D0; multiplexed with Data D8
89
PD1/D9
I/O
General Purpose I/O Signal — Port D1; multiplexed with Data D9
88
PD2/D10
I/O
General Purpose I/O Signal — Port D2; multiplexed with Data D10
87
PD3/D11
I/O
General Purpose I/O Signal — Port D3; multiplexed with Data D11
85
PD4/D12
I/O
General Purpose I/O Signal — Port D4; multiplexed with Data D12
84
PD5/D13
I/O
General Purpose I/O Signal — Port D5; multiplexed with Data D13
83
PD6/D14
I/O
General Purpose I/O Signal — Port D6; multiplexed with Data D14
82
PD7/D15
I/O
General Purpose I/O Signal — Port D7; multiplexed with Data D15
141
PE0/LCDLP/
LCDHRLP
I/O
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
139
PE1/LCDDCLK
I/O
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
138
PE2/LCDPS
I/O
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
137
PE3/LCDCLS
I/O
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
136
PE4/LCDDSPLEN/
LCDREV
I/O
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
134
PE5/LCDVDDEN
I/O
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
133
PE6LCDVEEN/
LCDMOD
I/O
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
120
PE7/nWAIT/nDEOT
I/O
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA
End of Transfer
153
PF0/LCDVD6
I/O
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
151
PF1/LCDVD7
I/O
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
149
PF2/LCDVD8
I/O
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
147
PF3/LCDVD9
I/O
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
146
PF4/LCDVD10
I/O
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
145
PF5/LCDVD11
I/O
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
143
PF6/LCDEN/
LCDSPL
I/O
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
142
PF7/LCDFP/
LCDSPS
I/O
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver Counter reset
162
PG0/ETHERTXEN
I/O
General Purpose I/O Signals — Port G0; multiplexed with Ethernet Transmit Enable
161
PG1/ETHERTXCLK
I/O
General Purpose I/O Signals — Port G1; multiplexed with Ethernet Clock
159
PG2/LCDVD0
I/O
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
158
PG3/LCDVD1
I/O
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
157
PG4/LCDVD2
I/O
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
156
PG5/LCDVD3
I/O
General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3
155
PG6/LCDVD4
I/O
General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4
154
PG7/LCDVD5
I/O
General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5
171
PH0/ETHERRX3
I/O
General Purpose I/O Signals — Port H0; multiplexed with Ethernet Receive Channel 3
170
PH1/ETHERRXDV
I/O
General Purpose I/O Signals — Port H1; multiplexed with Ethernet Data Valid
169
PH2/ETHERRXCLK
I/O
General Purpose I/O Signals — Port H2; multiplexed with Ethernet Receive Clock
167
PH3/ETHERTXER
I/O
General Purpose I/O Signals — Port H3; multiplexed with Ethernet Transmit Error
166
PH4/ETHERTX0
I/O
General Purpose I/O Signals — Port H4; multiplexed with Ethernet Transmit Channel 0
165
PH5/ETHERTX1
I/O
General Purpose I/O Signals — Port H5; multiplexed with Ethernet Transmit Channel 1
Data Sheet for Rev. A.1 Silicon
Version 1.0
13
LH79524/LH79525
System-on-Chip
Table 4. LH79525 Pin Descriptions (Cont’d)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
164
PH6/ETHERTX2
I/O
General Purpose I/O Signals — Port H6; multiplexed with Ethernet Transmit Channel 2
163
PH7/ETHERTX3
I/O
General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3
4
PI0/ETHERMDC
I/O
General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
Data Clock
2
PI1/ETHERMDIO
I/O
General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management Data I/O
1
PI2/ETHERCOL
I/O
General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect
176
PI3/ETHERCRS
I/O
General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
175
PI4/ETHERRXER
I/O
General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
174
PI5/ETHERRX0
I/O
General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive Channel 0
173
PI6/ETHERRX1
I/O
General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
172
PI7/ETHERRX2
I/O
General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive Channel 2
24
nRESETIN
I
Reset Input
22
nRESETOUT
O
Reset Output
127
XTALIN
I
Crystal Input, or external clock input
128
XTALOUT
O
Crystal Output
125
XTAL32IN
I
32.768 kHz Crystal Oscillator Input, or external clock input,
126
XTAL32OUT
O
32.768 kHz Crystal Oscillator Output
23
CLKOUT
O
Clock Out (selectable from the internal bus clock or 32.768 MHz)
8
nTRST
I
JTAG Test Reset Input
50
TMS
I
JTAG Test Mode Select Input
51
TCK
I
JTAG Test Clock Input
46
TDI
I
JTAG Test Serial Data Input
45
TDO
O
JTAG Test Data Serial Output
47
TEST1
I
Tie HIGH for Normal Operation; pull LOW to enable embedded ICE Debugging
48
TEST2
I
Tie HIGH for Normal Operation; pull HIGH to enable embedded ICE Debugging
9
LINREGEN
I
Linear Regulator Enable (Requires pull-up. See User’s Guide)
6, 66,
VDDC
107, 150
Power Core Power Supply
7, 64,
VSSC
105,148
Ground Core GND
3, 26, 33,
57, 75,
86, 101, VDD
129, 135,
144, 160
Power Input/Output Power Supply
5, 27, 49,
68, 81,
92, 108, VSS
132, 140,
152, 168
Ground Input/Output GND
10
VDDA0
Power Analog Power Supply for Analog-to-Digital Converter
122
VDDA1
Power Analog Power Supply for the USB PLL
123
VDDA2
Power Analog Power Supply for System PLL
21
VSSA0
Ground Analog GND for Analog-to-Digital Converter
121
VSSA1
Ground Analog GND for the USB PLL
124
VSSA2
Ground Analog GND for System PLL
14
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 5. LH79525 Numerical Pin List
MULTIPLEXED
FUNCTION(S)
Table 5. LH79525 Numerical Pin List (Cont’d)
PIN
NO.
FUNCTION
AT RESET
1
PI2
ETHERCOL
8 mA
1
46
TDI
2, 3
2
PI1
ETHERMDIO
8 mA
2
47
TEST1
2, 3
3
VDD
48
TEST2
2, 3
ETHERMDC
OUTPUT
NOTES
DRIVE
8 mA
1
PIN
NO.
FUNCTION
AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
NOTES
DRIVE
4
PI0
49
VSS
5
VSS
50
TMS
2, 3
6
VDDC
51
TCK
2, 3
52
PC7
A23/nFRE
8 mA
1
53
PC6
A22/nFWE
8 mA
1
7
VSSC
8
nTRST
9
LINREGEN
54
PC5
A21
8 mA
1
10
VDDA0
55
PC4
A20
8 mA
1
11
AN0/UL/X+
56
PC3
A19
8 mA
1
12
AN6
PJ7/INT7
57
VDD
13
AN7
PJ6/INT6
58
PC2
A18
8 mA
1
14
AN1/UR/X-
59
PC1
A17
8 mA
1
15
AN5
PJ5/INT5
60
PC0
A16
8 mA
1
16
AN8
PJ4
61
A15
8 mA
17
AN2/LL/Y+
PJ3
62
A14
8 mA
AN9
PJ2
63
A13
8 mA
AN4/WIPER PJ1
64
VSSC
18
19
2, 3
A12
66
VDDC
8 mA
AN3/LR/Y-
21
VSSA0
22
nRESETOUT
8 mA
67
A11
23
CLKOUT
8 mA
68
VSS
24
nRESETIN
2, 3
69
A10
8 mA
25
CTCLK
2, 3
70
A9
8 mA
26
VDD
71
A8
8 mA
27
VSS
72
A7
8 mA
73
A6
8 mA
74
A5
8 mA
75
VDD
76
A4
8 mA
77
A3
8 mA
78
A2
8 mA
79
A1
8 mA
80
A0
8 mA
81
VSS
82
PD7
D15
8 mA
1
83
PD6
D14
8 mA
1
84
PD5
D13
8 mA
1
85
PD4
D12
8 mA
1
86
VDD
87
PD3
D11
8 mA
1
88
PD2
D10
8 mA
1
89
PD1
D9
8 mA
1
90
PD0
D8
8 mA
1
91
D7
8 mA
1
92
VSS
93
D6
8 mA
1
94
D5
8 mA
1
95
D4
8 mA
1
96
D3
8 mA
1
28
PA7
PJ0
65
20
INT4/BATCNTL
CTCAP2B/CTCMP2B/
SCL
8 mA
8 mA
2, 3
29
PA6
CTCAP2A/CTCMP2A/
SDA
30
PA5
CTCAP1B/CTCMP1B
8 mA
1, 3
31
PA4
CTCAP1A/CTCMP1A
8 mA
1, 3
32
PA3
CTCAP0B/CTCMP0B
8 mA
1, 3
33
VDD
34
PA2
CTCAP0A/CTCMP0A
8 mA
1, 3
35
PA1
INT3/UARTTX2/
UARTIRTX2
8 mA
1, 3
36
PA0
INT2/UARTRX2/
UARTIRRX2
8 mA
1, 3
37
PB7
INT1/UARTTX0/
UARTIRTX0
8 mA
1, 3
38
PB6
INT0/UARTRX0/
UARTIRRX0
8 mA
1, 3
39
PB5
SSPTX/I2STXD/
UARTTX1/UARTIRTX1
40
PB4
SSPRX/I2SRXD/
UARTRX1/UARTIRRX1
8 mA
2, 3
8 mA
1
8 mA
2
41
PB3
SSPCLK/I2SCLK
8 mA
1
42
PB2
SSPFRM/I2SWS
8 mA
2
43
PB1
44
PB0
45
TDO
DREQ/nUARTRTS0
nDACK/nUARTCTS0
Data Sheet for Rev. A.1 Silicon
8 mA
8 mA
4 mA
2
2
Version 1.0
8 mA
15
LH79524/LH79525
System-on-Chip
Table 5. LH79525 Numerical Pin List (Cont’d)
MULTIPLEXED
FUNCTION(S)
PIN
NO.
FUNCTION
AT RESET
97
D2
8 mA
1
147
PF3
98
D1
8 mA
1
148
VSSC
99
D0
8 mA
1
149
PF2
150
VDDC
FUNCTION
AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
NOTES
DRIVE
LCDVD9
8 mA
2
LCDVD8
8 mA
2
LCDVD7
8 mA
1
nCS3
101
VDD
151
PF1
102
nCS2
PM2
8 mA
152
VSS
103
nCS1
PM1
8 mA
153
PF0
LCDVD6
8 mA
1
104
nCS0
PM0
8 mA
154
PG7
LCDVD5
8 mA
1
105
VSSC
155
PG6
LCDVD4
8 mA
1
106
nOE
156
PG5
LCDVD3
8 mA
1
VDDC
157
PG4
LCDVD2
8 mA
1
VSS
158
PG3
LCDVD1
8 mA
1
109
nBLE1
PM5
8 mA
159
PG2
LCDVD0
8 mA
1
110
nBLE0
PM4
8 mA
160
VDD
111
nWE
8 mA
161
PG1
ETHERTXCLK
8 mA
1
112
nCAS
8 mA
162
PG0
ETHERTXEN
8 mA
1
113
nRAS
8 mA
163
PH7
ETHERTX3
8 mA
1
114
nDCS1
8 mA
164
PH6
ETHERTX2
8 mA
1
8 mA
165
PH5
ETHERTX1
8 mA
1
PH4
ETHERTX0
8 mA
1
ETHERTXER
8 mA
1
1
108
115
8 mA
PIN
NO.
100
107
PM3
OUTPUT
NOTES
DRIVE
Table 5. LH79525 Numerical Pin List (Cont’d)
8 mA
nDCS0
116
SDCKE
8 mA
166
117
SDCLK
12 mA
167
PH3
118
DQM1
8 mA
168
VSS
119
DQM0
8 mA
169
PH2
ETHERRXCLK
8 mA
8 mA
170
PH1
ETHERRXDV
8 mA
1
PH0
ETHERRX3
8 mA
1
120
PE7
nWAIT/nDEOT
2, 3
121
VSSA1
171
122
VDDA1
172
PI7
ETHERRX2
8 mA
1
VDDA2
173
PI6
ETHERRX1
8 mA
1
1
123
124
VSSA2
174
PI5
ETHERRX0
8 mA
125
XTAL32IN
5
175
PI4
ETHERRXER
8 mA
1
126
XTAL32OUT
6
176
PI3
ETHERCRS
8 mA
1
127
XTALIN
5
128
XTALOUT
6
129
VDD
130
USBDN
7
131
USBDP
7
132
VSS
133
PE6
LCDVEEN/
LCDMOD
8 mA
1
134
PE5
LCDVDDEN
8 mA
1
135
VDD
136
PE4
LCDDSPLEN/LCDREV
8 mA
1
137
PE3
LCDCLS
8 mA
1
138
PE2
LCDPS
8 mA
1
139
PE1
LCDDCLK
8 mA
1
140
VSS
141
PE0
LCDLP/LCDHRLP
8 mA
1
142
PF7
LCDFP/LCDSPS
8 mA
1
143
PF6
LCDEN/LCDSPL
8 mA
1
144
VDD
145
PF5
LCDVD11
8 mA
2
146
PF4
LCDVD10
8 mA
2
16
NOTES:
1. Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
2. Internal pull-up. The internal pullup and pulldown resistance on all
digital I/O pins is 50KΩ.
3. Input with Schmitt Trigger.
4. Crystal Inputs should be driven to a maximum of 1.8 V ± 10%.
5. Output is for crystal oscillator only, no drive capability.
6. USB Inputs/outputs are tristated.
7. Output Drive Values shown are MAX. See ‘DC Specifications’.
8. All unused analog pins, and XTAL32IN (if unused) should be tied
to ground through a 33KΩ resistor.
Table 6. TESTx PIN FUNCTION
MODE
TEST1
TEST2
nBLE0
Embedded ICE
0
1
1
Normal
1
1
x
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 7. LH79524 LCD Data Multiplexing
STN
CABGA
BALL
NO.
CABGA
BALL NAME
C2
C1
MONO 4-BIT
TFT
MONO 8-BIT
COLOR
COLOR
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
LCDVD15
MUSTN0
MUSTN0
MUSTN0
MUSTN0
CUSTN0
CUSTN0
INTENSITY
LCDVD14
X
X
X
MLSTN4
X
CLSTN4
BLUE4
C10
LCDVD13
X
X
MUSTN6
MUSTN6
CUSTN6
CUSTN6
BLUE3
A10
LCDVD12
X
X
X
MLSTN7
X
CLSTN7
BLUE2
A11
LCDVD11
X
X
X
MLSTN6
X
CLSTN6
BLUE1
B10
LCDVD10
X
X
X
MLSTN5
X
CLSTN5
BLUE0
C9
LCDVD9
X
MLSTN3
X
MLSTN3
X
CLSTN3
GREEN4
B9
LCDVD8
X
MLSTN2
X
MLSTN2
X
CLSTN2
GREEN3
A9
LCDVD7
X
MLSTN1
X
MLSTN1
X
CLSTN1
GREEN2
A8
LCDVD6
X
MLSTN0
X
MLSTN0
X
CLSTN0
GREEN1
B8
LCDVD5
X
X
MUSTN7
MUSTN7
CUSTN7
CUSTN7
GREEN0
C8
LCDVD4
X
X
MUSTN5
MUSTN5
CUSTN5
CUSTN5
RED4
A7
LCDVD3
X
X
MUSTN4
MUSTN4
CUSTN4
CUSTN4
RED3
B7
LCDVD2
MUSTN3
MUSTN3
MUSTN3
MUSTN3
CUSTN3
CUSTN3
RED2
C7
LCDVD1
MUSTN2
MUSTN2
MUSTN2
MUSTN2
CUSTN2
CUSTN2
RED1
A6
LCDVD0
MUSTN1
MUSTN1
MUSTN1
MUSTN1
CUSTN1
CUSTN1
RED0
NOTES:
1. Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown.
2. The Intensity bit is identically generated for all three colors.
3. Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel.
4. CLSTN = Color Lower data bit for STN panel.
5. CUSTN = Color Upper data bit for STN panel.
6. MLSTN = Monochrome Lower data bit for STN panel.
7. MUSTN = Monochrome Upper data bit for STN panel.
Table 8. LH79525 LCD Data Multiplexing
PIN NO.
PIN NAME
145
STN MONO 4-BIT
SINGLE PANEL
DUAL PANEL
LCDVD11
MUSTN1
MUSTN1
146
LCDVD10
MUSTN0
MUSTN0
147
LCDVD9
149
LCDVD8
151
LCDVD7
MLSTN3
153
LCDVD6
MLSTN2
154
LCDVD5
MLSTN1
155
LCDVD4
MLSTN0
156
LCDVD3
157
LCDVD2
158
LCDVD1
MUSTN3
MUSTN3
159
LCDVD0
MUSTN2
MUSTN2
Data Sheet for Rev. A.1 Silicon
Version 1.0
17
LH79524/LH79525
System-on-Chip
TOUCH SCREEN
LCD
WIRELESS
ROUTER/
SWITCHER
ETHERNET
TRANSCEIVER
ETHERNET
MAC
STN/TFT,
AD-TFT
A/D
UART
CODEC
FLASH
I 2S
LH79524/LH79525
SRAM or
SDRAM
A/D
UART
USB
GPIO
SENSOR
ARRAY
1
2
3
4
5
6
7
8
9
*
0
#
SSP
BOOT
ROM
SERIAL
EEPROM
KEY
MATRIX
LH79525-19A
Figure 2. LH79524/LH79525 Application Diagram Example
SYSTEM DESCRIPTIONS
ARM720T Processor
The LH79524/LH79525 microcontrollers feature
the ARM720T cached core with an Advanced High-Performance Bus (AHB) interface. The ARM720T features:
• 32-bit ARM720T RISC Core
• 8KB Cache
• MMU (Windows CE enabled)
The core processor for both is a member of the
ARM7T family of processors. For more information, see
the ARM document, ‘ARM720T (Rev 3) Technical
Reference Manual’, available on ARM’s website at
www.ARM.com.
The LH79524/LH79525 MMU allows mapping Physical Memory (PA) addresses to virtual memory
18
addresses. This allows physical memory, which is
constrained by hardware to specific addresses, to be
reorganized at addresses identified by the user. These
user identified locations are called Virtual Addresses
(VA). When the MMU is enabled, Code and Data must
be built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU
is directly controlled through the System Control
Coprocessor, Coprocessor 15 (CP15). The MMU is
indirectly controlled by a Translation Table (TT) and
Page Tables (PT) prepared by the user and established using a portion of physical memory dedicated by
the user to storing the TT and PT’s.
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
External Memory Controller
An integrated External Memory Controller (EMC)
provides a glueless interface to external SDRAM, Low
Power SDRAM, Flash, SRAM, ROM, and burst ROM.
Three remap options for the physical memory are
selectable by software, as shown in Figure 3 through
Figure 6.
The EMC supports six banks of external memory. Two
chip selects for synchronous memory, and either two
(LH79525) or four (LH79524) static memory chip selects
are available. The static interface also includes two
(LH79525) or four (LH79524) byte lane enable signals.
0xFFFFFFFF
0xFFFF1000
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
RESERVED
0xFFFF0000
ADVANCED PERIPHERAL BUS
PERIPHERALS
0xFFFC0000
RESERVED
0xA0000000
BOOT ROM
0x80000000
16KB INTERNAL SRAM
0x60000000
EXTERNAL STATIC MEMORY
0xFFFFFFFF
0xFFFF1000
0x40000000
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
EXTERNAL SDRAM
0x20000000
RESERVED
EXTERNAL SDRAM nDCS0
0xFFFF0000
0x00000000
ADVANCED PERIPHERAL BUS
PERIPHERALS
REMAP = 01
0xFFFC0000
LH79525-16
RESERVED
0xA0000000
Figure 4. Memory Remap ‘01’
BOOT ROM
0x80000000
16KB INTERNAL SRAM
0xFFFFFFFF
0x60000000
EXTERNAL STATIC MEMORY
0xFFFF1000
0x40000000
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
RESERVED
EXTERNAL SDRAM
0xFFFF0000
0x20000000
ADVANCED PERIPHERAL BUS
PERIPHERALS
EXTERNAL SRAM nCS1
0xFFFC0000
0x00000000
RESERVED
REMAP = 00
0xA0000000
LH79525-15
Figure 3. Memory Remap ‘00’
BOOT ROM
0x80000000
16KB INTERNAL SRAM
0x60000000
EXTERNAL STATIC MEMORY
0x40000000
EXTERNAL SDRAM
0x20000000
INTERNAL SRAM
0x00000000
REMAP = 10
LH79525-17
Figure 5. Memory Remap ‘10’
Data Sheet for Rev. A.1 Silicon
Version 1.0
19
LH79524/LH79525
System-on-Chip
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 1,024 × 1,024
0xFFFFFFFF
0xFFFF1000
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
• 15 gray-level mono, 3,375 color STN, and 64 k color
TFT support
RESERVED
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
ADVANCED PERIPHERAL BUS
PERIPHERALS
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT (1-, 2-, or 4-bit only on LH79525)
0xFFFF0000
0xFFFC0000
• True-color non-palettized, for color STN and TFT
RESERVED
• Programmable timing for different display panels
0xA0000000
• 256-entry, 16-bit palette fast-access RAM
BOOT ROM
• Frame, line and pixel clock signals
0x80000000
16KB INTERNAL SRAM
• AC bias signal for STN or data enable signal for
TFT panels
0x60000000
EXTERNAL STATIC MEMORY
• Patented grayscale algorithm
0x40000000
• Interrupt Generation Events
EXTERNAL SDRAM
• Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
0x20000000
EXTERNAL SRAM nCS0
0x00000000
REMAP = 11
LH79525-18
Figure 6. Memory Remap ‘11’
DMA Controller
The DMA Controller provides support for DMAcapable peripherals. The LCD controller uses its own
DMA port, connecting directly to memory for retrieving
display data.
• Simultaneous servicing of up to 4 data streams
• Three transfer modes are supported:
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
• Identical source and destination capabilities
• Transfer Size Programmable (byte, half-word, word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Transfer Error interrupt for each stream
• 16-word FIFO array with pack and unpack logic
Handles all combinations of byte, half-word or word
transfers from input to output.
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• LH79524 has 16 LCD Data bits; LH79525 has 12
LCD Data bits.
• Supports single and dual scan color and monochrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces (LH79524 only)
20
ADVANCED LCD INTERFACE
The Advanced LCD Interface (ALI) allows for direct
connection to ultra-thin panels that do not include a timing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column drivers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The Advanced LCD
Interface peripheral also provides a bypass mode that
allows the LH79524/LH79525 to interface to the built-in
timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
The SSP is a master or slave interface for synchronous serial communication with master or slave peripheral devices that support protocols for Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Interface.
• Master or slave operation
• Programmable clock rate
• Separate transmit FIFO and receive FIFO buffers,
16 bits wide, 8 locations deep
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive
FIFO and receive overrun interrupts
• Available internal loopback test mode.
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Universal Asynchronous Receiver
Transmitter (UART)
The LH79524/LH79525 incorporates three UARTs.
UART0, UART1, and UART2 offer similar functionality
to the industry-standard 16C550. They perform serialto-parallel conversion on data received from a peripheral device and parallel-to-serial conversion on data
transmitted to the UART. The CPU reads and writes
data and control status information through the AMBA
APB interface. The transmit and receive paths are buffered with internal FIFO memories that support programmable-service 'trigger levels', and overrun
protection. These FIFO memories enable up to 32
characters to be stored independently in both transmit
and receive modes.
• Programmable bits-per-character (5, 6, 7, or 8)
• Optional nine-bit mode to tag and recognize
characters as either data or address
• Nine-bit Transmit FIFO and 12-bit Receive FIFO
• Programmable FIFO trigger points
• DMA support for UART0
• Programmable IrDA SIR input/output for each UART
• Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts
• Programmable FIFO disabling for 1-byte depth
• Programmable baud rate generator
• Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the highest priority interrupt source. This significantly improves
the real-time capabilities of the LH79524/LH79525 in
embedded control applications.
• 20 internal and eight external interrupt sources
– Individually maskable
– Status accessible for software polling
• IRQ interrupt vector logic for up to 16 channels with
programmable priorities
• All of the interrupt channels, with the exception of the
Watchdog Timer interrupt, can be programmed to
generate:
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
poll IRQ source)
– Vectored IRQ interrupt request (up to 16 channels total)
• The Watchdog timer can only generate FIQ interrupt
requests
• External interrupt inputs programmable
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
LOW
The 32 interrupt channels are shown in Table 9.
Table 9. Interrupt Channels
• False start bit detection
• Line break generation and detection
CHANNEL
INTERRUPT SOURCE
• Fully-programmable serial interface characteristics:
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd-, or no-parity bit generation and
detection
– 1 or 2 stop bit generation
0
WDT
1
Not Used
2
COMRX (used for debug)
3
COMTX (used for debug)
• IrDA SIR Encode/Decode block, providing:
– Programmable use of IrDA SIR or UART input/
output
– Supports data rates up to 115.2 kbit/s half-duplex
– Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
– Loopback for testing
4
Counter/Timer0 Combined
5
Counter/Timer1 Combined
6
Counter/Timer2 Combined
7
External Interrupt 0
8
External Interrupt 1
9
External Interrupt 2
10
External Interrupt 3
11
External Interrupt 4
12
External Interrupt 5
13
External Interrupt 6
Vectored Interrupt Controller (VIC)
The Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
The Interrupt Controller incorporates a hardware
Data Sheet for Rev. A.1 Silicon
Version 1.0
14
External Interrupt 7
15
RTC_ALARM
16
ACD TSIRQ Combined
17
ADC Brown Out INTR
21
LH79524/LH79525
System-on-Chip
Table 9. Interrupt Channels (Cont’d)
CHANNEL
Table 10. Maximum Clock Speeds
INTERRUPT SOURCE
FREQUENCY
(MAX.)
NAME
18
ADC Pen IRQ
19
CLCD Combined Interrupt
Oscillator Clock (CLK OSC)
20
DMA Stream 0
PLL System Clock (CLK PLL)
21
DMA Stream 1
PLL USB Clock
22
DMA Stream 2
32.768 kHz Oscillator Clock
32.768 kHz
23
DMA Stream 3
AHB Clock (HCLK)
50.803 MHz
24
2S
SSP I
Interrupt
20.0 MHz
304.819 MHz
48.0 MHz
AHB Fast CPU Clock (FCLK CPU)
76.205 MHz
50.803 MHz
25
Ethernet Interrupt
Ethernet Clock
26
USB Interrupt
DMA Clock
50.803 MHz
27
UART 0 Interrupt
External Memory Controller Clock
50.803 MHz
28
UART 1 Interrupt
SSP Clock
50.803 MHz
29
UART 2 Interrupt
CLCD Clock
50.803 MHz
30
USB DMA Interrupt
UART[2:0] Clock
31
I
2C
Interrupt
20.0 MHz
RTC Clock
Reset, Clock, and Power Controller (RCPC)
The RCPC generates the various clock signals for the
operation of the LH79524/LH79525 and provides for an
orderly start-up after power-on and during a wake-up
from one of the power saving operating modes. The
RCPC allows the software to individually select the frequency of the various on-chip clock signals as required
to operate the chip in the most power-efficient mode.
The maximum speeds of the various clocks in the SoC
are shown in Table 10. More detailed descriptions of
each clock appear in the User’s Guide.
1.0 Hz
Table 11. Clock Activity for Different Power Modes
DEVICE
ACTIVE STANDBY SLEEP STOP1 STOP2
RTC 32 kHz
Oscillator
ON
ON
ON
ON
ON
10 - 20 MHz
Oscillator
ON
ON
ON
ON
OFF
PLL
ON
ON
ON
OFF
OFF
Peripheral
Clock
ON
ON
OFF
OFF
OFF
CPU Clock
ON
OFF
OFF
OFF
OFF
The RCPC features:
• 10 - 20 MHz crystal oscillator and PLL for on-chip
Clock generation (11.2896 MHz recommended)
• External Clock input if on-chip oscillator and PLL are
not used
• 32.768 kHz crystal oscillator generating 1 Hz clock
for Real Time Clock
• Individually controlled clocks for peripherals and CPU
• Programmable clock prescalers for UARTs and PWMs
• Five global power control modes are available:
– Active
– Standby
– Sleep
– Stop1
– Stop2
Real Time Clock
The RTC provides an alarm or long time base
counter. An interrupt is generated following counting a
programmed number of one-second periods. The 1 Hz
RTC clock is internally derived. The RTC features:
• 32-bit up counter with programmable load
• Programmable 32-bit match compare register
• Software maskable interrupt when counter and compare registers are identical.
RTC input clock sources:
• PLL clock
• 32.768 kHz clock
• 1 Hz clock (default).
• CPU/Bus clock frequency can be changed on the fly
• Selectable clock output
• Hardware reset (nRESETIN) and software reset.
22
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Watchdog Timer
General Purpose Input/Output (GPIO)
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer to be
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The features of the Watchdog Timer are:
The LH79524 provides up to 108 bits of programmable input/output, and the LH79525 provides 86 bits.
Many of the GPIO pins are multiplexed with other signals. All GPIO feature:
• Driven by the bus clock
• 16 programmable time-out periods: 216 through 231
clock cycles
• Generates a reset or an FIQ Interrupt whenever a
time-out period is reached
• Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes
• Individually programmable input/output pins
• All default to Input on power-up.
• LH79524
– Ports A-I, K, L, and N: Bidirectional I/O (Port N is
4 bits wide)
– Port J: Input only
– Port M: Output only
• LH79525
– Ports A-I: Bidirectional I/O
– Port J: Input only
– Port M: Output only (6 bits wide)
• Protection mechanism guards against interrupt-service failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a system reset.
Boot Controller
Timers
• Supports booting from 8-, 16-, or 32-bit devices,
selectable via external pins at power-on reset
The boot controller allows selection of the hardware
device to be used for booting.
The LH79524 and LH79525 incorporate three 16-bit
independently programmable Timer modules. The timers are clocked by the system clock, but have an internal scaled-down system clock that is used for the Pulse
Width Modulator (PWM) and compare functions.
• Configures the byte lane boot state for nCS1,
selectable via external pins at power-on reset.
All counters are incremented by an internal prescaled counter clock or external clock and can generate an overflow interrupt. All three timers have separate
internal prescaled counter clocks, with either a common external clock or a prescaled version of the system clock.
• Glueless interface to external NAND flash.
• Timer 0 has five Capture Registers and two Compare Registers.
• Timer 1 and Timer 2 have two Capture and two Compare Registers each.
The Capture Registers have edge-selectable inputs
and can generate an interrupt. The Compare Registers
can force the compare output pin either HIGH or LOW
upon a match.
The timers support a PWM Mode that uses the two
Timer Compare Registers associated with a timer to
create a PWM. Each timer can generate a separate
interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt condition
occurs. The interrupt remains active until all compare,
capture, and overflow interrupts are cleared.
Data Sheet for Rev. A.1 Silicon
• Supports booting from alternate external devices
(e.g., NAND flash) via external pins on power-on reset
USB Device
The USB Device integrated into the LH79524/
LH79525 is compliant with the USB 1.1 and 2.0 specification, and compatible with both the OpenHCI and
Intel UHCI standards. The USB Device:
• Supports Full-Speed (12 Mbit/s) operation, and
suspend and resume signaling
• Four Endpoints
• Bulk/Interrupt or Isochronous Transfers
• FIFO for each Endpoint direction (except EP0 which
shares a FIFO between IN/OUT). FIFOs exist in
2464 × 8 RAM
• Supports DMA accesses to FIFO.
Version 1.0
23
LH79524/LH79525
System-on-Chip
Ethernet MAC Controller
SSP To I2S Converter
The on-board Ethernet MAC Controller (EMAC) is
compatible with IEEE 802.3, and has passed the University of New Hampshire (UNH) testing. It supports
both 10- and 100-Mbit/s, and full and half duplex operation. Other features include:
The SSP to I2S converter is an interface that converts a synchronous serial communication stream in TI
DSP-compatible mode into an I2S compliant synchronous serial stream. The I 2 S converter operates on
serial data in both master and slave mode.
The I2S converter provides:
• Statistics counter registers for RMON/MIB
• MII interface to the physical layer
• Programmable Word Select (WS) delay
• Interrupt generation to signal receive and transmit
completion
• Left/right channel information:
– Current WS value at the pin
– WS value associated with next entry written to
TX FIFO
– WS value associated with next entry read from
RX FIFO
• Transmit and receive FIFOs
• Automatic pad and CRC generation on transmitted
frames
• Automatic discard of frames received with errors
• Address checking logic supports up to four specific
(hardware) 48-bit addresses
• Supports promiscuous mode where
received frames are copied to memory
all
valid
• Hash matching of unicast and multicast destination
addresses
• Supports physical layer management through MDIO
interface
• Supports serial network interface operation
• Support for:
– Half duplex flow control by forcing collisions on incoming frames
– Full duplex flow control with recognition of incoming pause frames and hardware generation of
transmitted pause frames
– 802.Q VLAN tagging with recognition of incoming
VLAN and priority tagged frames
• Ability to invert WS state
• Ability to invert the bit clock
• Supports frame size of 16 bits only. Any other frame
size will result in a frame size error. Each frame
transmits starting with the most-significant bit.
• Master and slave modes supported
• As with the SSP, a single combined interrupt is generated as an OR function of the individual interrupt
requests. This interrupt replaces the SSP interrupt,
which is used solely as an input to the I2S converter.
• Additional interrupts:
– Transmit FIFO underrun
– Transmit frame size error
– Receive frame size error
• A set of Interrupt registers contain all the information
in the SSPIMSC, SSPRIS, and SSPMIS registers,
plus the transmit underrun error and frame size errors
• Additional status bits:
– Transmit FIFO Full
– Receive FIFO Empty
• Multiple buffers per receive and transmit frame
• Software configures the MAC address
• Jumbo frames of up to 10,240 bytes supported.
• Passes SSP data unaltered when module is not
enabled
I2C Controller
The I2C Controller includes a two-wire I2C serial
interface capable of operating in either Master or Slave
mode. The block conforms to the I2C 2.1 Bus Specification for data rates up to 400 kbit/s. The two wires are
SCL (serial clock) and SDA (serial data). The I2C module provides the following features:
• Loopback Test Mode support.
• Two-wire synchronous serial interface
• Operates in both the standard mode, for data rates
up to 100 kbit/s, and the fast mode, with data rates
up to 400 kbit/s
• Communicates with devices in the fast mode as well
as the standard mode if both are attached to the bus.
24
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
ADC and Brownout Detector
The ADC block consists of an 10-channel, 10-bit
Analog-to-Digital Converter with integrated Touch
Screen Controller (TSC). The complete touch screen
interface is achieved by combining the front-end biasing, control circuitry with analog-to-digital conversion,
reference generation, and digital control.
The ADC has a bias-and-control network that allows
correct operation with both 4- and 5-wire touch panels.
A 16-entry × 16-bit wide FIFO holds a 10-bit ADC
output and a 4-bit tag number.
When the screen is touched, it pushes the conductive coating on the coversheet against the coating
on the glass, making electrical contact. The voltages
produced are the analog representation of the position
touched. The voltage level of the coversheet is
converted continuously by the ADC and monitored by
the system.
Other features include:
• 10-bit fully differential Successive Approximation
Register (SAR) with integrated sample/hold
• A 10-channel multiplexer that routes user-selected
inputs to the ADC in single-ended and differential
modes
• A 16-entry × 16-bit wide FIFO that holds the 10-bit
ADC output
• Front bias-and-control network for touch screen
interface and support functions, which are compatible with industry-standard 4- and 5-wire touch-sensitive panels
• Touch-pressure sensing circuits
• Pen-down sensing circuit and interrupt generator
• Independent voltage reference generator
• Conversion automation function to minimize
interrupt overhead
• Brownout Detector
• Battery Control Signal.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
DC Core Supply Voltage
VDDC
-0.3 to 2.4
V
DC I/O Supply Voltage
DC Analog Supply
Voltage for ADC
Storage Temperature
VDD
-0.3 to 4.6
V
VDDA0
-0.3 to 4.6
V
VDDA1
-0.3 to 2.4
V
VDDA2
-0.3 to 2.4
V
TSTG
-55 to +125
°C
NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may
affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
PARAMETER
MINIMUM
TYPICAL
MAXIMUM
NOTES
DC Core Supply Voltage (VDDC)
1.7 V
1.8 V
1.9 V
1, 4
DC I/O Supply Voltage (VDD)
3.0 V
3.3 V
3.6 V
4
DC Analog Supply Voltage (VDDA0)
3.0 V
3.3 V
3.6 V
DC Analog Supply Voltage (VDDA1)
1.7 V
1.8 V
1.9 V
DC Analog Supply Voltage (VDDA2)
1.7 V
1.8 V
1.9 V
Clock Frequency
3.27 MHz
Crystal Frequency
10.0 MHz
-40°C
Operating Temperature (Industrial)
76.205 MHz
2
11.2896 MHz
20.0 MHz
3
25°C
+85°C
NOTES:
1. Linear Regulator disabled.
2. With PLL enabled. Without PLL, minimum frequency is 0 MHz.
Some peripherals may not operate at minimum frequency.
3. Choose 11.2896 MHz to ensure proper operation of the I2S, USB,
and UART peripherals.
4. Core Voltage should never exceed I/O Voltage after initial power
up. See “Power Supply Sequencing” on page 26.
Data Sheet for Rev. A.1 Silicon
Version 1.0
25
LH79524/LH79525
System-on-Chip
Power Supply Sequencing
DC/AC Specifications
When the linear regulator is not enabled, SHARP
recommends that the 1.8 V power supply be energized
before the 3.3 V supply. If this is not possible, the 1.8 V
supply may not lag the 3.3 V supply by more than 100
μs. If longer delay time is needed, it is recommended
that the voltage difference between the two power supplies be within 1.5 V during power supply ramp up. To
avoid a potential latchup condition, voltage should be
applied to input pins only after the device is poweredon as described above.
Unless noted, all data provided are based on:
• -40°C to +85°C (Industrial temperature range)
• VDDC = 1.7 V to 1.9 V
• VDD = 3.0 V to 3.6 V, VDDA = 1.7 V to 1.9 V.
DC SPECIFICATIONS
SYMBOL
VIH
VIL
VIT+
VITVHYST
VOH1
VOL1
PARAMETER
MIN.
CMOS input HIGH voltage
CMOS input LOW voltage
Positive Input threshold voltage (Schmitt pins)
Negative Input threshold voltage (Schmitt pins)
Schmitt trigger hysteresis
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
2.0
TYP.
MAX. UNIT
5.5
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
2.0
0.8
0.35
2.6
2.6
2.6
2.6
0.4
0.4
0.4
2.6
RIN
Input leakage pull-up/pull-down resistors
40
kΩ
IACTIVE
ISTANDBY
ISLEEP
ISTOP1
ISTOP2
ISTOP2
ISTOP2
ISTOP2
Active current
Standby current
Sleep current
Stop1 current
Stop2 current
Stop2 current
Stop2 current
Stop2 current
85
50
3.8
420
115
95
45
25
mA
mA
mA
μA
μA
μA
μA
μA
CONDITIONS
CEN = 1
CEN = 1
CSEN = 1
CSEN = 1
CSEN = 1
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
IOH = -12 mA
IOL = 2 mA
IOL = 4 mA
IOL = 7 mA
IOH = 12 mA
VIN = VDD or GND (Calculate input
leakage current at desired VDD)
Note 2
Notes 2, 3
RTC ON, Linear Regulator ON
RTC OFF, Linear Regulator ON
RTC ON, Linear Regulator OFF
RTC OFF, Linear Regulator OFF
NOTES:
1. Table 2 details each pin’s buffer type.
2. Running Typical Application over operating range.
3. Current measured with CPU stopped and all peripherals enabled
Linear Regulator DC Characteristics.
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
IQUIESCENT Quiescent Current
ISLEEPLR
Current with Linear Regulator disabled
IOLR
Output Current Range
VOLR
Output Voltage, Linear Regulator
26
μA
75
μA
8
0.0
200
1.84
Version 1.0
mA
V
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
AC Test Conditions
AC Specifications
PARAMETER
RATING
UNIT
Supply Voltage (VDD)
3.0 to 3.6
V
Core Voltage (VDDC)
1.7 to 1.9
V
Input Pulse Levels
VSS to VDD
V
2
ns
VDD/2
V
Input Rise and Fall Times
Input and Output Timing
Reference Levels
Power Consumption By Peripheral Device
Table 12 shows the typical power consumption by
individual peripheral device.
All signals described in Table 13 relate to transitions
after a reference clock signal. The illustration in Figure
7 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
The reference clock signals in this design are:
• HCLK, the System Bus clock
• PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79524/LH79525)
• SSPCLK, the Synchronous Serial Interface clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
LCD Controller
Table 12. Peripheral Current Consumption
PERIPHERAL
TYPICAL
UNITS
ADC/TSC
590
μA
Counter/Timers
203
μA
DMA
4.2
mA
Ethernet Controller
670
μA
I2S
200
μA
LCD Controller
2.2
mA
RTC
5.1
μA
SSP
508
μA
UARTs
203
μA
USB Device (+PLL)
5.6 (+3.3)
mA
• and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal. See
Figure 7.
For outputs from the LH79524/LH79525, tOVXXX
(e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX
are shown in Table 13.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 13.
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 13.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
rising edge of the reference clock signal. Minimum
requirements are shown in Table 13.
REFERENCE
CLOCK
tOHXXX
tOVXXX
OUTPUT
SIGNAL (O)
tISXXX tIHXXX
INPUT
SIGNAL (I)
LH79525-28
Figure 7. LH79524/LH79525 Signal Timing
Data Sheet for Rev. A.1 Silicon
Version 1.0
27
LH79524/LH79525
System-on-Chip
Table 13. AC Signal Characteristics
SIGNAL
TYPE LOAD
SYMBOL
MIN.
MAX.
DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
A[27:0]
D[31:0]
Output 50 pF
Input
Output 50 pF
tWC
3 × tHCLK – 5.0 ns
Write Cycle time
tRC
2 × tHCLK – 5.0 ns
Read Cycle time
tDHWE
tHCLK – 5.5 ns
Data out hold to nWE release
tDWE
tHCLK – 4.5 ns
Data out valid to nWE release
tDSCS
14.0 ns
Data valid to nCSx release
tDSOE
12.5 ns
Data valid to nOE release
tDSB
12.0 ns
Data valid to nBLEx release
tDHCS
0.0 ns
nCSx release to data invalid
tDHOE
0.0 ns
tAV
nCS[3:0]
Output 50 pF
tAHCS
tHCLK – 3.0 ns
tAHOE
tHCLK - 1.0 ns
nOE
Output 50 pF
Output 50 pF
Address hold after nOE release
Address valid to nCSx valid
tCW
2 × tHCLK + 3.0 ns
nCSx valid to nWE release
2 × tHCLK
nCSx valid to nBLE release
tHCLK – 3.5 ns
tBV
nWE
Address hold after nCSx release
2.5 ns
tCS
Output 50 pF
nCSx valid to Address valid
tASCS
tCB
nBLE
nOE release to data invalid
2.5 ns
nCSx width
1.5 ns
nCSx valid to nBLE valid
tAHB
tHCLK – 2.0 ns
Address hold after nBLE release
tDB
tHCLK – 6.0 ns
Data out valid to nBLE release
tDHBR
0.0 ns
tDHBW
tHCLK + 9 ns
Data out hold to nBLE release
tBR
–2.0 ns
Address hold to nBLE release
Data in hold to nBLE release
tAB
2 × tHCLK ns
tASB
1.0 ns
tBLE
tHCLK – 4.5 ns
tBP
tHCLK – 4.5 ns
Address valid to nBLE release
Address valid to nBLE valid
nBLE width (read)
nBLE width (write)
tASWE
tHCLK + 1.5 ns
Address valid to nWE valid
tAW
2 × tHCLK + 0.5 ns
Address valid to nWE release
tWR
tHCLK – 3.0 ns
tWP
tHCLK – 1 ns
Write Enable width
tOE
tHCLK – 1 ns
Ouput Enable width
tOEV
Address Hold to nWE release
– 0.5 ns
nOE valid after nCSx valid
SYNCHRONOUS MEMORY INTERFACE SIGNALS
A[23:0]
Ouput 50 pF
Output 50 pF
D[31:0]
Input
nCAS
Output 50 pF
nRAS
Output 50 pF
28
tOVA
tOVD
tSDCLK/2 + 4.5 ns
Address Valid
tSDCLK/2 + 7.0 ns
Output Data Valid
tOHD
tSDCLK/2 – 4.0 ns
Output Data Hold
tISD
5.0 ns
Input Data Setup
tIHD
1.5 ns
tOVCA
tOHCA
tSDCLK/2 – 4.0 ns
tOVRA
tOHRA
Input Data Hold
tSDCLK/2 + 4.0 ns
CAS Hold
tSDCLK/2 + 4.5 ns
tSDCLK/2 – 4.0 ns
Version 1.0
CAS Valid
RAS Valid
RAS Hold
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Table 13. AC Signal Characteristics (Cont’d)
SIGNAL
TYPE LOAD
nWE
Output 30 pF
SDCKE
Output 30 pF
DQM[3:0]
Output 30 pF
nSDCS[1:0]
Output 30 pF
SDCLK
Output 30 pF
SYMBOL
MIN.
tOVSDW
tOHSDW
tSDCLK/2 – 4.0 ns
tOVC0
tOHC0
tSDCLK/2 + 4.5 ns
SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
tSDCLK/2 + 5.0 ns
DQM Data Mask Valid
tSDCLK/2 + 4.5 ns
SDCS Data Mask Valid
tSDCLK/2 – 4.0 ns
tOVSC
DESCRIPTION
SDWE Write Enable Valid
SDWE Write Enable Hold
tSDCLK/2 – 4.0 ns
tOVDQ
tOHDQ
MAX.
tSDCLK/2 + 4.5 ns
DQM Data Mask Hold
tOHSC
tSDCLK/2 – 4.0 ns
SDCS Data Mask Hold
tSDCLK
19.37 ns
SDRAM Clock Period
SYNCHRONOUS SERIAL PORT (SSP)
SSPFRM
Output 50 pF tOVSSPFRM
14 ns
tOVSSPFRM Output Valid,
Referenced to SSPCLK
SSPTX
Output 50 pF
14 ns
SSP Transmit Valid
SSPRX
Input
tOVSSPTX
tISSPRX
20 ns
SSP Receive Setup
ETHERNET MAC CONTROLLER (EMC)
tOVTXER
ETHERTXER
Output 50 pF
tOHTXER
25 ns
ETHERTXCLK/2 +
2.0 ns
tOVTXD
ETHERTX[3:0] Output 50 pF
tOHTXD
ETHERTXEN
ETHERRXDV
ETHERRX[3:0]
Output 50 pF
Transmit Data Hold after
ETHERTXCLK
25 ns
ETHERTXCLK/2 +
2.0 ns
tOVTXEN
Transmit Data Valid after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
25 ns
Transmit Data Valid after
ETHERTXCLK
tOHTXEN
ETHERTXCLK/2 +
2.0 ns
tISRXDV
10 ns
Receive Data Setup prior to
ETHERRXCLK
tIHRXDV
10 ns
Receive Data Hold prior to
ETHERRXCLK
tISRXD
10 ns
Receive Data Setup prior to
ETHERRXCLK
tIHRXD
10 ns
Receive Data Hold prior to
ETHERRXCLK
Input
Input
Data Sheet for Rev. A.1 Silicon
Version 1.0
Transmit Data Hold after
ETHERTXCLK
29
LH79524/LH79525
System-on-Chip
Analog-To-Digital Converter
Electrical Characteristics
Table 14 shows the ADC electrical characteristics.
See Figure 8 for the ADC transfer characteristics.
Table 14. ADC Electrical Characteristics
PARAMETER
MIN.
A/D Resolution
10
Throughput Conversion
17
Acquisition Time
TYP.
MAX.
UNITS
10
Bits
CLK Cycles
3
NOTES
1
CLK Cycles
Data Format
binary
CLK Frequency
500
5,000
ns
Differential Non-Linearity
-0.99
3.0
LSB
Integral Non-Linearity
-3.0
+3.0
LSB
Offset Error
-10
+10
mV
Gain Error
-2.0
+2.0
LSB
Reference Voltage Output
1.85
2.0
2.15
V
VREF-
VSSA
VSSA
(VREF+) -1.0 V
V
2
VREF+
(VREF-) +1.0 V
VREF
VDDA
V
2
Crosstalk between channels
Analog Input Voltage Range
-60
VDDA
V
Analog Input Current
5
μA
Reference Input Current
5
μA
Analog input capacitance
15
pF
3.6
V
590
1000
μA
1
10
μA
180
300
μA
2.63
2.9
V
Operating Supply Voltage
0
dB
3.0
Operating Current, VDDA0
Powerdown Current, VDDA0
Standby Current
Brown Out Trip Point (falling point)
2.36
Brown Out Hysterisis
Operating Temperature
120
-40
3
4
mV
85
°C
NOTES:
1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion plus 1 × A2DCLK cycles to be made available in the PCLK
domain. An additional 3 × PCLK cycles are required before being available on the APB.
2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance
(RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. However, the on-chip
reference cannot drive the ADC unless the reference buffer is switched on.
3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+
or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above
or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible
damage to the ADC.
4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
30
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
OFFSET GAIN
ERROR ERROR
1024
1023
1022
1021
1020
1019
1018
IDEAL
TRANSFER CURVE
9
8
CENTER OF A
STEP OF THE ACTUAL
TRANSFER CURVE
7
ACTUAL
TRANSFER CURVE
6
5
INTEGRAL
NON-LINEARITY
4
3
2
CENTER OF STEP
1
1
OFFSET
ERROR
2
3
4
5
6
7
8
9
1,015 1,016 1,017 1,018 1,019 1,020 1,021 1,022 1,023 1,024
LSB
DNL
LH79525-2
Figure 8. ADC Transfer Characteristics
Data Sheet for Rev. A.1 Silicon
Version 1.0
31
LH79524/LH79525
System-on-Chip
External Memory Controller Waveforms
The External Memory Controller (EMC) handles
transactions with both static and dynamic memory.
STATIC MEMORY WAVEFORMS
This section illustrates static memory transaction
waveforms. Each wait state is one HCLK period.
nWAIT Input
The EMC’s Static Memory Controller supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the beginning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 9 through Figure 18.
Read and Write Waveforms
Figure 15 shows the Read cycle with zero wait
states. As shown in the figure, SWAITOENx and
SWAITRDx are programmed to 0 for minimum Read
cycle time.
The zero programmed into the SWAITRDx indicates
that the read occurs with zero wait states, on the first
rising edge following Address Valid. After a small propagation delay, nOE is deasserted (as is nCSx), latching
the data into the SoC. The address line is held valid
one more HCLK period (‘C’ in the figure). Thus, the
minimum Read cycle is two HCLK periods.
In Figure 16, nCSx is asserted coincident (following
a small propagation delay) with Valid Address. Data
becomes valid another small propagation delay later.
Unlike Read transactions, nWE (or nBLEx) assertion is
always delayed one HCLK cycle. The nBLEx signal has
the same timing as nWE for write to 8-bit devices that
use the byte lane enables instead of the write enables.
The nWE (or nBLEx) signal remains asserted for one
HCLK cycle when the nWE (or nBLEx) signal is deasserted and the data is latched into the external memory
device. Valid address is held for one additional cycle
before deassertion (‘C’ in the figure), as is the Chip
Select. The minimum Write cycle is three HCLK periods.
Read wait state programming uses the SWAITRDx
register. Figure 17 shows the results of programming
SWAITRDx to 0x3, setting the EMC for three wait
states. The deassertion of nOE is delayed from the first
rising HCLK edge following Valid Address, as in Figure
15, to the fourth rising edge, a delay of 3 HCLK periods.
Figure 18 shows the results of programming the
SWAITWRx and SWAITWENx registers for two Write
wait states: register SWAITWENx = 0x0, and SWAITWRx = 0x2. Assertion of nCSx precedes nWE (nBLEx)
by one HCLK period. Then, instead of the nWE
(nBLEx) signal deasserting one HCLK period after
assertion, it is delayed two wait states and the signal
deasserts on the rising edge following two wait states.
Chapter 7 of the User’s Guide has detailed register
descriptions and additional programming examples.
Figure 16 shows the minimum write cycle time with
both SWAITWRx and SWAITWENx programmed to
zero. The write access time is determined by the number
of wait states programmed in the SWAITWRx register.
32
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
tDD_nWAIT_nCS(x)
tDA_nCS(x)_nWAIT
tDD_nWAIT_nOE
nCS(x)
nOE
tA_nWAIT
nWAIT
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
HCLK
Transaction
Sequence
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
WST-0
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-133
Figure 9. nWAIT Read Sequence (SWAITRDx = 3)
Table 15. nWAIT Read Sequence Parameter Definitions
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT 1
0
16,365
HCLK periods
tDA_nCS(x)_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
tDD_nWAIT_nCS(x)
Delay from nWAIT deassertion to nCS(x) deassertion
4
HCLK periods
tDD_nWAIT_nOE
Delay from nWAIT deassertion to nOE deassertion
4
HCLK periods
tA_nWAIT
Assertion time of nWAIT
2
HCLK periods
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O condtioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Read Wait States register (SWAITRDx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another read wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Output Enable Delay register (SWAITOENx) is programmed to 0.
Data Sheet for Rev. A.1 Silicon
Version 1.0
33
LH79524/LH79525
System-on-Chip
tDD_nWAIT_nCS(x)
tDA_nCS(x)_nWAIT
tDD_nWAIT_nOE)
nCS(x)
nOE
tA_nWAIT
nWAIT
SI
SI
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
HCLK
Transaction
Sequence
WST-5
DELAY
WST-4
DELAY
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
SQ-0
nWAIT
DELAY
WST-0
DELAY
LH79525-134
Figure 10. nWAIT Read Sequence (SWAITRDx = 5)
tDA_nCS(x)_nWAIT
nCS(x)
nOE
tA_nWAIT
nWAIT
SI
SI
HCLK
Transaction
Sequence
WST-5
DELAY
WST-4
DELAY
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
WST-0
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-135
Figure 11. nWAIT Read Sequence (SWAITRDx = 5): nWAIT has no effect on the current transaction
34
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
tDD_nWAIT_nCS(x)
tDA_nCS(x)_nWAIT
tDD_nWAIT_nWE
nCS(x)
nWE
tA_nWAIT
nWAIT
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
HCLK
Transaction
Sequence
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
WST-0
DELAY
END
END
CYCLE CYCLE
nWE
nCS(x)
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-136
Figure 12. nWAIT Write Sequence (SWAITWRx = 3)
Table 16. nWAIT Write Sequence Parameter Definitions
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT1
0
16,365
HCLK periods
tIDA_nCS(x)_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
tDD_nWAIT_nCS(x)
Delay from nWAIT deassertion to nCS(x) deassertion
6
HCLK periods
tDD_nWAIT_nWE
Delay from nWAIT deassertion to nWE deassertion
5
HCLK periods
tA_nWAIT
Assertion time of nWAIT
2
HCLK periods
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O condtioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Write Wait States register (SWAITWRx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another write wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Write Enable Delay register (SWAITWENx) is programmed to 0.
Data Sheet for Rev. A.1 Silicon
Version 1.0
35
LH79524/LH79525
System-on-Chip
tDD_nWAIT_nCS(x)
tDA_nCS(x)_nWAIT
tDD_nWAIT_nWE
nCS(x)
nWE
tA_nWAIT
nWAIT
SI
SI
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
HCLK
Transaction
Sequence
WST-5
DELAY
WST-4
DELAY
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
WST-0
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
END
CYCLE
nWE
END
CYCLE
nCS(x)
LH79525-137
Figure 13. nWAIT Write Sequence (SWAITWRx = 5)
tDA_nCS(x)_nWAIT
nCS(x)
nWE
tA_nWAIT
nWAIT
SI
SI
HCLK
Transaction
Sequence
WST-5
DELAY
WST-4
DELAY
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
WST-0
DELAY
END
CYCLE
nWE
END
CYCLE
nCS(x)
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-138
Figure 14. nWAIT Write Sequence (SWAITWRx = 5): nWAIT has no effect on the current transaction
36
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
tRC
tDSB
tDSCS,
tDSOE
tASCS
tAHCS, tAHOE
tAHB
HCLK
A[23:0]
VALID ADDRESS
D[31:0]
VALID DATA
tCS
nCS
tOEV
tOE
tDHCS
nOE
tDHBR
tBV
tDHOE
nBLEx
tBLE
DATA
CAPTURED
LH79525-105
Figure 15. External Static Memory Read, Zero Wait States
Data Sheet for Rev. A.1 Silicon
Version 1.0
37
LH79524/LH79525
System-on-Chip
tWC
HCLK
A[23: 0]
VALID ADDRESS
tASCS
tAW, tAB
D[ 31:0 ]
VALID DATA
tCW
tCB
nCS
tDHWE, tWR
tDWE
tDB
nWE
tASB
tBR
tWP
tASWE
tBP
nBLEx
LH79525-71
Figure 16. External Static Memory Write, Zero Wait States
HCLK
tRC
A[23:0]
D[31:0]
VALID ADDRESS
VALID DATA
nCSx
DATA
CAPTURED
nOE
LH79525-72
Figure 17. External Static Memory Read with Three Wait States
38
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
HCLK
tWC
A[23:0]
VALID ADDRESS
D[31:0]
VALID DATA
nCSx
nWE or nBLEx
LH79525-73
Figure 18. External Static Memory Write with Two Wait States
Data Sheet for Rev. A.1 Silicon
Version 1.0
39
LH79524/LH79525
System-on-Chip
SDRAM MEMORY CONTROLLER WAVEFORMS
Figure 19 shows the waveform and timing for an
SDRAM Burst Read (page already open). Figure 20
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
tSDCLK
SCLK
tOVXXX tOHXXX
SDRAMcmd
READ
NOP
NOP
NOP
READ
NOP
NOP
tOHDQ
tOVDQ
DQMx
tOVA
A[14:0]
BANK,
COLUMN
tISD tIHD
D[31:0]
CAS
LATENCY = 2
DATA n
DATA n + 2
DATA n + 1
DATA n + 3
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. SDCKE is HIGH.
LH79525-3
Figure 19. SDRAM Burst Read
40
Version 1.0
Data Sheet for Rev. A.1 Silicon
Data Sheet for Rev. A.1 Silicon
Version 1.0
tOVC0
tOHXXX
tOVA
BANK,
ROW
tOVA
ACTIVE
tOVXXX
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
D[31:0]
A[14:0]
SDRAMcmd
SDCKE
SCLK
tSDCLK
tOVD
tOHD
DATA
BANK,
COLUMN
WRITE
tOHC0
LH79525-24
System-on-Chip
LH79524/LH79525
Figure 20. SDRAM Bank Activate and Write
41
LH79524/LH79525
System-on-Chip
External DMA Handshake Signal Timing
DACK/DEOT TIMING
These timing diagrams indicate when nDACK and
DEOT occur in relation to an external bus access to/from
the external peripheral that requested the DMA transfer.
DREQ TIMING
Once asserted, DREQ must not transition from LOW
to HIGH again until after nDACK has been asserted.
The first diagram shows the timing with relation to a
single read or the last word of a burst read from the
requesting peripheral. The remaining diagrams show
timing for data transfers.
DREQ MAY
TRANSITON
DREQ
MUST NOT
TRANSITON
tDREQ0L,
tDREQ1L
DREQ0,
DREQ1
DACK0
nDACK1
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
LH79525-5
Figure 21. DREQ Timing Restrictions
HCLK
(See Note)
A[23:0]
ADDRESS
D[31:0]
DATA
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/
DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal provided for reference only.
LH79525-6
Figure 22. Read, from Peripheral to Memory, Burst Size = 1
42
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
HCLK
(See Note)
A[23:0]
ADDRESS
D[15:0]
DATA
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/
DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal provided for reference only.
LH79525-7
Figure 23. Write, from Memory to Peripheral, Burst Size = 1
HCLK*
A[23:0]
ADDRESS
D[31:0]
DATA #1
DATA #2
DATA #3
DATA #4
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal, provided for reference only.
LH79525-8
Figure 24. Read, Peripheral to Memory: Peripheral Burst Size = 4
Data Sheet for Rev. A.1 Silicon
Version 1.0
43
44
Version 1.0
ADDRESS
LS DATA #1
ADDRESS + 2
LS DATA #4 MS DATA #4
ADDRESS
MS DATA #3
ADDRESS + 2
LS DATA #3
ADDRESS
MS DATA #2
ADDRESS + 2
LS DATA #2
ADDRESS
MS DATA #1
ADDRESS + 2
NOTE: * HCLK is an internal signal, provided for reference only.
nDACK1
DACK0/
DEOT0/
DEOT1
nOE
nBLE[1:0]
nWEN
nCSx
D[31:0]
A[23:0]
HCLK*
LH79525-9
LH79524/LH79525
System-on-Chip
Figure 25. Write, Memory-to-Peripheral: Burst Size = 4; Destination Width > External Access Width
Data Sheet for Rev. A.1 Silicon
Data Sheet for Rev. A.1 Silicon
Version 1.0
TIMING1: VSW = 1
TIMING1: LPP
SEE 'STN HORIZONTAL TIMING DIAGRAM'
ALL 'LINES' FOR ONE FRAME
NOTES:
1. Signal polarties may vary for some displays.
2. See 'STN horizontal timing' diagram.
3. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
PIXEL DATA AND
HORIZONTAL
CONTROL
SIGNALS FOR
ONE FRAME
LCDFP
(VERTICAL
SYNCHRONIZATION
PULSE)
TIMING1: IVS
(See Note 3)
DATA ENABLE
LCDEN
(DATA ENABLE)
TIMING2:ACB
TIMING2: IOE
PANEL LOGIC ACTIVE
PANEL DATA CLOCK ACTIVE
LCDVDDEN
(DIGITAL SUPPLY
ENABLE FOR
HIGH-VOLTAGE
SUPPLIES)
PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE
VSS
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2: BCD
TIMING2: IPC
TIMING2: CPL
See
Note 2
PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE
1 STN FRAME
VDD
DISPLAY-DEPENDENT
TURN-ON DELAY
ENUMERATED IN
HORIZONTAL 'LINES'
FRONT PORCH
TIMING1: VFP
LH79525-44
DISPLAY
DEPENDENT
TURN-OFF DELAY
System-on-Chip
LH79524/LH79525
Color LCD Controller Timing Diagrams
Figure 26. STN Horizontal Timing
45
46
Version 1.0
TIMING1: VSW = 1
TIMING1: LPP
SEE 'STN HORIZONTAL TIMING DIAGRAM'
ALL 'LINES' FOR ONE FRAME
NOTES:
1. Signal polarties may vary for some displays.
2. See 'STN horizontal timing' diagram.
3. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
PIXEL DATA AND
HORIZONTAL
CONTROL
SIGNALS FOR
ONE FRAME
LCDFP
(VERTICAL
SYNCHRONIZATION
PULSE)
TIMING1: IVS
(See Note 3)
DATA ENABLE
LCDEN
(DATA ENABLE)
TIMING2:ACB
TIMING2: IOE
PANEL LOGIC ACTIVE
PANEL DATA CLOCK ACTIVE
LCDVDDEN
(DIGITAL SUPPLY
ENABLE FOR
HIGH-VOLTAGE
SUPPLIES)
PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE
VSS
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2: BCD
TIMING2: IPC
TIMING2: CPL
See
Note 2
PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE
1 STN FRAME
VDD
DISPLAY-DEPENDENT
TURN-ON DELAY
ENUMERATED IN
HORIZONTAL 'LINES'
FRONT PORCH
TIMING1: VFP
LH79525-44
DISPLAY
DEPENDENT
TURN-OFF DELAY
LH79524/LH79525
System-on-Chip
Figure 27. STN Vertical Timing
Data Sheet for Rev. A.1 Silicon
Data Sheet for Rev. A.1 Silicon
Version 1.0
TIMING1: VSW
ENUMERATED IN
HORIZONTAL 'LINES'
BACK PORCH
TIMING1: VBP
TIMING1: LPP
SEE 'TFT HORIZONTAL TIMING DIAGRAM'
ALL 'LINES' FOR ONE FRAME
DATA ENABLE
NOTES:
1. Signal polarties may vary for some displays.
2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.
PIXEL DATA AND
HORIZONTAL
CONTROL
SIGNALS FOR
ONE FRAME
LCDFP
(VERTICAL
SYNCHRONIZATION
PULSE)
TIMING1: IVS
LCDEN
(DATA ENABLE)
TIMING2:ACB
TIMING2: IOE
PANEL DATA CLOCK ACTIVE
PANEL LOGIC ACTIVE
PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE
VSS
LCDVDDEN
(DIGITAL SUPPLY
ENABLE)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2: BCD
TIMING2: IPC
See
Note 2
PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE
1 TFT FRAME
VDD
DISPLAY-DEPENDENT
TURN-ON DELAY
ENUMERATED IN
HORIZONTAL 'LINES'
FRONT PORCH
TIMING1: VFP
LH79525-40
DISPLAY
DEPENDENT
TURN-OFF DELAY
System-on-Chip
LH79524/LH79525
Figure 28. TFT Horizontal Timing
47
48
Version 1.0
TIMING1: VSW
ENUMERATED IN
HORIZONTAL 'LINES'
BACK PORCH
TIMING1: VBP
TIMING1: LPP
SEE 'TFT HORIZONTAL TIMING DIAGRAM'
ALL 'LINES' FOR ONE FRAME
DATA ENABLE
NOTES:
1. Signal polarties may vary for some displays.
2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.
PIXEL DATA AND
HORIZONTAL
CONTROL
SIGNALS FOR
ONE FRAME
LCDFP
(VERTICAL
SYNCHRONIZATION
PULSE)
TIMING1: IVS
LCDEN
(DATA ENABLE)
TIMING2:ACB
TIMING2: IOE
PANEL DATA CLOCK ACTIVE
PANEL LOGIC ACTIVE
PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE
VSS
LCDVDDEN
(DIGITAL SUPPLY
ENABLE)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2: BCD
TIMING2: IPC
See
Note 2
PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE
1 TFT FRAME
VDD
DISPLAY-DEPENDENT
TURN-ON DELAY
ENUMERATED IN
HORIZONTAL 'LINES'
FRONT PORCH
TIMING1: VFP
LH79525-40
DISPLAY
DEPENDENT
TURN-OFF DELAY
LH79524/LH79525
System-on-Chip
Figure 29. TFT Vertical Timing
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
1 AD-TFT or HR-TFT HORIZONTAL LINE
*
CLCDCLK
(INTERNAL)
APBPERIPHCLKCTRL1:LCD
CLKPRESCALE:LCDPS
(SHOWN FOR REFERENCE)
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
INPUTS TO THE
ALI FROM THE CLCDC
TIMING0:HSW
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
16 × (TIMING0:PPL+1)
001 002 003 004 005 006 007 008
320
PIXEL DATA
TIMING0:HSW +
TIMING0: HBP
LCDEN
(INTERNAL DATA ENABLE)
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
(DELAYED FOR
AD-TFT, HR-TFT)
001 002 003 004 005 006
317 318 319 320
1 LCDDCLK
OUTPUTS FROM THE
ALI TO THE PANEL
ALITIMING2:SPLDEL
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
1 LCDDCLK
ALITIMING1:LPDEL
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
ALITIMING1:PSCLS
ALITIMING2:PS2CLS2
LCDCLS
LCDPS
LCDREV
NOTE: * Source is RCPC.
LH79525-42
Figure 30. AD-TFT, HR-TFT Horizontal Timing
TIMING1:VSW
LCDSPS
(VERTICAL
SYNCHRONIZATION)
1.5 μs - 4 μs
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDVD[11:0]
(LCD VIDEO DATA)
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
LH79525-43
Figure 31. AD-TFT, HR-TFT Vertical Timing
Data Sheet for Rev. A.1 Silicon
Version 1.0
49
LH79524/LH79525
System-on-Chip
Synchronous Serial Port
SSPRX
tISSPRX
SSPTX
SSPFRM
SSPCLK
tOVSSPTX
tOVSSPFRM
LH79525-21
The SSP timing is illustrated in Figure 32.
Figure 32. Synchronous Serial Port Waveform
50
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
Ethernet MAC Controller Waveforms
The timing for the EMC is presented in the following
two illustrations. Figure 33 shows an Ethernet transmit
and Figure 34 shows an Ethernet receive.
ETHERTXCLK
tOVTXER,
tOVTXD,
tOVTXEN
tOHTXER,
tOHTXD,
tOHTXEN
ETHERTXER,
ETHERTX[3:0],
ETHERTXEN
LH79525-13
Figure 33. Ethernet Transmit Timing
ETHERRXCLK
tISRXDV,
tISRXD
tIHRXDV,
tIHRXD
ETHERRXDV,
ETHERRX[3:0]
LH79525-14
Figure 34. Ethernet Receive Timing
Data Sheet for Rev. A.1 Silicon
Version 1.0
51
LH79524/LH79525
System-on-Chip
Reset, Clock, and Power Controller
(RCPC) Waveforms
Figure 36 shows external reset timing, and Table 17
gives the timing parameters.
Figure 35 shows the method the LH79524/LH79525
uses when coming out of Reset or Power On.
Table 17. Reset AC Timing
PARAMETER
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
tOSC32
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
550
ms
tOSC14
Oscillator stabilization time after Power Up (VDDC = VDDCMIN) or
exiting STOP2
2.5
ms
tRSTIH
nRESETIN hold time after crystal stabilization
200
μS
tRSTIW
nRESETIN Pulse Width (once sampled LOW)
2
HCLK
tRSTOV
nRESETIN LOW to nRESETOUT valid
(once nRESETIN sampled LOW)
tRSTOH
nRESETOUT hold relative to nRESETIN HIGH
3.5
HCLK
1
HCLK
VDDCmin
VDDC
tOSC32
XTAL32
XTAL14
tRSTIH
tOSC14
nRESETIN
tRSTOH
nRESETOUT
LH79525-22
Figure 35. PLL Start-up
tRSTIW
nRESETIN
tRSTOH
tRSTOV
nRESETOUT
LH79525-23
Figure 36. External Reset
52
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
UNUSED INPUT SIGNAL CONDITIONING
Floating input signals can cause excessive power
consumption. Unused inputs which do not include internal pull-up or pull-down resistors should be pulled up or
down externally, to tie the signal to its inactive state.
Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
Some GPIO signals may default to inputs. If the pins
which carry these signals are unused, software can
program these signals as outputs, to eliminate the need
for pull-ups or pull-downs. Power consumption may be
higher than expected until such software executes.
Add pull-ups to all unused inputs unless an
internal pull-down resistor has been specified; see
Table 2. Consider all signals that are Inputs at Reset.
Some LH79524/LH79525 inputs have internal pullups or pull-downs. If unused, these inputs do not
require external conditioning.
SUGGESTED EXTERNAL COMPONENTS
Figure 37 shows the suggested external components for the 32.768 kHz crystal circuit to be used with
the SHARP LH79524/LH79525. The NAND gate represents the logic inside the SoC. See the table in
Figure 37 for crystal specifics.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
All output pins on the LH79524/LH79525 have fast
rise and fall times. Printed circuit trace interconnection
length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times.
This recommendation particularly applies to the
address and data buses.
Figure 38 shows the suggested external components for the 10 - 20 MHz crystal circuit to be used with
the SHARP LH79524/LH79525. The NAND gate
represents the logic inside the SoC. See the chart for
crystal specifics.
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
ENABLE
INTERNAL TO
THE LH79524/LH79525
EXTERNAL TO
THE LH79524/LH79525
XTAL32IN
Y1
XTAL32OUT
32.768 kHz
R1
10 MΩ
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 12.5 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
6. Tolerance for R1, C1, C2 is ≤ 5%.
C1
15 pF
C2
18 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER
DESCRIPTION
32.768 kHz Crystal
Tolerance
Aging
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
Parallel Mode
±30 ppm
±3 ppm
12.5 pF
50 kΩ
1.0 μW (MAX.)
MTRON SX1555 or equivalent
LH79525-11
Figure 37. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT)
Data Sheet for Rev. A.1 Silicon
Version 1.0
53
LH79524/LH79525
System-on-Chip
ENABLE
INTERNAL TO
THE LH79524/LH79525
EXTERNAL TO
THE LH79524/LH79525
XTALIN
Y1
XTALOUT
10 - 20 MHz
R1
1 MΩ
C1
18 pF
C2
22 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
6. Tolerance for R1, C1, C2 is ≤ 5%.
PARAMETER
DESCRIPTION
11.2896 MHz Crystal
Tolerance
Stability
Aging
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
(AT-Cut) Parallel Mode
±50 ppm
±100 ppm
±5 ppm
18 pF
40 Ω
100 μW (MAX.)
CITIZEN CM309S - 11.2896 MABJTR
or equivalent
LH79525-12
Figure 38. Suggested External Components, 10 - 20 MHz Oscillator
54
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
PACKAGE SPECIFICATIONS
176LQFP (JEDEC MS-026)
22.0 ±0.2
20.0 (TYP.)
0.10
1.00 REF.
1.00 REF.
22.0 ±0.2
20.0 (TYP.)
Pin 1 Marker
0.08
1.40 NOM.
DETAIL
0.40 (TYP.)
0.23
0.13
0.75
0.45
NOTES:
1. Dimensions in mm. MAX.
MIN.
2. Refer to JEDEC MS-026 for tolerances.
3. Pin 1 indicator should be used for proper package orientation
(device marking orientation may change with respect to the Pin 1 indicator).
0.15
0.05
176LQFP-JEDEC
Figure 39. LH79525: 176-pin LQFP
Data Sheet for Rev. A.1 Silicon
Version 1.0
55
LH79524/LH79525
System-on-Chip
208-BALL CABGA
0.10 (4X)
TOP VIEW
14.0
A
14.0
B
A1 BALL
PAD CORNER
0.10 C
A1 BALL
PAD CORNER
16 14 12 10 8 6 4
2
15 13 11 9 7 5
3 1
SIDE VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00
0.80
BOTTOM VIEW
(208 solder balls)
0.12 C
1.00
0.80
NOTES:
1. Dimensions in mm.
2. A1 ball indicator should be used for proper package orientation
(device marking orientation may change with respect to the A1 ball indicator).
C
5 φ0.46 TYP.
φ0.15 M C A B
φ0.08 M C
6
SEATING PLANE
0.36 ±0.04
0.70 ±0.05
1.70 MAX.
208CABGA
Figure 40. LH79524: 208-ball CABGA
56
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
21.25
0.4
22.95
17.2
19.55
0.25
1.70
17.2
NOTE: Dimensions in mm.
176LQFP-FP
Figure 41. LH79525: 176-pin LQFP PCB Footprint
208-BALL CABGA
TOP VIEW
A1 BALL
PAD CORNER
1.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
0.80
B
C
D
E
0.30
(208 PLACES)
F
G
H
J
K
L
M
N
P
R
1.00
T
0.80
NOTES:
1.00
1. Dimensions in mm.
2. Recommended PCB pad diameter: 0.30 mm.
208CABGA-FP
Figure 42. LH79524: 208-ball CABGA PCB Footprint
Data Sheet for Rev. A.1 Silicon
Version 1.0
57
LH79524/LH79525
System-on-Chip
Table 18. Record of Revisions
DATE
PAGE
NO.
1
Added text denoting that the oscillator pins are NOT 5V tolerant.
Pinout Tables
UART0 and UART1 positions reversed in Pinout Tables; UART0 functions
muxed with PB[7:6] and UART1 functions muxed with PB[5:4].
10
Notes
Added ‘The internal pullup and pulldown resistance on all digital I/O pins
is 50KΩ’ to notes 1 and 2.
16
Notes
Added ‘The internal pullup and pulldown resistance on all digital I/O pins
is 50KΩ’ to notes 1 and 2.
22
Table 11
Added ‘RTC 32 kHz Oscillator’ row to table.
26
DC Specifications
IOL corrected to 7 mA instead of 8 mA.
30
Analog-To-Digital Converter Electrical Characteristics
Corrected VREF+ and VREF– maximum/minimum values.
—
Throughout
“Commercial” temperature range references removed.
1
Features
SDRAM data bus width corrected to 15 bits.
Table 2, Table 5
SDCLK drive changed to 12 mA
10
Notes
Note 8 added (unused analog pins and XTAL32IN).
16
Notes
Note 8 added (unused analog pins and XTAL32IN).
25
Recommended Operating
Conditions
Footnote 4 added.
26
Power Supply Sequencing Section added.
26
DC Specifications
Added 12 mA-capable pins to VOH and VOL.
28
Table
Revamped Asynchronous Memory timing values for A.1 silicon.
29
Table 9
Updated Output Hold times for Ethernet Transmit signals.
28
Table 9
For Synchronous Memory, Changed tIHD to 1.5ns; all Output Hold signals
changed to: tSDCLK/2 - 4.0 ns.
30
Analog-To-Digital
Converter Electrical
Characteristics
Inserted new values for A.1 for Offset, Gain, and INL Min.
37, 38
Figure 15, Figure 16
Replaced with updated figures for A.1 silicon.
55, 56
Figure 39, Figure 40
Added note about pin/ball 1 designation.
8, 16
5/22/06
10/31/06
58
SUMMARY OF CHANGES
5 V Tolerant bullet
4, 9, 12,
15
3/6/06
PARAGRAPH OR
ILLUSTRATION
All
Throughout
Version number changed to 1.0.
33
Figure 9
Figure replaced with updated figure.
34 – 36
Figure 10 – Figure 14
nWAIT figures added.
33 & 35
Table 15 and Table 16
nWAIT parameter definition tables added.
Version 1.0
Data Sheet for Rev. A.1 Silicon
System-on-Chip
LH79524/LH79525
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
JAPAN
SHARP Microelectronics of the Americas
5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
www.sharpsma.com
SHARP Microelectronics Europe
Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
www.sharpsme.com
SHARP Corporation
Electronic Components & Devices
22-22 Nagaike-cho, Abeno-Ku
Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
www.sharp-world.com
TAIWAN
SINGAPORE
KOREA
SHARP Electronic Components
(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
SHARP Electronics (Singapore) PTE., Ltd.
438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
SHARP Electronic Components
(Korea) Corporation
RM 501 Geosung B/D, 541
Dohwa-dong, Mapo-ku
Seoul 121-701, Korea
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
CHINA
HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
©2005, 2006 by SHARP Corporation
Reference Code SMA04000