LR38574

LR38574 LR38574 DESCRIPTION The LR38574 is a CMOS timing generator IC which generates timing pulses for driving 1 090 k/ 1 310 k-pixel CCD area sensors and processing pulses. Timing Generator IC for 1 090 k/1 310 k-pixel CCDs PIN CONNECTIONS 48-PIN QFP TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 FEATURES • Designed for 1/3-type 1 090 k/1 310 k-pixel CCD area sensors • Frequency of driving horizontal CCD : 12.27 MHz • Both double speed drive monitoring mode and still mode are possible • Two still mode types : 3 fields period and 4 fields period • External shutter control function with serial data input is possible • +3 V and +4.5 V power supplies • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch OFDC 1 V1x 2 VH1Ax 3 VH1Bx 4 V2x 5 VDD3 6 GND 7 V3x 8 VH3Ax 9 VH3Bx 10 V4x 11 OFDX 12 13 14 15 16 17 18 19 20 21 22 23 24 PBLK BCPX CLPX ADCK GND FCDS FS VDD3 ACLX RS GND VCON SHTR DRMD FR TST3 VDD4 FH2 GND FH1 VDD4 CCD TST2 TST1 36 ID 35 ED2 34 ED1 33 ED0 32 HD 31 GND 30 VDD3 29 VD 28 DCLK 27 CLK 26 CKO 25 CKI (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38574 BLOCK DIAGRAM DCLK GND CKO VDD3 CLK ED2 ED1 ED0 CKI 25 OSC TST1 37 TST2 38 CCD 39 VDD4 40 1/2 FH1 41 GND 42 FH2 43 RESET VDD4 44 TST3 45 FR 46 DRMD 47 SHTR 48 LEVEL SHIFTER RESET DECODER H COUNTER 1/2 1/8 RESET 20 VDD3 19 FS 18 FCDS 17 GND 16 ADCK 15 CLPX 14 BCPX 13 PBLK GATE DATA LATCH & SHUTTER CONTROL 24 VCON 23 GND 22 RS 21 ACLX 12 OFDX HD VD 29 ID 36 35 34 33 32 31 30 28 27 26 GATE V COUNTER 1 OFDC 2 V1X 3 VH1AX 4 VH1BX 5 V2X 6 VDD3 7 GND 8 V3X 9 VH3AX 10 VH3BX 11 V4X 2 LR38574 PIN DESCRIPTION PIN NO. SYMBOL 1 2 OFDC V1X I/O O3 O3 POLARITY PIN NAME Control pulse output for OFD voltage Vertical transfer pulse output 1 Readout pulse output 1A Readout pulse output 1B Vertical transfer pulse output 2 – – Power supply Ground Vertical transfer pulse output 3 Readout pulse output 3A Readout pulse output 3B Vertical transfer pulse output 4 DESCRIPTION A pulse to control OFD voltage. A vertical transfer pulse for CCD. Connect to V1X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1BX pin of vertical driver IC. A vertical transfer pulse for CCD. Connect to V2X pin of vertical driver IC. Supply of +3.3 V power. A grounding pin. A vertical transfer pulse for CCD. Connect to V3X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3BX pin of vertical driver IC. A vertical transfer pulse for CCD. Connect to V4X pin of vertical driver IC. A pulse that sweeps the charge of the photo-diode for the electronic shutter. Connect to OFD pin of CCD through the vertical driver IC and DC offset circuit. Held at H level at normal mode. A pulse that corresponds to the cease period of the horizontal transfer pulse. A pulse to clamp the optical black signal. This pulse stays high during the absence of effective pixels within the vertical blanking or the period of sweep-out signal. A pulse to clamp the dummy outputs of CCD signal. This pulse stays high during the sweep-out period. An output pin for AD converter. The output phase of ADCK is selected by serial data step by 90˚. A grounding pin. 3 VH1AX O3 4 VH1BX O3 5 6 7 8 V2X VDD3 GND V3X O3 – – O3 9 VH3AX O3 10 VH3BX O3 11 V4X O3 12 OFDX O3 OFD pulse output 13 PBLK O3 Pre-blanking pulse output Optical black clamp pulse output 14 BCPX O3 15 16 17 CLPX ADCK GND O3 O6MA3 – – Clamp pulse output AD clock output Ground 3 LR38574 PIN NO. SYMBOL 18 19 20 21 FCDS FS VDD3 ACLX I/O O6MA3 O6MA3 – ICU3 – – POLARITY PIN NAME CDS pulse output 1 CDS pulse output 2 Power supply All clear input DESCRIPTION A pulse to clamp the feed-through level from CCD. The output phase of FCDS is selected by serial data. A pulse to sample-hold the signal from CCD. The output phase of FS is selected by serial data. Supply of +3.3 V power. An input pin for resetting all internal circuits at power on. Connect to VDD through the diode and GND through the capacitor. A pulse to sample-hold the signal. The output phase of RS is selected by serial data. A grounding pin. An input pin to control internal vertical clock for long shutter speed. H level or open 24 VCON ICU3 – VD control input L level : VD : VD is masked by the pulse which is latched at the rising edge of VD. 22 23 RS GND O6MA3 – – S/H pulse output Ground It's necessary to be set SMD = high and number of the fields data n ≥ 2 in serial data control at VCON operation. 25 26 27 CKI CKO CLK OSCI3 OSCO3 O6MA3 – – Clock input Clock output Clock output An input pin for reference clock oscillation. The frequency is 24.54545 MHz. An output pin for reference clock oscillation. The output is the inverse of CKI (pin 25). An output pin to generate HD and VD pulses. The frequency is 12.72737 MHz. An output pin for DSP IC. The frequency is 12.72727 MHz. The output phase of DCLK is selected by serial data step by 90˚. An input pin for reference of vertical pulse. Connect to VD pin of DSP IC. Supply of +3.3 V power. A grounding pin. An input pin for reference of horizontal pulse. Connect to HD pin of DSP IC. An input pin for the strobe pulse, to control the functions of LR38574. For details, see "Serial Data Control". An input pin for the clock of the shift register, to control the functions of LR38574. For details, see "Serial Data Control". 28 DCLK O6MA3 Clock output Vertical reference – – pulse input Power supply Ground Horizontal drive pulse input – Strobe pulse input Shift register clock input 29 30 31 32 33 VD VDD3 GND HD ED0 IC3 – – IC3 ICSU3 34 ED1 ICSU3 – 4 LR38574 PIN NO. SYMBOL 35 ED2 I/O ICSU3 POLARITY – PIN NAME Shift register data input Line index pulse – – output Test pin 1 Test pin 2 DESCRIPTION An input pin for the data of the shift register, to control the functions of LR38574. For details, see "Serial Data Control". The pulse is used in color separator. The signal switches between high and low at every line. A test pin. Set open or to L level in the normal mode. A test pin. Set open or to L level in the normal mode. An input pin to select CCD. It should be used with MODE input which is in the serial data. CCD L 39 CCD ICU4 – CCD selection input L H H 40 41 42 43 44 45 46 VDD4 FH1 GND FH2 VDD4 TST3 FR – O6MA43 – O6MA43 – ICD4 O6MA43 – – – – Power supply Horizontal transfer pulse output 1 Ground Horizontal transfer pulse output 2 Power supply Test pin 3 Reset pulse output Drive mode selection input Trigger output level) level with level with level with level with pull-up resistor) schmitt-trigger) pull-up resistor) pull-down resistor) 36 37 38 ID TST1 TST2 O3 ICD4 ICD4 MODE L H L H CCD LZ23H3V1 – LZ23J3V – – Supply of +4.5 V power. A horizontal transfer pulse for CCD. Connect to ØH1 pin of CCD. A grounding pin. A horizontal transfer pulse for CCD. Connect to ØH2 pin of CCD. Supply of +4.5 V power. A test pin. Set open or to L level in the normal mode. A pulse to reset the charge of output circuit. The output phase of FR is selected by serial data. An input pin to select the period of still mode. L level : 3 fields period H level or open O3 O6MA3 O6MA43 OSCI3 OSCO3 : : : : : 47 48 IC3 ICU3 ICSU3 ICU4 ICD4 DRMD SHTR : : : : : Input Input Input Input Input pin pin pin pin pin ICU3 O3 (CMOS (CMOS (CMOS (CMOS (CMOS – : 4 fields period A trigger pulse for effective signal period. Output pin (output high level is VDD3.) Output pin (output high level is VDD3.) Output pin (output high level is VDD4.) Input pin for oscillation Output pin for oscillation 5 LR38574 Serial Data Control SERIAL DATA INPUT TIMING ED0 ED1 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 ... D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 ED2 The data is shifted at the rising edge of ED1, and is latched at the rising edge of ED0. PWSA is effective at the rising edge of ED0, but others are effective at the horizontal line in which VH1AX to VH3BX are active. ED0 should be low level during data inputs of ED1 and ED2. As all internal data are set to low level by ACLX or PWSA, ED0 to ED1 should be input for desirable operations. As all internal data except PWSA are set to low level by PWSA, ED0 to ED1 should be input for desirable operations. 6 LR38574 SERIAL DATA INPUTS DATA D00-D06 D07 D08 D09 D10 D11 D12 D13 NAME SD0-SD6 SD7 SD8 SD9 SMD INMD PWSA PLCH Electronic shutter mode control Integration mode control Power save control Polarity control of FCDS, FS and RS pulses Monitoring mode selection with CCD (pin 39) – Monitoring Normal Negative Still Power save Positive L L – L FUNCTION Step of high speed shutter Number of exposed fields DATA = L – – DATA = H AT ACLX = L All L All L D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 MODE 2 lines/4 lines 2 lines/8 lines CCD = L CCD = H CCD = L CCD = H LZ23H3V1 LZ23J3V – – Uncontinuously Continuously – L L L L L L L L L L L L L L BCPCNT BCP control ML1 ML2 MR1 MR2 MR3 MC1 MC2 MC3 MS1 MS2 MS3 MF1 MF2 MF3 MA1 MA2 Phase control – – – – L L L L – ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature SYMBOL VDD3, VDD4 VI3 VI4 VO3 VO4 TOPR TSTG RATING –0.3 to +6.0 –0.3 to VDD3 + 0.3 –0.3 to VDD4 + 0.3 –0.3 to VDD3 + 0.3 –0.3 to VDD4 + 0.3 –20 to +70 –55 to +150 UNIT V V V V V ˚C ˚C 7 LR38574 ELECTRICAL CHARACTERISTICS DC Characteristics PARAMETER Input "Low" voltage Input "High" voltage Input "Low" voltage Input "High" voltage Hysteresis voltage Input "Low" voltage Input "High" voltage Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage (VDD3 = 3.0 V to VDD4, VDD4 = 4.2 to 5.5 V, TOPR = –20 to +70 ˚C) SYMBOL VIL3-1 VIH3-1 VIL3-2 VIH3-2 VT+ – VT– VIL4 VIH4 |IIL3-1| |IIH3-1| |IIL3-2| |IIH3-2| |IIL4-1| |IIH4-1| |IIL4-2| |IIH4-2| VOL3-1 VOH3-1 VOL3-2 VOH3-2 VOL3-3 VOH3-3 VOL4 VOH4 0.8VDD4 VI = 0 V VI = VDD3 VI = 0 V VI = VDD3 VI = 0 V VI = VDD4 VI = 0 V VI = VDD4 IOL = 2 mA IOH = –1 mA IOL = 3 mA IOH = –3 mA IOL = 3 mA IOH = –3 mA IOL = 10 mA IOH = –10 mA VDD3 – 0.5 0.4 VDD3 – 0.5 0.4 VDD4 – 0.5 4.0 VDD3 – 0.5 0.4 2.0 4.0 1.0 1.0 60 2.0 60 2.0 2.0 60 0.4 Schmitt-buffer 0.08VDD3 0.2VDD4 CONDITIONS MIN. 0.8VDD3 0.2VDD3 0.75VDD3 TYP. MAX. UNIT 0.2VDD3 V V V V V V V µA µA µA µA µA µA µA µA V V V V V V V V NOTE 1, 2 3 4, 5 1 2, 3 4 5 6 7 8 9 NOTES : 1. 2. 3. 4. 5. Applied Applied Applied Applied Applied to to to to to inputs (IC3, OSCI3). input (ICU3). input (ICSU3). input (ICU4). input (ICD4). 6. Applied to output (O3). 7. Applied to output (OSCO3). (Output (OSCO3) measures on condition that input (OSCI3) level is 0 V or VDD3.) 8. Applied to output (O6MA3). 9. Applied to output (O6MA43). 8 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE 48 QFP (QFP048-P-0707) (Unit : mm) 0.5TYP. 36 M 37 0.08 0.2±0.08 (1.0) 25 24 7.0±0.2 9.0±0.3 0.15±0.05 1 (1.0) 7.0±0.2 9.0±0.3 12 (1.0) (1.0) 48 13 0.65±0.2 1.45±0.2 0.1±0.1 9 Package base plane 8.0±0.2 0.1