LR38630

LR38630 LR38630 DESCRIPTION The LR38630 is a CMOS digital signal processor for color camera systems of 110 k-pixel CMOS image sensor with primary color mosaic filters. The camera system consists of CIF CMOS image sensor (LZ34C10) and DSP IC (LR38630) with 2 kbit EEPROM. Depending on application, 1 M-bit SRAM can be added in order to get slower frame rate at video output. Digital Signal Processor for CIF CMOS Image Cameras FEATURES • Designed for 110 k-pixel color CMOS image sensors with R, G, and B color mosaic filters • Compatible with CIF standard • External control interface input/output • Variable GAMMA and KNEE response • 8-bit digital input • Available for digital video 4 : 2 : 2 (U/Y/V/Y) output • Built-in synchronous signal generation circuit to drive CMOS image sensor • Built-in 2 k-bit EEPROM controller to set the camera adjustment data • Built-in auto exposure control • Built-in auto white balance control • Built-in auto carrier balance control • Built-in white blemish compensator • Lower power consumption by dual clocking signal process technology • Single +3.0 V power supply • Package : 80-pin LQFP (LQFP080-P-1212) 0.5 mm pin-pitch In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38630 PIN CONNECTIONS 80-PIN LQFP ADJMODE IFMODE EEPCK EEPDA VDD GND VS OLSTEN HREF STANDBY CTLDCK CTLDEN CTLDOUT CTLDIN VDD GND DATA0 DATA1 DATA2 DATA3 TOP VIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ACL CKI GND VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND VDD TST3 ADDSEL SCLK SDI CHD CVD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DATA4 DATA5 DATA6 DATA7 RCLK VDD GND EXMCK MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 WE OE TST2 TST1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ADD16 ADD15 ADD14 GND VDD ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 GND ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 (LQFP080-P-1212) 2 40 LR38630 BLOCK DIAGRAM OE, WE MDIO7-MDIO0 ADD16-ADD0 AD7-AD0 FPN SUPPRESSION BLACK BALANCE 1H/2H DELAY LINE SRAM CONTROL PROCESSOR SSG EXMCK OB CLAMP WHITE BALANCE GAMMA INTERPOLATION EXPOSURE CONTROL WHITE BALANCE CONTROL SDI, SCLK CMOS IMAGE SENSOR INTERFACE COLOR MATRIX COLOR SUPPRESS IMAGE FORMAT CONVERTER EXTERNAL INTERFACE DATA7-DATA0 RCLK CTLDIN, CTLDOUT CTLDEN, CTLDCK IFMODE, ADJMODE EEPDA, EEPCK CVD, CHD ACL CKI STANDBY TST1, TST2 CMOS IMAGE SENSOR SSG LUMINANCE SIGNAL PROCESS SETUP EEPROM INTERFACE HREF, OLSTEN, VS 3 LR38630 PIN DESCRIPTION PIN NO. SYMBOL 1 ACL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 CKI GND VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND VDD TST3 ADDSEL SCLK SDI CHD CVD ADD16 ADD15 ADD14 GND VDD ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 GND ADD5 ADD4 ADD3 ADD2 ADD1 I/O IC IC – – IC IC IC IC IC IC IC IC – – IC IC OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M – – OBF4M OBF4M OBF4M IO4M IO4M IO4M IO4M IO4M – IO4M IO4M IO4M IO4M IO4M POLARITY Initializing input. Clock input. Connect to pin 14 of LZ34C10. A grounding pin. Supply of +3.0 V power. Digital signal input, fed from pin 23 of LZ34C10 (MSB). Digital signal input, fed from pin 22 of LZ34C10. Digital signal input, fed from pin 21 of LZ34C10. Digital signal input, fed from pin 20 of LZ34C10. Digital signal input, fed from pin 19 of LZ34C10. Digital signal input, fed from pin 18 of LZ34C10. Digital signal input, fed from pin 17 of LZ34C10. Digital signal input, fed from pin 16 of LZ34C10 (LSB). A grounding pin. Supply of +3.0 V power. A test pin. Connect to GND. Pin to set MSB to be added on serial address data. Low : MSB = 0 (address 00h-7Fh), High : MSB = 1 (address 80h-FFh) Clock output of serial data, connected to pin 28 of LZ34C10. Serial data output, connected to pin 27 of LZ34C10. Horizontal drive pulse output, connected to pin 25 of LZ34C10. Vertical drive pulse output, connected to pin 26 of LZ34C10. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. A grounding pin. Supply of +3.0 V power. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. A grounding pin. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. DESCRIPTION 4 LR38630 PIN NO. SYMBOL 40 ADD0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 TST1 TST2 OE WE MDIO7 MDIO6 MDIO5 MDIO4 MDIO3 MDIO2 MDIO1 MDIO0 EXMCK GND VDD RCLK DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VDD CTLDIN I/O POLARITY DESCRIPTION IO4M Address output to drive an external SRAM. IC IC OBF4M OBF4M IO4MU IO4MU IO4MU IO4MU IO4MU IO4MU IO4MU IO4MU IC – – OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M OBF4M – – IC A test pin. Connected to GND. A test pin. Connected to GND. Output enable to drive an external SRAM. Write enable to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. Address output to drive an external SRAM. External clock input. A grounding pin. Supply of +3.0 V power. Clock output for digital video output signal. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. A grounding pin. Supply of +3.0 V power. Serial data input. Serial data input. The rising edge enables the serial data to be available. Clock input to set the data. High level puts this IC and LZ34C10 in standby mode. Horizontal blanking pulse output keeping high level during the effective image period. Horizontal pulse output going to low level when starting in horizontal. Vertical blanking pulse output keeping high level during the effective image period. A grounding pin. Supply of +3.0 V power. Data input/output to/from EEPROM. Going to high-impedance with high level of pin 80. CTLDOUT OBF4M CTLDEN IC CTLDCK STANDBY HREF IC IC OBF4M OLSTEN OBF4M VS GND VDD EEPDA OBF4M – – IO4M 5 LR38630 PIN NO. SYMBOL 78 EEPCK I/O IO4M POLARITY DESCRIPTION Clock input/output to/from EEPROM. Going to high-impedance with high level of pin 80. The option of number of bits of serial data to adjust. High level : W/R flag + address 6 bits + data 16 bits Low level : W/R flag + address 8 bits + data 8 bits Void input of internal automatic control circuit, connected to low level normally. 80 IO4M IO4MU 79 IFMODE IC ADJMODE IC High level input stops automatic control function. Power-on with high level input stops automatic loading of EEPROM data. OBF4M IC : Output pin (4 mA output) : Input pin (CMOS level input) : Input/output pin (4 mA output, CMOS level input) : Input/output pin (4 mA output, CMOS level input with pull-up resistor) 6 LR38630 INTERNAL COEFFICIENT TABLE ADDRESS 00h 01h 02h MOS_MIR NAME – – BITS – Not used. – 2 (7) (6) 2 (5) (4) 3 (3) MOS_AGC (2) (1) 1 (0) 1 (7) 1 (6) 1 (5) 2 WB_MODE (4) (3) 2 EE_HOLD (2) (1) Not used. Option of the output image type. 00 : Normal 10 : Reversed left and right Option of AD converter clock phase. 00 : Reference 10 : Delayed by 180˚ Option of AGC offset gain. 000 : 3 dB 001 : 4 dB 010 : 5 dB 100 : 7 dB 110 : 9 dB MOS_STD 03h QCIF_SEL 011 : 6 dB 101 : 8 dB 111 : 10 dB 01 : Inverted top and bottom 11 : Reversed all 01 : Delayed by 90˚ 11 : Delayed by 270˚ FUNCTION MOS_SAD Under low level at pin 71, this bit can make CMOS image sensor standby. 0 : Operating 1 : Standby Option of sampling position in QCIF. 0 : Red filter 1 : Green filter Carrier balance function. 0 : Automatic added an offset (coefficient) 1 : 0h added an offset (coefficient) Option of exposure level reference. 0 : Data of address 06h 1 : Data of address 09h Option of white balance mode. 00 : Automatic 01 : Preset WB1 1X : Preset WB2 Option of electronic exposure mode. 00 : Automatic electronic shutter speed and AGC ON 01 : Fixed electronic shutter speed and AGC ON 10 : Automatic electronic shutter speed and AGC OFF 11 : Fixed electronic shutter speed and AGC OFF Option of optical black level control. 0 : Automatic 1 : Fixed level CA_HOLD BLC OFSET_AUTO 1 (0) 7 LR38630 ADDRESS 04h NAME OUT_SEL BITS 2 Option of output mode. (7) (6) 2 IN_TIM (5) (4) 4 (3) (2) (1) (0) 00 : QCIF1 10 : QVGA Clock timing for input. 00 : Delayed by one CK 10 : Not delayed 01 : Delayed by two CK 01 : CIF 11 : QCIF2 FUNCTION 0000 : CIF image output with CKI clock of CMOS image sensor 0001 : 1 frame of image output per second with CKI clock 0010 : 2 frames of image output per second with CKI clock 0011 : 15 frames of image output per second with CKI clock 0101 : 1 frame of image output per second with EXCK clock (1 frame data is written to RAM in vertical blanking.) 0110 : 2 frames of image output per second with EXCK clock (2 frames data are written to RAM in vertical blanking.) 0111 : Image output with EXMCK clock (EXMCK should be lower than 4.5 MHz.) 1XXX : Except 0000, works with 30 frames after power-on. (example) 1001 : 1 frame of image output per second with CKI starting with 30 frames after power-on. 1000 : Prohibited to use Setting a period to work with 30 frames after power-on. A period = (Data + 1) x frame rate Electronic exposure reference level. The second target area of electronic exposure control. In the case that exposure control data is within (data of address 06h ± data of address 07h), the exposure control is completed. ACT_MODE 05h 06h 07h ACT_TIM REF_IRIS CTLD_01 8 8 8 08h CTLD_02 09h 0Ah CTLD_11 0Bh CTLD_12 REF_BLC 8 The first target area of electronic exposure control. If exposure control data is over (data of address 06h ± data of address 08h), the exposure control is restarted. Exposure reference level in BLC (valid with BLC of address 03h = 1). The second target area of electronic exposure control in BLC. In the case that exposure control data is within (data of address 09h ± data of address 0Ah), the exposure control is completed. 8 8 8 The first target area of electronic exposure control in BLC. If exposure control data is over (data of address 09h ± data of address 0Bh), the exposure control is restarted. 8 LR38630 ADDRESS 0Ch NAME BITS FUNCTION 2 Option of maximum electronic shutter speed in automatic. (7) (6) Electronic exposure control. 00 : 1/9 900 s 01 : 1/4 950 s 10 : 1/1 980 s 11 : 1/1 100 s 2 (5) (4) 2 EE_RATIO (3) (2) 2 EE_LPF 0Dh 0Eh 0Fh 10h 11h OFSET_LPF SH_HOLD2 SH_HOLD1 AGC_HOLD OFSET_HOLD (1) (0) 1 8 8 8 2 (4) (3) 1 (2) 2 (1) (0) 8 KGBGR1 Option of electronic shutter speed and AGC speed change. 00 : Shutter speed is changed by 10-19 pitches. 01 : Shutter speed is changed by 8-10 pitches. 1X : Shutter speed is changed by 1 pitch (the finest) Window option of automatic electronic exposure control. 00 : Center weighted 1 10 : No window 01 : Center weighted 2 11 : Lower-position weighted SH_MAX EE_SPD Option of time constant in electronic exposure control. 00 : Longer time constant 01 : Long time constant 1X : No time constant MSB of fixed electronic shutter speed. Lower bits of fixed electronic shutter speed. Data between 000 and 149 can be set by address 0Dh and 0Eh. Preset gain in making AGC OFF (EE_HOLD = 1X at address 03h). Fixed optical black level (OFSET_AUTO =1 at address 03h). Time constant option of automatic optical black level control. 00 : Longer time constant 01 : Long time constant 1X : No time constant Option of automatic white balance control. 0 : Not accelerated 1 : Accelerated Time constant option of automatic white balance control. 00 : Longer time constant 01 : Long time constant 1X : No time constant The first target area of automatic white balance control in minus direction of highspeed mode. In the case that white balance control data is within (data of address 12h + data of address 13h), high-speed mode control is completed and then changed to normalspeed control mode. WBFIX1 SEL_LPF 12h 9 LR38630 ADDRESS 13h NAME BITS FUNCTION The first target area of automatic white balance control in plus direction of high8 speed mode. KGBGR2 In the case that white balance control data is within (data of address 12h + data of address 13h), high-speed mode control is completed and then changed to normalspeed control mode. 14h KGBGR3 8 The second target area of automatic white balance control in minus direction of high-speed mode. In the case that white balance control data is over (data of address 14h + data of address 15h), high-speed mode control is restarted. 15h KGBGR4 8 The second target area of automatic white balance control in plus direction of highspeed mode. In the case that white balance control data is over (data of address 14h + data of address 15h), high-speed mode control is restarted. 8 8 8 8 8 8 7 LIMWIIM 1Dh 1Eh 1Fh 20h LIMWIIP LIMWIQM LIMWIQP LIMWOI 21h LIMWOQ 22h 23h 24h 25h 26h 27h 28h 29h WBR_MAX WBR_MIN WBB_MAX WBB_MIN WBR1 WBB1 WBR2 WBB2 8 8 8 8 8 8 8 8 7 7 7 7 7 Limitation in making white balance data at minus I-axis. Limitation in making white balance data at plus I-axis. Limitation in making white balance data at minus Q-axis. Limitation in making white balance data at plus Q-axis. Limitation in making white balance data. A pixel with lower luminance level than data of this address is neglected. Limitation in making white balance data. A pixel with higher luminance level than data of this address is neglected. The first target area of auto white balance control in minus I-axis. In the case that white balance control data is within the area by address 1Ch, 1Dh, 1Eh and 1Fh, automatic white balance control is completed. The first target area of auto white balance control in plus I-axis. The first target area of auto white balance control in minus Q-axis. The first target area of auto white balance control in plus Q-axis. The second target area of auto white balance control in I-axis. In the case that white balance control data is over the area by address 20h and 21h, automatic white balance control is restarted. The second target area of auto white balance control in Q-axis. In the case that white balance control data is over the area by address 20h and 21h, automatic white balance control is restarted. Maximum gain of red signal in automatic white balance control. Minimum gain of red signal in automatic white balance control. Maximum gain of blue signal in automatic white balance control. Minimum gain of blue signal in automatic white balance control. White balance preset 1 : Red signal gain White balance preset 1 : Blue signal gain White balance preset 2 : Red signal gain White balance preset 2 : Blue signal gain 16h 17h 18h 19h 1Ah 1Bh 1Ch LIMIM LIMIP LIMQM LIMQP YLCL YHCL 10 LR38630 ADDRESS NAME 2Ah GAM_SLOPE0 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h GAM_SLOPE1 GAM_SLOPE2 GAM_SLOPE3 GAM_SLOPE4 GAM_SLOPE5 GAM_SLOPE6 GAM_SLOPE7 GAM_SLOPE8 GAM_SLOPE9 GAM_OFSET1 GAM_OFSET2 GAM_OFSET3 GAM_OFSET4 GAM_OFSET5 GAM_OFSET6 GAM_OFSET7 GAM_OFSET8 GAM_OFSET9 KCBR KCBB KCBG1 KCBG2 KY1 KHC KHGA KVC KVGA KLL KSU K0_MAT1 K1_MAT1 K2_MAT1 K3_MAT1 K0_MAT2 K1_MAT2 K2_MAT2 K3_MAT2 K0_MAT3 K1_MAT3 K2_MAT3 BITS FUNCTION 8 Gamma curve setting : First straight line slope 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 6 8 6 8 8 6 8 8 8 8 8 8 8 8 8 8 8 Gamma curve setting : Second straight line slope Gamma curve setting : Third straight line slope Gamma curve setting : Fourth straight line slope Gamma curve setting : Fifth straight line slope Gamma curve setting : Sixth straight line slope Gamma curve setting : Seventh straight line slope Gamma curve setting : Eighth straight line slope Gamma curve setting : Ninth straight line slope Gamma curve setting : Tenth straight line slope Gamma curve setting : Second straight line offset Gamma curve setting : Third straight line offset Gamma curve setting : Fourth straight line offset Gamma curve setting : Fifth straight line offset Gamma curve setting : Sixth straight line offset Gamma curve setting : Seventh straight line offset Gamma curve setting : Eighth straight line offset Gamma curve setting : Ninth straight line offset Gamma curve setting : Tenth straight line offset Carrier balance : Red signal compensation Carrier balance : Blue signal compensation Carrier balance : Green signal compensation in RG line Carrier balance : Green signal compensation in BG line Gain in middle frequency components of luminance signal. Horizontal aperture level compression in lower luminance level. Horizontal aperture gain. Vertical aperture level compression in lower luminance level. Vertical aperture gain. Luminance level. Set up level. AWB color matrix : R – Y 1 AWB color matrix : R – Y 2 AWB color matrix : B – Y 1 AWB color matrix : B – Y 2 WB1 color matrix : R – Y 1 WB1 color matrix : R – Y 2 WB1 color matrix : B – Y 1 WB1 color matrix : B – Y 2 WB2 color matrix : R – Y 1 WB2 color matrix : R – Y 2 WB2 color matrix : B – Y 1 11 LR38630 ADDRESS NAME 53h K3_MAT3 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah KCRGA KCBGA KCRGA1 KCBGA1 KCRGA2 KCBGA2 KCCR KCCB KCLC KLGL KCHC KLGH KLGE KILL_AGC KILL_AGCG APT_AGC APT_AGCG FPN_GA AGC_SLP1 AGC_SLP2 AGC_SLP3 AGC_SLP4 IN_OUT – – – – TEST R_DATA1 R_DATA2 G_DATA1 G_DATA2 B_DATA1 B_DATA2 I_DATA1 I_DATA2 Q_DATA1 Q_DATA2 IRIS_DATA1 BITS 8 WB2 color matrix : B – Y 2 8 8 8 8 8 8 7 7 8 4 8 4 8 8 4 8 4 8 8 8 8 8 1 (0) – – – – 5 8 4 8 4 8 4 8 1 8 1 8 AWB color level : R – Y AWB color level : B – Y WB1 color level : R – Y WB1 color level : B – Y WB2 color level : R – Y WB2 color level : B – Y R – Y color signal base clip level. B – Y color signal base clip level. Lower luminance level to suppress color signal level. Gain to suppress color signal level by data of address 5Ch. Higher luminance level to suppress color signal level. Gain to suppress color signal level by data of address 5Eh. Gain to suppress color edge signal. AGC gain to start the suppression of color signal level. Gain to suppress color signal level by data of address 61h. AGC gain to start the suppression of aperture level. Gain to suppress aperture level by data of address 63h. Gain for fixed pattern noise signal. AGC gain compensation 1 for fixed pattern noise signal. AGC gain compensation 2 for fixed pattern noise signal. AGC gain compensation 3 for fixed pattern noise signal. AGC gain compensation 4 for fixed pattern noise signal. Option of output mode. 0 : Normal processing Not used. Not used. Not used. Not used. Data should be 00h. Lower 8 bits of red signal to control auto white balance. Upper 4 bits of red signal to control auto white balance. Lower 8 bits of green signal to control auto white balance. Upper 4 bits of green signal to control auto white balance. Lower 8 bits of blue signal to control auto white balance. Upper 4 bits of blue signal to control auto white balance. Lower 8 bits of I signal to control auto white balance. Sign bit of I signal to control auto white balance. Lower 8 bits of Q signal to control auto white balance. Sign bit of Q signal to control auto white balance. Lower 8 bits of luminance signal to control auto exposure. 1 : Output of input signal1 FUNCTION 12 LR38630 ADDRESS NAME BITS FUNCTION Upper 4 bits of luminance signal to control auto exposure. 7Bh IRIS_DATA2 4 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h RCA_DATA GRCA_DATA BCA_DATA GBCA_DATA WP00H1 WP00H2 WP00V1 WP00V2 WP01H1 WP01H2 WP01V1 WP01V2 WP02H1 WP02H2 WP02V1 WP02V2 WP03H1 WP03H2 WP03V1 WP03V2 WP04H1 WP04H2 WP04V1 WP04V2 WP05H1 WP05H2 WP05V1 WP05V2 WP06H1 WP06H2 WP06V1 WP06V2 WP07H1 WP07H2 WP07V1 WP07V2 WP08H1 WP08H2 WP08V1 WP08V2 8 8 8 8 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 Red signal to control auto carrier balance. Green signal in RG line to control auto carrier balance. Blue signal to control auto carrier balance. Green signal in BG line to control auto carrier balance. Lower 8 bits of X-axis on the position of white blemish 1. MSB of X-axis on the position of white blemish 1. Lower 8 bits of Y-axis on the position of white blemish 1. MSB of Y-axis on the position of white blemish 1. Lower 8 bits of X-axis on the position of white blemish 2. MSB of X-axis on the position of white blemish 2. Lower 8 bits of Y-axis on the position of white blemish 2. MSB of Y-axis on the position of white blemish 2. Lower 8 bits of X-axis on the position of white blemish 3. MSB of X-axis on the position of white blemish 3. Lower 8 bits of Y-axis on the position of white blemish 3. MSB of Y-axis on the position of white blemish 3. Lower 8 bits of X-axis on the position of white blemish 4. MSB of X-axis on the position of white blemish 4. Lower 8 bits of Y-axis on the position of white blemish 4. MSB of Y-axis on the position of white blemish 4. Lower 8 bits of X-axis on the position of white blemish 5. MSB of X-axis on the position of white blemish 5. Lower 8 bits of Y-axis on the position of white blemish 5. MSB of Y-axis on the position of white blemish 5. Lower 8 bits of X-axis on the position of white blemish 6. MSB of X-axis on the position of white blemish 6. Lower 8 bits of Y-axis on the position of white blemish 6. MSB of Y-axis on the position of white blemish 6. Lower 8 bits of X-axis on the position of white blemish 7. MSB of X-axis on the position of white blemish 7. Lower 8 bits of Y-axis on the position of white blemish 7. MSB of Y-axis on the position of white blemish 7. Lower 8 bits of X-axis on the position of white blemish 8. MSB of X-axis on the position of white blemish 8. Lower 8 bits of Y-axis on the position of white blemish 8. MSB of Y-axis on the position of white blemish 8. Lower 8 bits of X-axis on the position of white blemish 9. MSB of X-axis on the position of white blemish 9. Lower 8 bits of Y-axis on the position of white blemish 9. MSB of Y-axis on the position of white blemish 9. 13 LR38630 ADDRESS NAME A4h WP09H1 A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh WP09H2 WP09V1 WP09V2 WP0AH1 WP0AH2 WP0AV1 WP0AV2 WP0BH1 WP0BH2 WP0BV1 WP0BV2 WP0CH1 WP0CH2 WP0CV1 WP0CV2 WP0DH1 WP0DH2 WP0DV1 WP0DV2 WP0EH1 WP0EH2 WP0EV1 WP0EV2 WP0FH1 WP0FH2 WP0FV1 WP0FV2 WP10H1 WP10H2 WP10V1 WP10V2 WP11H1 WP11H2 WP11V1 WP11V2 WP12H1 WP12H2 WP12V1 WP12V2 WP13H1 BITS FUNCTION 8 Lower 8 bits of X-axis on the position of white blemish 10. 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 MSB of X-axis on the position of white blemish 10. Lower 8 bits of Y-axis on the position of white blemish 10. MSB of Y-axis on the position of white blemish 10. Lower 8 bits of X-axis on the position of white blemish 11. MSB of X-axis on the position of white blemish 11. Lower 8 bits of Y-axis on the position of white blemish 11. MSB of Y-axis on the position of white blemish 11. Lower 8 bits of X-axis on the position of white blemish 12. MSB of X-axis on the position of white blemish 12. Lower 8 bits of Y-axis on the position of white blemish 12. MSB of Y-axis on the position of white blemish 12. Lower 8 bits of X-axis on the position of white blemish 13. MSB of X-axis on the position of white blemish 13. Lower 8 bits of Y-axis on the position of white blemish 13. MSB of Y-axis on the position of white blemish 13. Lower 8 bits of X-axis on the position of white blemish 14. MSB of X-axis on the position of white blemish 14. Lower 8 bits of Y-axis on the position of white blemish 14. MSB of Y-axis on the position of white blemish 14. Lower 8 bits of X-axis on the position of white blemish 15. MSB of X-axis on the position of white blemish 15. Lower 8 bits of Y-axis on the position of white blemish 15. MSB of Y-axis on the position of white blemish 15. Lower 8 bits of X-axis on the position of white blemish 16. MSB of X-axis on the position of white blemish 16. Lower 8 bits of Y-axis on the position of white blemish 16. MSB of Y-axis on the position of white blemish 16. Lower 8 bits of X-axis on the position of white blemish 17. MSB of X-axis on the position of white blemish 17. Lower 8 bits of Y-axis on the position of white blemish 17. MSB of Y-axis on the position of white blemish 17. Lower 8 bits of X-axis on the position of white blemish 18. MSB of X-axis on the position of white blemish 18. Lower 8 bits of Y-axis on the position of white blemish 18. MSB of Y-axis on the position of white blemish 18. Lower 8 bits of X-axis on the position of white blemish 19. MSB of X-axis on the position of white blemish 19. Lower 8 bits of Y-axis on the position of white blemish 19. MSB of Y-axis on the position of white blemish 19. Lower 8 bits of X-axis on the position of white blemish 20. 14 LR38630 ADDRESS NAME CDh WP13H2 CEh WP13V1 CFh WP13V2 D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h WP14H1 WP14H2 WP14V1 WP14V2 WP15H1 WP15H2 WP15V1 WP15V2 WP16H1 WP16H2 WP16V1 WP16V2 WP17H1 WP17H2 WP17V1 WP17V2 WP18H1 WP18H2 WP18V1 WP18V2 WP19H1 WP19H2 WP19V1 WP19V2 WP1AH1 WP1AH2 WP1AV1 WP1AV2 WP1BH1 WP1BH2 WP1BV1 WP1BV2 WP1CH1 WP1CH2 WP1CV1 WP1CV2 WP1DH1 WP1DH2 BITS FUNCTION 1 MSB of X-axis on the position of white blemish 20. 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 Lower 8 bits of Y-axis on the position of white blemish 20. MSB of Y-axis on the position of white blemish 20. Lower 8 bits of X-axis on the position of white blemish 21. MSB of X-axis on the position of white blemish 21. Lower 8 bits of Y-axis on the position of white blemish 21. MSB of Y-axis on the position of white blemish 21. Lower 8 bits of X-axis on the position of white blemish 22. MSB of X-axis on the position of white blemish 22. Lower 8 bits of Y-axis on the position of white blemish 22. MSB of Y-axis on the position of white blemish 22. Lower 8 bits of X-axis on the position of white blemish 23. MSB of X-axis on the position of white blemish 23. Lower 8 bits of Y-axis on the position of white blemish 23. MSB of Y-axis on the position of white blemish 23. Lower 8 bits of X-axis on the position of white blemish 24. MSB of X-axis on the position of white blemish 24. Lower 8 bits of Y-axis on the position of white blemish 24. MSB of Y-axis on the position of white blemish 24. Lower 8 bits of X-axis on the position of white blemish 25. MSB of X-axis on the position of white blemish 25. Lower 8 bits of Y-axis on the position of white blemish 25. MSB of Y-axis on the position of white blemish 25. Lower 8 bits of X-axis on the position of white blemish 26. MSB of X-axis on the position of white blemish 26. Lower 8 bits of Y-axis on the position of white blemish 26. MSB of Y-axis on the position of white blemish 26. Lower 8 bits of X-axis on the position of white blemish 27. MSB of X-axis on the position of white blemish 27. Lower 8 bits of Y-axis on the position of white blemish 27. MSB of Y-axis on the position of white blemish 27. Lower 8 bits of X-axis on the position of white blemish 28. MSB of X-axis on the position of white blemish 28. Lower 8 bits of Y-axis on the position of white blemish 28. MSB of Y-axis on the position of white blemish 28. Lower 8 bits of X-axis on the position of white blemish 29. MSB of X-axis on the position of white blemish 29. Lower 8 bits of Y-axis on the position of white blemish 29. MSB of Y-axis on the position of white blemish 29. Lower 8 bits of X-axis on the position of white blemish 30. MSB of X-axis on the position of white blemish 30. 15 LR38630 ADDRESS NAME F6h WP1DV1 F7h F8h F9h FAh FBh FCh FDh FEh FFh WP1DV2 WP1EH1 WP1EH2 WP1EV1 WP1EV2 WP1FH1 WP1FH2 WP1FV1 WP1FV2 BITS FUNCTION 8 Lower 8 bits of Y-axis on the position of white blemish 30. 1 8 1 8 1 8 1 8 1 MSB of Y-axis on the position of white blemish 30. Lower 8 bits of X-axis on the position of white blemish 31. MSB of X-axis on the position of white blemish 31. Lower 8 bits of Y-axis on the position of white blemish 31. MSB of Y-axis on the position of white blemish 31. Lower 8 bits of X-axis on the position of white blemish 32. MSB of X-axis on the position of white blemish 32. Lower 8 bits of Y-axis on the position of white blemish 32. MSB of Y-axis on the position of white blemish 32. 16 LR38630 Default Data Table ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh DATA – – 10 00 00 00 30 03 06 3A 04 08 00 00 E7 00 80 00 6B 9A 55 C0 80 80 40 40 04 FE 02 02 02 02 ADDRESS 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh DATA 05 05 FE 10 FE 10 40 40 40 40 14 18 20 18 18 12 0F 0F 0E 07 14 20 30 3C 48 5A 78 B4 DE 00 00 00 ADDRESS 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh DATA 00 40 04 00 04 00 80 00 2D F9 39 ED 2D F9 39 ED 2D F9 39 ED 40 40 40 40 40 40 04 04 00 00 F0 08 ADDRESS 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh DATA 10 E0 04 E0 04 20 06 0B 14 23 00 – – – – 00 – – – – – – – – – – – – – – – – 17 LR38630 ABSOLUTE MAXIMUM RATINGS PARAMETER Power supply voltage Input voltage Output voltage Storage temperature SYMBOL VDD VI VO TSTG RATING –0.3 to +4.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 UNIT V V V ˚C RECOMMENDED OPERATING CONDITIONS PARAMETER Power supply voltage Operating temperature Input clock frequency SYMBOL VDD TOPR fCK MIN. 2.7 –20 TYP. 3.0 +25 9.0 MAX. 3.3 +70 UNIT V ˚C MHz ELECTRICAL CHARACTERISTICS PARAMETER Input "Low" voltage Input "High" voltage Input "Low" current Input "High" current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage SYMBOL VIL VIH |IIL1| |IIH1| |IIL2| |IIH2| VOL VOH VIN = 0 V VIN = VDD VI = 0 V VIN = VDD IOL = 4 mA IOH = –4 mA CONDITIONS (VDD = 3.0±0.3 V, TOPR = –20 to +70 ˚C) MIN. 0.8VDD TYP. MAX. UNIT 0.2VDD V V 1.0 1.0 40 100 300 2.0 0.2VDD 0.8VDD µA µA µA µA V V NOTE 1 2 3 4 NOTES : 1. 2. 3. 4. Applied Applied Applied Applied to to to to input (IC) and inputs/outputs (IO4M, IO4MU). input (IC) and input/output (IO4M). input/output (IO4MU). output (OBF4M) and inputs/outputs (IO4M, IO4MU). 18 LR38630 (APPENDIX) Weighting area of exposure control 1 block = 44 pixels in horizontal and 36 lines in vertical q (Bit 3, Bit 2) of address 0Ch = (0, 0) 2/4 1 1 1 1 1 1 1 2/4 1 1 1 1 1 1 1 2/4 1 1 5/4 5/4 5/4 5/4 1 2/4 1 1 5/4 5/4 5/4 5/4 1 2/4 1 1 5/4 5/4 5/4 5/4 1 2/4 1 1 5/4 5/4 5/4 5/4 1 2/4 1 1 1 1 1 1 1 2/4 1 1 1 1 1 1 1 w (Bit 3, Bit 2) of address 0Ch = (0, 1) 2/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 2/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 e (Bit 3, Bit 2) of address 0Ch = (1, 0) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r (Bit 3, Bit 2) of address 0Ch = (1, 1) 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 2/4 2/4 1 1 5/4 5/4 5/4 5/4 19 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE 80 LQFP (LQFP080-P-1212) 0.08 0.5TYP. 60 61 0.2±0.08 (1.0) 41 40 0.125±0.05 M (Unit : mm) 12.0±0.2 14.0±0.3 13.0±0.2 0.6375 1.70MAX. 1.40±0.2 0.1±0.1 Package base plane 80 1 (1.0) 12.0±0.2 14.0±0.3 20 21 (1.0) (1.0) 20 0.10