LRS1386

L R S1 3 8 6 Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). • • • • • • Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. • Control and safety devices for airplanes, trains, automobiles, and other transportation equipment • Mainframe computers • Traffic control systems • Gas leak detectors and automatic cutoff devices • Rescue and security equipment • Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. • • • • Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. L R S1 3 8 6 1 Contents 1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Identifier Codes and OTP Address for Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Identifier Codes and OTP Address for Read Operation on Partition Configuration . . . . . . . . . . . . . . . . . . . . . . 10 5.4 OTP Block Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Functions of Block Lock and Block Lock-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Status Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance . . . . . . . . . . . . . . . . . . . 22 12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 SRAM AC Characteristics Timing Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 29 14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 L R S1 3 8 6 2 1. Description The LRS1386 is a combination memory organized as 4,194,304 x16 bit flash memory and 524,288 x16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon Flash Memory - Access Time Read Word write Block erase Reset Power-Down Standby - Optimized Array Blocking Architecture Eight 4K-word Parameter Blocks One-hundred and twenty-seven 32K-word Main Blocks Top Parameter Location - Extended Cycling Capability 100,000 Block Erase Cycles (F-VPP = 2.7V to 3.3V) 1,000 Block Erase Cycles and total 80 hours (F-VPP = 11.7V to 12.3V) - Enhanced Automated Suspend Options Word Write Suspend to Read Block Erase Suspend to Word Write Block Erase Suspend to Read - OTP Block 4 Word + 4 Word Array SRAM - Access Time - Power Supply current Operating current Standby current Data retention current •••• •••• 2.7V to 3.3V -25°C to +85°C •••• •••• •••• •••• •••• •••• 90 ns 25 mA 60 mA 30 mA 25 µA 25 µA (Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max. F-RST = GND ± 0.2V, IOUT (F-RY/BY) = 0mA) (Max. F-CE = F-RST = F -VCC ± 0.2V) - Power supply current (The current for F-VCC pin and F-VPP pin) •••• •••• •••• •••• •••• 85 ns 50 mA 8 mA 25 µA 25 µA (Max.) (Max. tRC, tWC = Min.) (Max. tRC, tWC = 1µs, CMOS Input) (Max.) (Max. S-VCC = 3.0V) L R S1 3 8 6 3 2. Pin Configuration INDEX (TOP View) L R S1 3 8 6 4 Pin A0 to A16, A18 F-A17, F-A19 to F-A21 S-A17 F-CE S-CE1, S-CE2 F-WE S-WE F-OE S-OE S-LB S-UB Address Inputs (Common) Address Inputs (Flash) Address Input (SRAM) Chip Enable Inputs (Flash) Chip Enable Inputs (SRAM) Write Enable Input (Flash) Write Enable Input (SRAM) Output Enable Input (Flash) Output Enable Input (SRAM) Description Type Input Input Input Input Input Input Input Input Input Input Input SRAM Byte Enable Input (DQ0 to DQ7) SRAM Byte Enable Input (DQ8 to DQ15) Reset Power Down Input (Flash) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Write Protect Input (Flash) When F-WP is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and locked-down. When F-WP is VIH, lock-down is disabled. Ready/Busy Output (Flash) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Data Inputs and Outputs (Common) Power Supply (Flash) Power Supply (SRAM) Monitoring Power Supply Voltage (Flash) Block Erase and Write : F-VPP = VPPH1/2 All Blocks Locked : F-VPP < VPPLK GND (Common) Non Connection (Should be all open) Test pins (Should be all open) F-RST Input F-WP Input F-RY/BY DQ0 to DQ15 F-VCC S-VCC F-VPP GND NC T1 to T 3 Open Drain Output Input / Output Power Power Input Power - L R S1 3 8 6 5 3. Truth Table 3.1 Bus operation(1) Flash Read Output Disable Write Read Standby Output Disable Write Read Reset Power Output Down Disable Write Standby Reset Power Standby Down Notes: 1. L = VIL, H = VIH, X = H or L. High-Z = High impedance. Refer to the DC Characteristics. 2. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when F-VPP = VPPH1/2 and F-VCC = 2.7V to 3.3V. Block erase, full chip erase, (page buffer) program or OTP program with F-VPP < VPPH1/2 (Min.) produce spurious results and should not be attempted. 3. Never hold F-OE low and F-WE low at the same timing. 4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation. 5. F-WP set to VIL or VIH. 6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V. 7. Flash Read Mode Mode Read Array Read Identifier Codes/OTP Read Query 8. SRAM Standby Mode S-CE1 S-CE2 S-LB S-UB H X X X L X X X H X X H Address X See 5.2, 5.3 Refer to the Appendix DQ0 to DQ15 DOUT See 5.2, 5.3 Refer to the Appendix Standby SRAM Notes 3,5 5 2,3,4,5 5 5 5 5,6 5,6 5,6 5 5,6 H X H L X X (8) X X (8) High-Z X L X X L H H H X X L H L H F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15 L H H L L H X X L H X X H H X L H H X L X H X H (9) X H X H (9) (9) High-Z (9) High-Z (8) X X (8) (7) High-Z DIN 9. S-UB, S-LB Control Mode S-LB S-UB DQ0 to DQ7 L L H L H L DOUT/DIN DOUT/DIN High-Z DQ8 to DQ15 DOUT/DIN High-Z DOUT/DIN L R S1 3 8 6 6 3.2 Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend Notes: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing except page buffer program. Commands must be written to an address within the block targeted by that command. X X X X X X Read Array X X X X X X Read ID/OTP X X X X X X Read Status X X X X X X X X X X X X X X X X X X Read Query X X X X X X Page Word OTP Buffer Program Program Program X X X X X X X X X Block Erase X X X X X Full Chip Erase Program Suspend X X X X Block Erase Suspend X X X X X X L R S1 3 8 6 7 4. Block Diagram L R S1 3 8 6 8 5. Command Definitions for Flash Memory(11) 5.1 Command Definitions Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Set Partition Configuration Register Notes: 1. Bus operations are defined in 3.1 Bus operation. 2. First bus cycle command address should be the same as the second cycle address. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See 5.2, 5.3). QA=Query codes address. Refer to the LH28F320BX, LH28F640BX series Appendix for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See 5.4 OTP Block Address Map). PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes. (See 5.2, 5.3 ). QD=Data read from query database. Refer to the LH28F320BX, LH28F640BX series Appendix for details. SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). OD=Data to be programmed at location OA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within OTP block (See 5.2, 5.3 ). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when F-RST is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. Bus Cycles Req’d 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 2 First Bus Cycle Notes 2 2,3,4 2,3,4 2,3 2 2,3,5 2,5,9 2,3,5,6 2,3,5,7 2,8,9 2,8,9 2 2,10 2 2,3,9 2,3 Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address(2) PA PA PA PA PA BA X WA WA PA PA BA BA BA OA PCRC Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H 60H Write Write Write Write Write BA BA BA OA PCRC 01H D0H 2FH OD 04H Write Write Write Write BA X WA WA D0H D0H WD N-1 Read Read Read IA or OA ID or OD QA PA QD SRD Second Bus Cycle Oper(1) Address(2) Data(3) L R S1 3 8 6 9 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F320BX, LH28F640BX series Appendix for details. 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is VIL. When F-WP is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. L R S1 3 8 6 10 5.2 Identifier Codes and OTP Address for Read Operation Code Manufacturer Code Device Code Manufacturer Code 64M TopParameter Device Code Block is Unlocked Block is Locked Block Lock Configuration Code Block is not Locked-Down Block is Locked-Down Device Configuration Code OTP Notes: 1. The address A21-A16 to read the manufacturer, device, lock configuration, device configuration code and OTP data are shown in below table. 2. Top parameter device has its parameter blocks in the plane 3 (The highest address). 3. DQ15-DQ2 is reserved for future implementation. 4. PCRC=Partition Configuration Register Code. 5. OTP-LK=OTP Block Lock configuration. 6. OTP=OTP Block data. 5.3 Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) Partition Configuration Register PCR.10 0 0 0 1 0 1 1 1 Notes: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H). PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 10H 00H or 20H 00H or 30H 00H or 10H or 20H 00H or 20H or 30H 00H or 10H or 30H 00H or 10H or 20H or 30H Address (64M-bit device) [A21-A16] Partition Configuration Register OTP Lock OTP 0006H 0080H 0081-0088H Block Address +2 Address [A15-A0](1) 0000H 0001H Data [DQ15-DQ0] 00B0H 00B0H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC OTP-LK OTP 2 3 3 3 3 4 5 6 Notes L R S1 3 8 6 11 5.4 OTP Block Address Map 5.5 Functions of Block Lock(1) and Block Lock-Down Current State State [000] [001] [011] [100] [101](4) [110](5) [111] Note: 1. OTP (One Time Program) block has the lock function which is different from those described above. 2. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 3. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 4. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101] (F-WP = 1), regardless of the states before power-off or reset operation. 5. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. (4) (2) F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0(2) 0 1 1 0 1 0 1 Locked State Name Unlocked Erase/Program Allowed (3) Yes No No Yes No Yes No Locked-down Unlocked Locked Lock-down Disable Lock-down Disable L R S1 3 8 6 12 5.6 Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] Note: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lockdown" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that F-WP is not changed and fixed VIL or VIH. 5.7 Block Locking State Transitions upon F-WP Transition(4) Current State Previous State State [110](2) Other than [110](2) Note: 1. "F-WP = 0 1" means that F-WP is driven to VIH and "F-WP = 1 0" means that F-WP is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. [000] [001] [011] [100] [101] [110] [111] F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 F-WP = 0 1(1) [100] [101] [110] [111] F-WP = 1 0(1) [000] [001] [011](3) [011] Result after F-WP Transition (Next State) F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change Clear Lock(1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change L R S1 3 8 6 13 6. Status Register Definition Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 Notes: Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. R 11 VPPS 3 R 10 PBPSS 2 R 9 DPS 1 R 8 R 0 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP LOW Detect, Operation Abort 0 = F-VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked Check SR.7 or F-RY/BY to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set read/partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of F-VPP level. The WSM interrogates and indicates the F-VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when F-VPP VPPH1/2 or VPPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) be masked out when polling the status register. L R S1 3 8 6 14 R 15 SMS 7 R 14 R 6 R 13 R 5 Extended Status Register Definition R R 12 R 4 Notes: 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0 XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) After issue a Page Buffer Program command (E8H), XSR.7=1 indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register. L R S1 3 8 6 15 R 15 R 7 R 14 R 6 R 13 R 5 Partition Configuration Register Definition R R PC2 12 R 4 11 R 3 10 R 2 PC1 9 R 1 PC0 8 R 0 PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) Notes: 011 = Plane 2-3 are merged into one partition. There are 1. After power-up or device reset, PCR10-8 (PC2-0) is set three partitions in this configuration. Dual work to "001" in a bottom parameter device and "100" in a top operation is available between any two partitions. parameter device. 110 = Plane 0-1 are merged into one partition. There are 2. See the table below for more details. three partitions in this configuration. Dual work 3. PCR.15-11 and PCR.7-0 bits are reserved for future use. operation is available between any two partitions. If these bits are read via the Read Identifier Codes/OTP 101 = Plane 1-2 are merged into one partition. There are command, the device may output "1" or "0" on these bits. three partitions in this configuration. Dual work operation is available between any two partitions. Partition Configuration 111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. L R S1 3 8 6 16 7. Memory Map for Flash Memory L R S1 3 8 6 17 8. Absolute Maximum Ratings Symbol VCC VIN TA TSTG F-VPP Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. -2.0V undershoot and VCC +2.0V overshoot are allowed when the pulse width is less than 20 nsec. 4. VIN should not be over VCC +0.3V. 5. Applying 12V ±0.3V to F-VPP during erase/write can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V ±0.3V for total of 80 hours maximum. +12.6V overshoot is allowed when the pulse width is less than 20 nsec. 9. Recommended DC Operating Conditions (TA = -25°C to +85°C) Symbol VCC VIH VIL Notes: 1. VCC is the lower of F-VCC or S-VCC. 2. VCC is the higher of F-VCC or S-VCC. 3. VCC includes both F-VCC and S-VCC. 10. Pin Capacitance(1) (TA = 25°C, f = 1MHz) Symbol CIN CI/O Note: 1. Sampled but not 100% tested. Parameter Input capacitance I/O capacitance Notes Min. Typ. Max. 15 25 Unit pF pF Condition VIN = 0V VI/O = 0V Parameter Supply Voltage Input Voltage Input Voltage Notes 3 Min. 2.7 VCC -0.4 (2) -0.2 Typ. 3.0 Max. 3.3 VCC +0.2 (1) 0.4 Unit V V V Parameter Supply voltage Input voltage Operating temperature Storage temperature F-VPP voltage 1,3,5 Notes 1,2 1,2,3,4 -0.2 -0.2 -25 -55 -0.2 Ratings to to to to to +3.9 VCC +0.3 +85 +125 +12.6 Unit V V °C °C V L R S1 3 8 6 18 11. DC Electrical Characteristics(1) DC Electrical Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.3V) Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current F-VCC Standby Current 2 4 Notes Min. Typ. Max. ±2 ±2 20 Unit A A A Test Conditions VIN = VCC or GND VOUT = VCC or GND F-VCC = F-VCC Max., F-CE = F-RST = F-VCC ±0.2V, F-WP = F-VCC or GND F-VCC = F-VCC Max., F-CE = GND ±0.2V, F-WP = F-VCC or GND F-RST = GND ±0.2V IOUT (F-RY/BY) = 0mA ICCAS F-VCC Automatic Power Savings Current F-VCC Reset Power-Down Current Average F-VCC Read Current Normal Mode Average F-VCC 8 Word Read Read Current Page Mode F-VCC (Page Buffer) Program Current F-VCC Block Erase, Full Chip Erase Current F-VCC (Page Buffer) Program or Block Erase Suspend Current F-VPP Standby or Read Current F-VPP (Page Buffer) Program Current F-VPP Block Erase, Full Chip Erase Current F-VPP (Page Buffer) Program Suspend Current F-VPP Block Erase Suspend Current 2,5 4 20 A ICCD 2 4 20 A 2 15 25 mA ICCR 2 2,6 2,6 2,6 2,6 2,3 2,7 2,6,7 2,6,7 2,6,7 2,6,7 2,7 2,7 2,7 2,7 5 20 10 10 5 10 2 2 10 2 5 2 10 2 10 10 60 20 30 15 200 5 5 30 5 15 5 200 5 200 mA mA mA mA mA A A A mA A mA A A A A F-VCC = F-VCC Max., F-CE = VIL, F-OE = VIH , f = 5MHz IOUT = 0mA ICCW ICCE ICCWS ICCES IPPS IPPR IPPW IPPE IPPWS F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-CE = VIH F-VPP F-VCC F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 IPPES L R S1 3 8 6 19 DC Electrical Characteristics (Continue) (TA = -25°C to +85°C, VCC = 2.7V to 3.3V) Symbol ISB ISB1 ICC1 Parameter S-VCC Standby Current S-VCC Standby Current S-VCC Operation Current Notes Min. Typ. (1) Max. 2 25 3 50 Unit µA mA Conditions S-CE1, S-CE2 S-CE2 0.2V S-CE2 = VIL tCYCLE = Min II/O = 0mA S-VCC - 0.2V or S-CE1 = VIL, mA S-CE2 = VIH VIN = VIL or VIH mA V V V V IOL = 0.5mA IOH = -0.5mA ICC2 VIL VIH VOL VOH VPPLK VPPH1 VPPH2 VLKO S-VCC Operation Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lockout during Normal Operations F-VPP during Block Erase, Full Chip Erase, Word Write or Lock-Bit configuration Operations F-VCC Lockout Voltage 6 6 6 6 4,6,7 1.65 7 11.7 1.5 3 12 VCC -0.2 -0.2 VCC -0.4 8 0.4 VCC +0.2 0.4 S-CE1 0.2V, S-CE S-VCC -0.2V, tCYCLE = 1µA II/O = 0mA VIN S-VCC -0.2V or 0.2V 0.4 3.3 12.3 V V V V Notes: 1. VCC includes both F-VCC and S-VCC. 2. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25 C. 3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 4. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when F-VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.) , between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.). 5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 6. Sampled, not 100% tested. 7. F-VPP is not used for power supply pin. With F-VPP VPPLK, block erase, full chip erase, (page buffer) program and OTP program cannot be executed and should not be attempted. Applying 12V ±0.3V to F-VPP provides fast erasing or fast programming mode. In this mode, F-VPP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V ±0.3V to F-VPP during erase/program can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V ±0.3V for a total of 80 hours maximum. L R S1 3 8 6 20 12. AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH Note: 1. Sampled, not 100% tested. 2. F-OE may be delayed up to tELQV tGLQV after the falling edge of F-CE without impact to tELQV. Read Cycle Time Address to Output Delay F-CE to Output Delay Page Address Access Time F-OE to Output Delay F-RST High to Output Delay F-CE or F-OE to Output in High - Z, Whichever Occurs First F-CE to Output in Low - Z F-OE to Output in Low - Z Output Hold from First Occurring Address, F-CE or F-OE change 1 1 1 1 0 0 0 2 2 Parameter Notes Min. 90 90 90 35 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns 0 V to 2.7 V 5 ns 1.35 V 1TTL + CL (50pF) L R S1 3 8 6 21 12.3 Write Cycle (F-WE / F-CE Controlled)(1,2) (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol tPHWL (tPHEL) tELWL (tWLEL) Parameter F-RST High Recovery to F-WE (F-CE) Going Low F-CE (F-WE) Setup to F-WE (F-CE) Going Low Notes 3 4 4 8 8 Min. 150 0 60 40 50 0 0 0 5 3 3 30 0 200 30 3, 6 3, 6 3, 7 3 0 0 tAVQV+50 100 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWLWH (tELEH) F-WE (F-CE) Pulse Width tDVWH (tDVEH) Data Setup to F-WE (F-CE) Going High tAVWH (tAVEH) Address Setup to F-WE (F-CE) Going High tWHEH (tEHWH) F-CE (F-WE) Hold from F-WE (F-CE) High tWHDX (tEHDX) Data Hold from F-WE (F-CE) High tWHAX (tEHAX) Address Hold from F-WE (F-CE) High tWHWL (tEHEL) F-WE (F-CE) Pulse Width High tSHWH (tSHEH) F-WP High Setup to F-WE (F-CE) Going High tVVWH (tVVEH) F-VPP Setup to F-WE (F-CE) Going High tWHGL (tEHGL) Write Recovery before Read tQVSL tQVVL tWHR0 (tEHR0) F-WP High Hold from Valid SRD, F-RY/BY High - Z F-VPP Hold from Valid SRD, F-RY/BY High - Z F-WE (F-CE) High to SR.7 Going "0" tWHRL (tEHRL) F-WE (F-CE) High to F-RY/BY Going Low Notes: 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. See the AC Characteristics for read cycle. 2. A write operation can be initiated and terminated with either F-CE or F-WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of F-CE or F-WE (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH . 5. Write pulse width high (tWPH) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling edge of F-CE or F-WE (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. F-VPP should be held at F-VPP=VPPH1/2 until determination of block erase, full chip erase, (page buffer) program or OTP program success (SR.1/3/4/5=0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration. L R S1 3 8 6 22 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(4) (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Page Buffer Command Notes is Used or not Used 2 2, 3 2 2, 3 2 2, 3 2 2 2 5 5 Not Used Used Not Used Used Not Used Used Not Used F-VPP=VPPH1 (In System) Min. Typ. (1) Symbol Parameter F-VPP=VPPH2 (In Manufacturing) (2) Unit (2) Max. Min. Typ. (1) Max. tWPB tWMB 4K-Word Parameter Block Program Time 32K-Word Main Block Program Time 0.05 0.03 0.38 0.24 11 7 36 0.3 0.6 5 5 0.3 0.12 2.4 1 200 100 400 4 5 10 20 0.04 0.02 0.31 0.17 9 5 27 0.2 0.5 5 5 0.12 0.06 1 0.5 185 90 185 4 5 10 20 s s s s s s s s s s s tWHQV1/ Word Program Time tEHQV1 tWHOV1/ OTP Program Time tEHOV1 tWHQV2/ 4K-Word Parameter Block tEHQV2 Erase Time tWHQV3/ 32K-Word Main Block tEHQV3 Erase Time tWHRH1/ (Page Buffer) Program Suspend tEHRH1 Latency Time to Read tWHRH2/ Block Erase Suspend tEHRH2 Latency Time to Read tERES Notes: Latency Time from Block Erase Resume Command to Block Erase Suspend Command 6 - 500 500 s 1. Typical values measured at TA=+25 C and nominal voltages. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Every 16 words data are loaded alternatively into 2 page buffers. 4. Sampled, but not 100% tested. 5. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going "1"or F-RY/BY going High-Z. 6. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. L R S1 3 8 6 23 12.5 Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code L R S1 3 8 6 24 AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks L R S1 3 8 6 25 AC Waveform for Write Operations(F-WE / F-CE Controlled) L R S1 3 8 6 26 12.6 Reset Operations (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol tPLPH tPLRH tVPH tVHQV Parameter F-RST Low to Reset during Read (F-RST should be low during power-up.) F-RST Low to Reset during Erase or Program F-VCC 2.7V to F-RST High F-VCC 2.7V to Output Delay Notes 1, 2, 3 1, 3, 4 1, 3, 5 3 100 1 Min. 100 22 Max. Unit ns s ns ms Notes: 1. A reset time, tPHQV, is required from the later of SR.7(F-RY/BY) going "1"(High-Z) or F-RST going high until outputs are valid. See the AC Characteristics - read cycle for t PHQV. 2. 4. tPLPH is