LZ21N3VS

LZ21N3V/VS LZ21N3V/VS DESCRIPTION The LZ21N3V/VS are 1/2-type (8.08 mm) solidstate image sensors that consist of PN photodiodes and CCDs (charge-coupled devices). With approximately 2 140 000 pixels (1 704 horizontal x 1 255 vertical), the sensor provides a stable highresolution color image. 1/2-type Interline Color CCD Area Sensors with 2 140 k Pixels PIN CONNECTIONS 20-PIN HALF-PITCH WDIP 20-PIN HALF-PITCH WSOP TOP VIEW OD 1 GND 2 OFD 3 PW 4 ØRS 5 NC1 6 NC2 7 ØH1 8 NC3 9 ØH2 10 20 OS 19 GND 18 NC5 17 NC4 16 ØV1A 15 ØV1B 14 ØV2 13 ØV3A 12 ØV3B 11 ØV4 FEATURES • • • • • Optical size : 8.08 mm (aspect ratio 4 : 3) Interline scan format Square pixel Number of effective pixels : 1 650 (H) x 1 250 (V) Number of optical black pixels – Horizontal : 2 front and 52 rear – Vertical : 3 front and 2 rear Number of dummy bits – Horizontal : 28 – Vertical : 2 Pixel pitch : 3.95 µm (H) x 3.95 µm (V) R, G, and B primary color mosaic filters Supports monitoring mode Low fixed-pattern noise and lag No burn-in and no image distortion Blooming suppression structure Built-in output amplifier Built-in overflow drain voltage circuit and reset gate voltage circuit Variable electronic shutter Packages – LZ21N3V : 20-pin half-pitch WDIP [Plastic] (WDIP020-P-0500) Row space : 12.20 mm – LZ21N3VS : 20-pin half-pitch WSOP [Plastic] (WSOP020-P-0525) • • • • • • • • • • • (WDIP020-P-0500) (WSOP020-P-0525) PRECAUTIONS • The exit pupil position of lens should be 30 to 50 mm from the top surface of the CCD. • Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details. COMPARISON TABLE Package LZ21N3V 20-pin half-pitch WDIP LZ21N3VS 20-pin half-pitch WSOP In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LZ21N3V/VS PIN DESCRIPTION SYMBOL OD OS ØRS ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 ØH1, ØH2 OFD PW GND NC1, NC2, NC3, NC4, NC5 PIN NAME Output transistor drain Output signals Reset transistor clock Vertical shift register clock Horizontal shift register clock Overflow drain P-well Ground No connection ABSOLUTE MAXIMUM RATINGS PARAMETER Output transistor drain voltage Overflow drain voltage Reset gate clock voltage Vertical shift register clock voltage Horizontal shift register clock voltage Voltage difference between P-well and vertical clock Voltage difference between vertical clocks Storage temperature Ambient operating temperature SYMBOL VOD VOFD VØRS VØV VØH VPW-VØV VØV-VØV TSTG TOPR RATING 0 to +15 Internal output Internal output VPW to +15 –0.3 to +12 –24 to 0 0 to +15 –40 to +85 –20 to +70 (TA = +25 ˚C) UNIT V V V V V V V ˚C ˚C 3 NOTE 1 2 NOTES : 1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 22 Vp-p. 2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p. 3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 22 V. 2 LZ21N3V/VS RECOMMENDED OPERATING CONDITIONS PARAMETER Ambient operating temperature Output transistor drain voltage Overflow drain clock p-p level Ground P-well voltage LOW level Vertical shift register clock INTERMEDIATE level HIGH level Horizontal shift register clock LOW level HIGH level SYMBOL TOPR VOD VØOFD GND VPW VØV1AL, VØV1BL, VØV2L VØV3AL, VØV3BL, VØV4L VØV1AI, VØV1BI, VØV2I VØV3AI, VØV3BI, VØV4I VØV1AH, VØV1BH VØV3AH, VØV3BH VØH1L, VØH2L VØH1H, VØH2H VØRS fØV1A, fØV1B, fØV2 fØV3A, fØV3B, fØV4 fØH1, fØH2 fØRS MIN. 12.5 18.6 –8.0 –7.35 –7.0 0.0 12.5 –0.05 4.5 4.5 13.0 0.0 4.8 4.8 7.87 17.94 17.94 13.5 0.05 5.5 5.5 TYP. 25.0 13.0 19.5 0.0 VØVL –6.65 MAX. 13.5 20.9 UNIT ˚C V V V V V V V V V V kHz MHz MHz 1 1 2 NOTE Reset gate clock p-p level Vertical shift register clock frequency Horizontal shift register clock frequency Reset gate clock frequency NOTES : 1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly. 2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected to VL of V driver IC. * To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on PW first and then turn on other powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied. 3 LZ21N3V/VS CHARACTERISTICS (Drive method : 1/30 s frame accumulation) (TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS". Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.) PARAMETER Standard output voltage Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity (green channel) Smear ratio Image lag Blooming suppression ratio Output transistor drain current SYMBOL VO PRNU VSAT VDARK DSNU R SMR AI ABL IOD 1 000 4.0 8.0 mA 140 450 320 530 400 0.5 0.5 180 –89 3.0 2.0 –82 1.0 MIN. TYP. 150 MAX. 10 UNIT mV % mV mV mV mV mV dB % NOTE 2 3 4 5 1, 6 1, 7 8 9 10 11 NOTES : • Within the recommended operating conditions of VOD, VOFD of the internal output satisfies with ABL larger than 1 000 times exposure of the standard exposure conditions, and VSAT larger than 320 mV. 1. TA = +60 ˚C 2. The average output voltage of G signal under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV. 3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax – Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively. 4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is high. (for still image capturing) 5. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is low. 6. The average output voltage under non-exposure conditions. 7. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively. 8. The average output voltage of G signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm. 9. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square. 10. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 4 LZ21N3V/VS PIXEL STRUCTURE OPTICAL BLACK (2 PIXELS) OPTICAL BLACK (2 PIXELS) 1 650 (H) x 1 250 (V) OPTICAL BLACK (52 PIXELS) 1 pin OPTICAL BLACK (3 PIXELS) COLOR FILTER ARRAY (1, 1 250) (1 650, 1 250) GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG GBGBGBGBGB RGRGRGRGRG (1 650, 1) Pin arrangement of the vertical readout clock ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3A G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1A R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3A G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G ØV3B G B G B G B G B G B ØV1A R G R G R G R G R G ØV3B G B G B G B G B G B ØV1B R G R G R G R G R G (1, 1) 5 LZ21N3V/VS TIMING CHART TIMING CHART EXAMPLE Pulse diagram in more detail is shown in figures q to t after the next page. Field accumulation mode q q' q Frame accumulation Frame accumulation mode mode at first w e r Field accumulation Field accumulation mode at first mode t q q' 263 VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 ØOFD 525 1 263 525 1 656 1 656 1 656 1 263 525 1 (at OFD shutter operation) OFDC OS (Number of vertical line) Field accumulation mode (3, 8, 13,..) (3, 8, 13,..) (3, 8, 13,..) Not for use (NOTE 1) Frame accumulation mode (1, 3, ..., 1247, 1249) (2, 4, ..., 1248, 1250) (NOTE Not for use Field accumulation 2) mode (3, 8, 13,..) NOTES : 1. Do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. Do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * Apply at least an OFD shutter pulse to OFD in each field accumulation mode. 6 LZ21N3V/VS q VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡ Shutter speed 1/30 s 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 1203 1213 1223 1233 1243 1198 1208 1218 1228 1238 1248 GB RG GB RG GB RG GB RG GB RG GB OB1 3 8 13 18 RG GB RG GB q' VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡ 519 520 521 522 523 524 525 1 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD 1193 1203 1213 1223 1233 1243 1198 1208 1218 1228 1238 1248 RG GB RG GB RG GB RG GB RG GB RG GB 2 3 4 5 6 7 8 9 Shutter speed 1/30 s 10 11 12 13 14 15 16 17 18 19 20 21 OB1 OS 3 8 13 18 RG GB RG GB 7 LZ21N3V/VS w VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE AT FIRST¡ 519 520 521 522 523 524 525 1 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 1198 1208 1218 1228 1238 1248 1193 1203 1213 1223 1233 1243 RG GB RG GB RG GB RG GB RG GB RG GB 2 3 4 5 6 7 8 9 Shutter speed 1/15 s 10 11 12 13 14 15 16 17 18 19 20 21 Not for use * Do not use the frame signals immediately after accumulation mode is transferred to frame accumulation mode. e VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ 618 619 620 621 622 623 624 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Charge swept transfer (1 368 stages) OFDC ØOFD OB2 1 3 5 … … 655 656 1 2… 9 10 11 12 13 14 15 16 17 18 19 20 21 OS Not for use RG RG RG * Do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. 8 LZ21N3V/VS r VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ 638 639 640 641 642 643 644 645 646 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B … 656 1 2… 9 10 11 12 13 14 15 16 17 18 19 20 21 ØV4 Charge swept transfer (684 stages) OFDC ØOFD 1241 1245 1249 1243 1247 OB1 RG RG RG RG RG OB1 OB3 OS 2 4 GB GB Not for use t VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE AT FIRST¡ 640 641 642 643 644 … 656 1 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 1246 1250 1244 1248 OB2 GB GB GB GB 2 3 4 5 6 7 8 Shutter speed 1/15 s 9 10 11 12 13 14 15 16 17 18 19 20 21 9 LZ21N3V/VS READOUT TIMING ¿FIELD ACCUMULATION MODE¡ 2280, 1 HD ØV1A ØV1B 172 292 ØV2 ØV3A ØV3B ØV4 132 332 40.9 µs (732 bits) 58.8 µs (1 052 bits) 972 6.7 µs (120 bits) 6.7 µs (120 bits) 332 52 252 1052 1172 892 1012 292 252 228 92 212 732 852 932 2280, 1 228 212 * Keep over 2.2 µs when vertical transfer clock pulse is overlapping. e 2280, 1 HD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 52 252 132 332 228 92 212 172 292 READOUT TIMING ¿FRAME ACCUMULATION MODE¡ 2280, 1 732 852 932 1012 892 972 6.7 µs (120 bits) 2280, 1 932 1012 1052 1172 892 972 6.7 µs 58.8 µs (1 052 bits) (120 bits) 228 212 292 252 332 228 212 292 252 332 40.9 µs (732 bits) r 2280, 1 HD 228 92 212 172 292 52 252 132 332 ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 * Keep over 2.2 µs when vertical transfer clock pulse is overlapping. 10 LZ21N3V/VS HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-1 HD ØH1 ØH2 ØRS OS πππ1650 OB (52) 40 clk (= 2.2 µs) 2280, 1 52 92 132 172 212 1 clk = 55.8 ns (= 1/17.9 MHz) 228 252 292 332 Double transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Triple transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 192 OFD 272 11 LZ21N3V/VS HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-2 332 HD ØH1 ØH2 ØRS 372 412 452 492 532 572 1 clk = 55.8 ns (= 1/17.9 MHz) 600 OS Double transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 PRE SCAN (28) OB (2) OUTPUT (1 650) 1πππππππ Triple transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFD 12 LZ21N3V/VS HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-1 2280, 1 HD ØH1 ØH2 ØRS OS ..1650 OB (52) 40 clk (= 2.2 µs) 52 92 132 172 212 1 clk = 55.8 ns (= 1/17.9 MHz) 228 252 292 332 Standard transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 192 OFD 272 HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-2 332 HD ØH1 ØH2 ØRS OS PRE SCAN (28) OB (2) OUTPUT (1 650) 1ππππππππ 372 412 452 492 532 572 1 clk = 55.8 ns (= 1/17.9 MHz) 600 Standard transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFD 13 LZ21N3V/VS CHARGE SWEPT TRANSFER TIMING ¿e¡ 621H 1 HD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 1 2 3 4 ••••••• 622H 623H 228 ••••• 655H 656H 1H 2H 3H ••••• 11H 12H 13H 2 42 82 122 162 22 62 102 142 2 42 82 122 162 22 62 102 142 1366 1367 2242 2262 2242 2262 1368 * Keep over 1.1 µs when vertical transfer clock pulse of charge swept transfer is overlapping. CHARGE SWEPT TRANSFER TIMING ¿r¡ 645H 1 HD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 1 2 3 4 ••••••• 646H 647H 228 ••••• 655H 656H 1H 2H 3H ••••• 11H 12H 13H 2 42 82 122 162 22 62 102 142 2 42 82 122 162 22 62 102 142 682 683 2242 2262 2242 2262 684 * Keep over 1.1 µs when vertical transfer clock pulse of charge swept transfer is overlapping. 14 VOD + 47 k$ 33 k$ + 100 $ 100 k$ 270 pF 1 M$ 1.0 µF 0. 1 µF OFDC 5.6 k$ VL (VPW) ØRS ØH1 0.01 µF 1 M$ ØH2 SYSTEM CONFIGURATION EXAMPLE VH V4 V2 VL ØRS V1A V1B V3A V3B ØH2 ØH1 OFD NC3 NC2 NC1 POFD GND VMa NC VMb OD PW VH + 15 9 8 7 6 5 4 3 2 1 10 9 12 11 10 8 7 6 5 (*1) 4 3 (*1) 2 1 LR36685 ØV4 V4X V3X V1X V2X VDD ØV3B GND VOFDH VH3AX VH1AX VH3BX OFDX + LZ21N3V 11 12 13 14 15 16 17 18 19 20 OS NC4 NC5 ØV2 ØV3A ØV1B ØV1A GND 13 14 15 16 17 18 19 20 21 22 23 24 VH1BX VH1BX V4X VH3AX CCD OUT +VDD V3X VH1AX V1X V2X OFDX VH3BX LZ21N3V/VS (*1) ØRS, OFD : Use the circuit parameter indicated in this circuit example, and do not connect to DC voltage directly. PACKAGES FOR CCD AND CMOS DEVICES PACKAGES 20 WDIP (WDIP020-P-0500) 6.90±0.075 0.40±0.40 20 6.00±0.075 0.40±0.40 11 Center of effective imaging area and center of package (Unit : mm) ¬ 11.20±0.10 (◊2) 12.00±0.10 CCD Rotation error of die : ¬ = 1.0˚MAX. (◊ 1 : Effective imaging area) (◊ 2 : Lid's size) 1 13.00±0.10 (◊2) 13.80 2.40±0.10 ±0.10 10 12.20±0.10 Refractive index : nd = 1.5 0.02 (◊1) A 3.50±0.10 Glass Lid ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, CCD ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, Package ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A 0.50±0.05 (◊2) 1.41±0.05 2.90±0.10 A' 0.04 0.02 (◊1) 12.20–0 +0.30 0.30TYP. 0.64TYP. A' P-1.27TYP. 0.20 M 0.25±0.10 20 WSOP (WSOP020-P-0525) 6.90±0.075 0.40±0.40 20 0.40±0.40 11 Center of effective imaging area and center of package (1.00) 11.20±0.10 (◊2) 12.00±0.10 14.00±0.10 6.00±0.075 ¬ CCD Rotation error of die : ¬ = 1.0˚MAX. (◊ 1 : Effective imaging area) (◊ 2 : Lid's size) 13.00±0.10 (◊2) 13.80±0.10 (1.00) 1 10 12.20±0.10 Refractive index : nd = 1.5 0.02 (◊1) A ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, , CCD ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, Package ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 2.40±0.10 A 1.00±0.10 2.90±0.10 Glass Lid 0.50±0.05 (◊2) 1.41±0.05 1-5˚ 0.25±0.10 A' 0.83 0.04 0.02 (◊1) A' 0.30TYP. 0.64TYP. 0.20 M P-1.27TYP. 0.10 16 PRECAUTIONS FOR CCD AREA SENSORS PRECAUTIONS FOR CCD AREA SENSORS 1. Package Breakage In order to prevent the package from being broken, observe the following instructions : 1) The CCD is a precise optical component and the package material is ceramic or plastic. Therefore, ø Take care not to drop the device when mounting, handling, or transporting. ø Avoid giving a shock to the package. Especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn’t fixed. 2) When applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. In addition, when applying force, do it at a point below the stand-off part. (In the case of ceramic packages) – The leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. Low melting point glass Lead (In the case of plastic packages) – The leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. Glass cap Package Lead Fixed Stand-off 3) When mounting the package on the housing, be sure that the package is not bent. – If a bent package is forced into place between a hard plate or the like, the package may be broken. 4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore, ø Do not hit the glass cap. ø Do not give a shock large enough to cause distortion. ø Do not scrub or scratch the glass surface. – Even a soft cloth or applicator, if dry, could cause dust to scratch the glass. 2. Electrostatic Damage Fixed Stand-off As compared with general MOS-LSI, CCD has lower ESD. Therefore, take the following anti-static measures when handling the CCD : 1) Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 M$ between the human body and the ground to be on the safe side. 2) When directly handling the device with the fingers, hold the part without leads and do not touch any lead. 17 PRECAUTIONS FOR CCD AREA SENSORS 3) To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dustcleaning tape. 4) When storing or transporting the device, put it in a container of conductive material. ø The contamination on the glass surface should be wiped off with a clean applicator soaked in Isopropyl alcohol. Wipe slowly and gently in one direction only. – Frequently replace the applicator and do not use the same applicator to clean more than one device. ◊ Note : In most cases, dust and contamination are unavoidable, even before the device is first used. It is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 3. Dust and Contamination Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. In order to minimize dust or contamination on the glass surface, take the following precautions : 1) Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be, if possible, class 1 000 at least.) 2) Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended : ø Dust from static electricity should be blown off with an ionized air blower. For antielectrostatic measures, however, ground all the leads on the device before blowing off the dust. 4. Other 1) Soldering should be manually performed within 5 seconds at 350 °C maximum at soldering iron. 2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD. 3) Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters. 18