LZ23J3V

Back LZ23J3V LZ23J3V DESCRIPTION The LZ23J3V is a 1/2.7-type (6.72 mm) solid-state image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices). With approximately 1 310 000 pixels (1 344 horizontal x 971 vertical), the sensor provides a stable highresolution color image. 1/2.7-type Interline Color CCD Area Sensor with 1 310 k Pixels PIN CONNECTIONS 16-PIN SHRINK-PITCH WDIP TOP VIEW OD 1 GND 2 OFD 3 16 OS 15 GND 14 ØV1A 13 ØV1B 12 ØV2 11 ØV3A 10 ØV3B 9 ØV4 FEATURES • • • • • Optical size : 6.72 mm (aspect ratio 4 : 3) Interline scan format Square pixel Number of effective pixels : 1 292 (H) x 966 (V) Number of optical black pixels – Horizontal : 3 front and 49 rear – Vertical : 3 front and 2 rear Number of dummy bits – Horizontal : 28 – Vertical : 2 Pixel pitch : 4.2 µm (H) x 4.2 µm (V) R, G, and B primary color mosaic filters Supports monitoring mode Low fixed-pattern noise and lag No burn-in and no image distortion Blooming suppression structure Built-in output amplifier Built-in overflow drain voltage circuit and reset gate voltage circuit Variable electronic shutter Package : 16-pin shrink-pitch WDIP [Plastic] (WDIP016-P-0500C) Row space : 12.70 mm PW 4 ØRS 5 NC 6 ØH1 7 ØH2 8 • (WDIP016-P-0500C) • • • • • • • • • • PRECAUTIONS • The exit pupil position of lens should be 15 to 50 mm from the top surface of the CCD. • Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LZ23J3V PIN DESCRIPTION SYMBOL OD OS ØRS ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 ØH1, ØH2 OFD PW GND NC Output transistor drain Output signals Reset transistor clock Vertical shift register clock Horizontal shift register clock Overflow drain P-well Ground No connection PIN NAME ABSOLUTE MAXIMUM RATINGS PARAMETER Output transistor drain voltage Overflow drain voltage Reset gate clock voltage Vertical shift register clock voltage Horizontal shift register clock voltage Voltage difference between P-well and vertical clock Voltage difference between vertical clocks Storage temperature Ambient operating temperature SYMBOL VOD VOFD VØRS VØV VØH VPW-VØV VØV-VØV TSTG TOPR RATING 0 to +18 Internal output Internal output VPW to +18 –0.3 to +12 –29 to 0 0 to +17 –40 to +85 –20 to +70 (TA = +25 ˚C) UNIT V V V V V V V ˚C ˚C 3 NOTE 1 2 NOTES : 1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 33 Vp-p. 2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p. 3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 V. 2 LZ23J3V RECOMMENDED OPERATING CONDITIONS PARAMETER Ambient operating temperature Output transistor drain voltage Overflow drain clock p-p level Ground P-well voltage LOW level Vertical shift register clock INTERMEDIATE level HIGH level Horizontal shift register clock LOW level HIGH level SYMBOL TOPR VOD VØOFD GND VPW VØV1AL, VØV1BL, VØV2L VØV3AL, VØV3BL, VØV4L VØV1AI, VØV1BI, VØV2I VØV3AI, VØV3BI, VØV4I VØV1AH, VØV1BH VØV3AH, VØV3BH VØH1L, VØH2L VØH1H, VØH2H VØRS fØV1A, fØV1B, fØV2 fØV3A, fØV3B, fØV4 fØH1, fØH2 fØRS MIN. 15.0 28.0 –10.0 –8.5 –8.0 0.0 15.0 –0.05 4.5 4.5 15.5 0.0 5.0 5.0 7.87 12.27 12.27 16.0 0.05 5.5 5.5 TYP. 25.0 15.5 30.0 0.0 VØVL –7.5 MAX. 16.0 32.0 UNIT ˚C V V V V V V V V V V kHz MHz MHz 1 1 2 NOTE Reset gate clock p-p level Vertical shift register clock frequency Horizontal shift register clock frequency Reset gate clock frequency NOTES : 1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly. 2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected to VL of V driver IC. * To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on PW first and then turn on other powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied. 3 LZ23J3V CHARACTERISTICS (Drive method : 1/30 s frame accumulation) (TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS". Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.) PARAMETER Standard output voltage Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity (green channel) Smear ratio Image lag Blooming suppression ratio Output transistor drain current SYMBOL VO PRNU VSAT VDARK DSNU R SMR AI ABL IOD 500 4.0 8.0 mA 140 470 340 550 420 0.5 0.5 200 –75 3.0 2.0 –65 1.0 MIN. TYP. 150 MAX. 10 UNIT mV % mV mV mV mV mV dB % NOTE 2 3 4 5 1, 6 1, 7 8 9 10 11 NOTES : • Within the recommended operating conditions of VOD, VOFD of the internal output satisfies with ABL larger than 500 times exposure of the standard exposure conditions, and VSAT larger than 340 mV. 1. TA = +60 ˚C 2. The average output voltage of G signal under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV. 3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax – Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively. 4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is high. (for still image capturing) 5. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is low. 6. The average output voltage under non-exposure conditions. 7. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively. 8. The average output voltage of G signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm. 9. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square. 10. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 4 LZ23J3V PIXEL STRUCTURE OPTICAL BLACK (3 PIXELS) yyyyyyyyy ,,,,,,,,, yyyyyyyyy ,,,,,,,,, yyyyyyyyy ,,,,,,,,, yyyyyyyyy ,,,,,,,,, yyyyyyyyy ,,,,,,,,, ,,,,,,,,, yyyyyyyyy ,,,,,,,,, yyyyyyyyy OPTICAL BLACK (2 PIXELS) 1 292 (H) x 966 (V) 1 pin OPTICAL BLACK (3 PIXELS) OPTICAL BLACK (49 PIXELS) COLOR FILTER ARRAY (1, 966) (1 292, 966) Pin arrangement of the vertical readout clock ØV3A ØV1B ØV3B ØV1A ØV3A ØV1B G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G ØV3A ØV1B ØV3B ØV1A ØV3A ØV1B (1, 1) G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G (1 292, 1) 5 LZ23J3V TIMING CHART TIMING CHART EXAMPLE Pulse diagram in more detail is shown in figures q to r after the next page. Field accumulation mode Frame accumulation Frame accumulation mode mode at first q q w e r Field accumulation mode at first q' Field accumulation mode q 525 1 VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 ØOFD (at OFD shutter operation) 525 1 525 1 525 1 525 1 525 1 525 1 OFDC OS (Number of vertical line) Field accumulation mode (2, 3, 6, ..) (2, 3, 6, ..) Not for use (NOTE 1) Frame accumulation mode (1, 4, ..., 964, 965) (2, 3, ..., 963, 966) Not for use (NOTE 2) Field accumulation mode (2, 3, 6, ..) NOTES : 1. Do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. Do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * Start the exposure period after 10 ms later that OFDC is high, and finish before charge swept transfer. * Apply at least an OFD shutter pulse to OFD in each field accumulation mode. q VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡ Shutter speed 503 504 505 506 507 508 509 510 511 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 963 966 OB1 RG GB OB1 OB2 2 3 6 7 GB RG GB RG ... 525 1 ... 8 1/15 s 9 10 11 12 ... 18 19 20 21 22 23 24 25 6 LZ23J3V w VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE AT FIRST¡ 503 504 505 506 507 508 509 510 511 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 963 966 OB1 RG GB ... 525 1 ... 8 Shutter speed 1/15 s 9 10 11 12 ... 18 19 20 21 22 23 24 25 Not for use * Do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. e VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ 503 504 505 506 507 508 509 510 511 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Charge swept transfer (780 stages) OFDC ØOFD OB3 ... 525 1 ... 8 9 10 11 12 ... 18 19 20 21 22 23 24 25 OS Not for use 1 4 5 8 GB RG GB RG * Do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. 7 LZ23J3V r VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ 503 504 505 506 507 508 509 510 511 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Charge swept transfer (780 stages) OFDC ØOFD OS 964 965 OB2 RG GB OB1 OB2 2 3 6 7 GB RG GB RG ... 525 1 ... 8 9 10 11 12 ... 18 19 20 21 22 23 24 25 Not for use q' VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE AT FIRST¡ 503 504 505 506 507 508 509 510 511 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 963 966 OB1 RG GB ... 525 1 2 ... 9 10 11 12 Shutter speed 1/15 s ... 18 19 20 21 22 23 24 25 Not for use * Do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode. 8 LZ23J3V READOUT TIMING ¿ q , w , r , q ' ¡ 1560, 1 HD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 84 164 452 5.22 µs (64 bits) 644 84 164 100 148 52 132 468 420 628 100 148 52 132 68 116 436 596 676 740 68 116 156 1560, 1 156 500 564 612 40.7 µs (500 bits) 5.22 µs (64 bits) 55.1 µs (676 bits) 127.1 µs (1 560 bits) READOUT TIMING ¿e¡ 1560, 1 HD 68 116 ØV1A 676 740 ØV1B 100 148 ØV2 52 ØV3A 500 564 ØV3B ØV4 84 164 452 5.22 µs (64 bits) 644 84 164 132 420 612 52 132 468 628 100 148 436 596 68 116 156 1560, 1 156 40.7 µs (500 bits) 5.22 µs (64 bits) 55.1 µs (676 bits) 127.1 µs (1 560 bits) 9 LZ23J3V HORIZONTAL TRANSFER TIMING-1 HD ØH1 ØH2 ØRS OS πππππ1292 ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 108 ØOFD 1 clk = 81.5 ns ( = 1/12.27 MHz) 140 52 84 132 OB (49) 68 100 116 148 1560, 1 52 156 HORIZONTAL TRANSFER TIMING-2 156 HD ØH1 ØH2 ØRS OS PRE SCAN (28) OB (3) OUTPUT (1 292) 1ππππππππ ØV1A ØV1B 148 ØV2 ØV3A ØV3B ØV4 140 ØOFD 1 clk = 81.5 ns ( = 1/12.27 MHz) 132 164 240 10 LZ23J3V CHARGE SWEPT TRANSFER TIMING 510H 1 HD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 1 2 3 4 ••••••• 511H 156 512H ••••• 524H 525H 1H 2H 3H ••••• 7H 8H 9H 1560 2 26 50 74 98 14 38 62 86 1538 1550 1538 1550 778 779 780 2 26 50 74 98 14 38 62 86 11 VOD + 18 k$ 5.6 k$ 100 $ 0. 47 µF 270 pF 1 M$ OFDC 0.01 µF 1 M$ ØRS ØH1 ØH2 VL (VPW) + VH SYSTEM CONFIGURATION EXAMPLE + ØRS V1A V1B V3A V3B ØH2 ØH1 OFD GND POFD +3.3 V V3X VH1AX V1X V2X OFDX VH3BX VOFDH + 12 12 11 10 9 8 7 6 5 4 3 2 1 8 13 14 15 16 17 18 19 20 21 22 23 24 V4X + V3X V1X V2X VDD GND VOFDH VH1BX VH3AX VH1AX VH3BX OFDX VMa V4 V2 VL VMb OD PW NC LR36685 9 ØV4 NC VH 7 6 5 (*1) 4 3 (*1) 2 1 LZ23J3V 10 11 12 13 14 15 16 OS ØV2 ØV3A ØV3B ØV1B ØV1A GND VH1BX CCD OUT V4X VH3AX (*1) ØRS, OFD : Use the circuit parameter indicated in this circuit example, and do not connect to DC voltage directly. LZ23J3V PACKAGES FOR CCD AND CMOS DEVICES PACKAGE 16 WDIP (WDIP016-P-0500C) 0.60±0.60 7.00±0.075 1.40±0.60 16 Center of effective imaging area and center of package (◊ : Lid's size) 9 0.04 Glass Lid (Unit : mm) 6.20±0.075 1.66±0.05 11.20±0.10 (◊) CCD Package 0.04 Cross section A-A' θ CCD 1 11.20±0.10 (◊) 14.00±0.10 3.42±0.10 2.60±0.10 A 8 Rotation error of die : θ = 1.0˚MAX. 0.80±0.05 (◊) 2.62±0.10 0.25±0.10 12.70–0 +0.5 5.24MAX. P-1.78TYP. 16-0.46±0.10 12-0.90±0.10 A' 0.25 M 2.63TYP. 1.27±0.25 3.90±0.30 12.40±0.10 13 PRECAUTIONS FOR CCD AREA SENSORS PRECAUTIONS FOR CCD AREA SENSORS 1. Package Breakage In order to prevent the package from being broken, observe the following instructions : 1) The CCD is a precise optical component and the package material is ceramic or plastic. Therefore, ø Take care not to drop the device when mounting, handling, or transporting. ø Avoid giving a shock to the package. Especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn’t fixed. 2) When applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. In addition, when applying force, do it at a point below the stand-off part. (In the case of ceramic packages) – The leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. Low melting point glass Lead (In the case of plastic packages) – The leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. Glass cap Package Lead Fixed Stand-off 3) When mounting the package on the housing, be sure that the package is not bent. – If a bent package is forced into place between a hard plate or the like, the package may be broken. 4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore, ø Do not hit the glass cap. ø Do not give a shock large enough to cause distortion. ø Do not scrub or scratch the glass surface. – Even a soft cloth or applicator, if dry, could cause dust to scratch the glass. 2. Electrostatic Damage Fixed Stand-off As compared with general MOS-LSI, CCD has lower ESD. Therefore, take the following anti-static measures when handling the CCD : 1) Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 M$ between the human body and the ground to be on the safe side. 2) When directly handling the device with the fingers, hold the part without leads and do not touch any lead. 14 PRECAUTIONS FOR CCD AREA SENSORS 3) To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dustcleaning tape. 4) When storing or transporting the device, put it in a container of conductive material. ø The contamination on the glass surface should be wiped off with a clean applicator soaked in Isopropyl alcohol. Wipe slowly and gently in one direction only. – Frequently replace the applicator and do not use the same applicator to clean more than one device. ◊ Note : In most cases, dust and contamination are unavoidable, even before the device is first used. It is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 3. Dust and Contamination Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. In order to minimize dust or contamination on the glass surface, take the following precautions : 1) Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be, if possible, class 1 000 at least.) 2) Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended : ø Dust from static electricity should be blown off with an ionized air blower. For antielectrostatic measures, however, ground all the leads on the device before blowing off the dust. 4. Other 1) Soldering should be manually performed within 5 seconds at 350 °C maximum at soldering iron. 2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD. 3) Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters. 15