BTS650P

PROFET® BTS650P Smart Highside High Current Power Switch Features • Overload protection • Current limitation • Short circuit protection • Overtemperature protection • Overvoltage protection (including load dump) • Clamp of negative voltage at output • Fast deenergizing of inductive loads 1) • Low ohmic inverse current operation • Reverse battery protection • Diagnostic feedback with load current sense • Open load detection via current sense • Loss of Vbb protection2) • Electrostatic discharge (ESD) protection Product Summary Overvoltage protection Output clamp Operating voltage On-state resistance Load current (ISO) Short circuit current limitation Current sense ratio Vbb(AZ) 62 V VON(CL) 42 V Vbb(on) 5.0 ... 34 V RON 6.0 mΩ IL(ISO) 70 A IL(SC) 130 A IL : IIS 14 000 TO-220AB/7 • Power switch with current sense diagnostic feedback for 12 V and 24 V DC grounded loads • Most suitable for loads with high inrush current like lamps and motors; all types of resistive and inductive loads • Replaces electromechanical relays, fuses and discrete circuits Application 7 1 7 Standard SMD 1 General Description N channel vertical power FET with charge pump, current controlled input and diagnostic feedback with load current sense, integrated in Smart SIPMOS® chip on chip technology. Fully protected by embedded protection functions. 4 & Tab Voltage source Overvoltage protection Current limit Gate protection OUT R bb + V bb 1,2,6,7 IL Voltage sensor Charge pump Level shifter Rectifier Limit for unclamped ind. loads Output Voltage detection Current Sense 3 IN Load ESD Logic I IN Temperature sensor IS I IS ® PROFET Load GND VIN V IS Logic GND 5 R IS 1 ) 2) With additional external diode. Additional external diode required for energized inductive loads (see page 9). Semiconductor Group Page 1 of 16 1998-Nov.-2 BTS650P Pin 1 2 3 4 Symbol OUT OUT IN Vbb O O I Function Output to the load. The pins 1,2,6 and 7 must be shorted with each other 3 especially in high current applications! ) Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) Input, activates the power switch in case of short to ground Positive power supply voltage, the tab is electrically connected to this pin. In high current applications the tab should be used for the Vbb connection 4 instead of this pin ). Diagnostic feedback providing a sense current proportional to the load current; zero current on failure (see Truth Table on page 7) Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) Output to the load. The pins 1,2,6 and 7 must be shorted with each other especially in high current applications!3) + 5 6 7 IS OUT OUT S O O Maximum Ratings at Tj = 25 °C unless otherwise specified Parameter Supply voltage (overvoltage protection see page 4) Supply voltage for short circuit protection, Tj,start =-40 ...+150°C: (see diagram on page 10) Load current (short circuit current, see page 5) Load dump protection VLoadDump = VA + Vs, VA = 13.5 V RI5) = 2 Ω, RL = 0.54 Ω, td = 200 ms, IN, IS = open or grounded Operating temperature range Storage temperature range Power dissipation (DC), TC ≤ 25 °C Inductive load switch-off energy dissipation, single pulse Vbb = 12V, Tj,start = 150°C, TC = 150°C const., IL = 20 A, ZL = 7.5 mH, 0 Ω, see diagrams on page 10 Electrostatic discharge capability (ESD) Human Body Model acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993, C = 100 pF, R = 1.5 kΩ Symbol Vbb Vbb Values 42 34 self-limited 75 -40 ...+150 -55 ...+150 170 1.5 4 +15 , -250 +15 , -250 Unit V V A V °C W J kV mA IL VLoad dump6) Tj Tstg Ptot EAS VESD IIN IIS Current through input pin (DC) Current through current sense status pin (DC) see internal circuit diagrams on page 7 and 8 3) 4) 5) 6) Not shorting all outputs will considerably increase the on-state resistance, reduce the peak current capability and decrease the current sense accuracy Otherwise add up to 0.7 mΩ (depending on used length of the pin) to the RON if the pin is used instead of the tab. RI = internal resistance of the load dump test pulse generator. VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839. Semiconductor Group Page 2 1998-Nov.-2 BTS650P Thermal Characteristics Parameter and Conditions Thermal resistance Symbol min --7 chip - case: RthJC ) junction - ambient (free air): RthJA SMD version, device on PCB8): Values typ max -- 0.75 60 -33 Unit K/W Electrical Characteristics Parameter and Conditions at Tj = -40 ... +150 °C, Vbb = 12 V unless otherwise specified Symbol Values min typ max Unit Load Switching Capabilities and Characteristics On-state resistance (Tab to pins 1,2,6,7, see IL = 20 A, Tj = 25 °C: measurement circuit page 7) VIN = 0, IL = 20 A, Tj = 150 °C: IL = 90 A, Tj = 150 °C: 9) Vbb = 6V , IL = 20 A, Tj = 150 °C: Nominal load current10) (Tab to pins 1,2,6,7) ISO 10483-1/6.7: VON = 0.5 V, Tc = 85 °C 11) Nominal load current10), device on PCB8)) TA = 85 °C, Tj ≤ 150 °C VON ≤ 0.5 V, Maximum load current in resistive range (Tab to pins 1,2,6,7) VON = 1.8 V, Tc = 25 °C: see diagram on page 13 VON = 1.8 V, Tc = 150 °C: 12) Turn-on time IIN to 90% VOUT: to 10% VOUT: Turn-off time IIN RL = 1 Ω , Tj =-40...+150°C Slew rate on 12) (10 to 30% VOUT ) RL = 1 Ω , TJ = 25 °C Slew rate off 12) (70 to 40% VOUT ) RL = 1 Ω , TJ = 25 °C RON -- RON(Static) IL(ISO) -55 4.4 7.9 -10 70 6.0 10.5 10.7 17 -- mΩ A IL(NOM) IL(Max) ton toff dV/dton -dV/dtoff 13.6 250 150 100 30 --- 17 ----0.7 1.1 ---420 110 --- A A µs V/µs V/µs 7) 8 Thermal resistance RthCH case to heatsink (about 0.5 ... 0.9 K/W with silicone paste) not included! Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb connection. PCB is vertical without blown air. 9) Decrease of Vbb below 10 V causes slowly a dynamic increase of RON to a higher value of RON(Static). As long as VbIN > VbIN(u) max, RON increase is less than 10 % per second for TJ < 85 °C. 10) Not tested, specified by design. 11) TJ is about 105°C under these conditions. 12) See timing diagram on page 14. ) Semiconductor Group Page 3 1998-Nov.-2 BTS650P Inverse Load Current Operation On-state resistance (Pins 1,2,6,7 to pin 4) VbIN = 12 V, IL = - 20 A Tj = 25 °C: RON(inv) see diagram on page 10 Tj = 150 °C: Nominal inverse load current (Pins 1,2,6,7 to Tab) IL(inv) VON = -0.5 V, Tc = 85 °C11 Drain-source diode voltage (Vout > Vbb) -VON IL = - 20 A, IIN = 0, Tj = +150°C Operating Parameters Operating voltage (VIN = 0) 9, 13) Undervoltage shutdown 14) Undervoltage start of charge pump see diagram page 15 Overvoltage protection15) Tj =-40°C: Ibb = 15 mA Tj = 25...+150°C: Standby current Tj =-40...+25°C: IIN = 0 Tj = 150°C: -55 -- 4.4 7.9 70 0.6 6.0 10.5 --- mΩ A V Vbb(on) VbIN(u) VbIN(ucp) VbIN(Z) Ibb(off) 5.0 1.5 3.0 60 62 --- -3.0 4.5 -66 15 25 34 4.5 6.0 --25 50 V V V V µA ) If the device is turned on before a V -decrease, the operating voltage range is extended down to VbIN(u). bb For all voltages 0 ... 34 V the device is fully protected against overtemperature and short circuit. 14) VbIN = Vbb - VIN see diagram on page 7. When VbIN increases from less than VbIN(u) up to VbIN(ucp) = 5 V (typ.) the charge pump is not active and VOUT ≈Vbb - 3 V. 15) See also VON(CL) in circuit diagram on page 9. 13 Semiconductor Group Page 4 1998-Nov.-2 BTS650P Parameter and Conditions at Tj = -40 ... +150 °C, Vbb = 12 V unless otherwise specified Symbol Values min typ max Unit Protection Functions Short circuit current limit (Tab to pins 1,2,6,7) VON = 12 V, time until shutdown max. 350 µs Tc =-40°C: Tc =25°C: Tc =+150°C: Short circuit shutdown delay after input current positive slope, VON > VON(SC) min. value valid only if input "off-signal" time exceeds 30 µs IL(SC) IL(SC) IL(SC) td(SC) --65 80 14 110 130 115 -16.5 -180 -350 20 A µs V Output clamp 16) (inductive load switch off) IL= 40 mA: -VOUT(CL) see diagram Ind. and overvolt. output clamp page 8 Output clamp (inductive load switch off) at VOUT = Vbb - VON(CL) (e.g. overvoltage) IL= 40 mA Short circuit shutdown detection voltage (pin 4 to pins 1,2,6,7) VON(CL) VON(SC) Tjt ∆Tjt 39 -150 -- 42 6 -10 47 ---- V V °C K Thermal overload trip temperature Thermal hysteresis Reverse Battery 17 Reverse battery voltage ) -Vbb On-state resistance (Pins 1,2,6,7 to pin 4) Tj = 25 °C: RON(rev) Vbb = -12V, VIN = 0, IL = - 20 A, RIS = 1 kΩ Tj = 150 °C: Integrated resistor in Vbb line ---- -5.4 8.9 120 32 7.0 12.3 -- V mΩ Ω Rbb ) This output clamp can be "switched off" by using an additional diode at the IS-Pin (see page 8). If the diode is used, VOUT is clamped to Vbb- VON(CL) at inductive load switch off. 17) The reverse load current through the intrinsic drain-source diode has to be limited by the connected load (as it is done with all polarity symmetric loads). Note that under off-conditions (I IN = I IS = 0) the power transistor is not activated. This results in raised power dissipation due to the higher voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Increasing reverse battery voltage capability is simply possible as described on page 9. 16 Semiconductor Group Page 5 1998-Nov.-2 BTS650P Parameter and Conditions at Tj = -40 ... +150 °C, Vbb = 12 V unless otherwise specified Symbol Values min typ max Unit Diagnostic Characteristics Current sense ratio, static on-condition, kILIS = IL : IIS, VON < 1.5 V18), VIS 4.0 V see diagram on page 12 IL = 90 A,Tj =-40°C: kILIS Tj =25°C: Tj =150°C: IL = 20 A,Tj =-40°C: Tj =25°C: Tj =150°C: IL = 10 A,Tj =-40°C: Tj =25°C: Tj =150°C: IL = 4 A,Tj =-40°C: Tj =25°C: Tj =150°C: IIS=0 by IIN =0 (e.g. during deenergizing of inductive loads): Sense current saturation Current sense leakage current 12 500 12 500 11 500 12 500 12 000 11 500 12 500 11 500 11 500 11 000 11 000 11 200 6.5 --60 62 -- 14 200 13 700 13 000 14 500 14 000 13 400 15 000 14 300 13 500 18 000 15 400 14 000 --2 -66 -- 16 000 16 000 14 500 17 500 16 500 15 000 19 000 17 500 15 500 28 500 22 000 19 000 -0.5 ---500 mA µA V µs IIS,lim IIN = 0: IIS(LL) VIN = 0, IL ≤ 0: IIS(LH) Current sense overvoltage protection Tj =-40°C: VbIS(Z) Ibb = 15 mA Tj = 25...+150°C: 19) Current sense settling time ts(IS) Input Input and operating current (see diagram page 13) IIN(on) IN grounded (VIN = 0) --- 0.8 -- 1.5 80 mA µA Input current for turn-off20) IIN(off) 18) If VON is higher, the sense current is no longer proportional to the load current due to sense current saturation, see IIS,lim . 19) Not tested, specified by design. 20) We recommend the resistance between IN and GND to be less than 0.5 kΩ for turn-on and more than 500kΩ for turn-off. Consider that when the device is switched off (IIN = 0) the voltage between IN and GND reaches almost Vbb. Semiconductor Group Page 6 1998-Nov.-2 BTS650P Truth Table Input current level Normal operation Very high load current Currentlimitation Short circuit to GND Overtemperature Short circuit to Vbb Open load Negative output voltage clamp Inverse load current L H H H L H L H L H L H L L H Output level L H H H L L L L H H 22 Z) H L H H Current Sense IIS 0 nominal IIS, lim 0 0 0 0 0 0 21 VON(Fold back) if VON>VON(SC), shutdown will occure Remark L = "Low" Level H = "High" Level Overtemperature reset by cooling: Tj < Tjt (see diagram on page 15) Short circuit to GND: Shutdown remains latched until next reset via input (see diagram on page 14) Terms I bb VbIN 4 Vbb IL V bb RIN V IN RON measurement layout VON l≤ 5.5mm 3 IN PROFET IS 5 OUT 1,2,6,7 Vbb force I IS DS R IS VOUT I IN VbIS VIS Out Force Sense contacts contacts (both out pins parallel) Typical RON for SMD version is about 0.2 mΩ less than straight leads due to l ≈ 2 mm Two or more devices can easily be connected in parallel to increase load current capability. 21 22 ) Low ohmic short to Vbb may reduce the output current IL and can thus be detected via the sense current IIS. ) Power Transistor "OFF", potential defined by external impedance. Semiconductor Group Page 7 1998-Nov.-2 BTS650P Input circuit (ESD protection) V bb Current sense status output Vbb R bb ZD IS V V V bIN ZD R bb Z,IS Z,IN IN I IN I IS R IS VIS V IN When the device is switched off (IIN = 0) the voltage between IN and GND reaches almost Vbb. Use a mechanical switch, a bipolar or MOS transistor with appropriate breakdown voltage as driver. VZ,IN = 66 V (typ). Short circuit detection Fault Condition: VON > VON(SC) (6 V typ.) and t> td(SC) (80 ...350 µs). + Vbb VZ,IS = 66 V (typ.), RIS = 1 kΩ nominal (or 1 kΩ /n, if n devices are connected in parallel). IS = IL/kilis can be driven only by the internal circuit as long as Vout - VIS > 5 V. If you want measure load currents up to IL(M), RIS Vbb - 5 V should be less than . IL(M) / Kilis Note: For large values of RIS the voltage VIS can reach almost Vbb. See also overvoltage protection. If you don't use the current sense output in your application, you can leave it open. Inductive and overvoltage output clamp + Vbb VZ1 VON VON VZG OUT OUT Logic unit Short circuit detection DS IS PROFET VOUT VON is clamped to VON(Cl) = 42 V typ. At inductive load switch-off without DS, VOUT is clamped to VOUT(CL) = -19 V typ. via VZG. With DS, VOUT is clamped to Vbb VON(CL) via VZ1. Using DS gives faster deenergizing of the inductive load, but higher peak power dissipation in the PROFET. Semiconductor Group Page 8 1998-Nov.-2 BTS650P Overvoltage protection of logic part + Vbb V R IN Z,IN Vbb disconnect with energized inductive load Provide a current path with load current capability by using a diode, a Z-diode, or a varistor. (VZL < 72 V or VZb < 30 V if RIN=0). For higher clamp voltages currents at IN and IS have to be limited to 250 mA. V Z,IS R bb IN Logic V OUT IS Version a: V PROFET RV Signal GND bb IN V R IS V Z,VIS bb OUT PROFET Rbb = 120 Ω typ., VZ,IN = VZ,IS = 66 V typ., RIS = 1 kΩ nominal. Note that when overvoltage exceeds 71 V typ. a voltage above 5V can occur between IS and GND, if RV, VZ,VIS are not used. IS V ZL Reverse battery protection - Vbb Rbb Version b: V IN OUT bb IN Vbb PROFET OUT RIN Logic IS Power Transistor IS DS RL RV Power GND V Zb D Signal GND RIS RV ≥ 1 kΩ, RIS = 1 kΩ nominal. Add RIN for reverse battery protection in applications with Vbb above 1 1 1 16 V17); recommended value: + + = RIN RIS RV 0.1A 1 0.1A if DS is not used (or = if DS RIN |Vbb| - 12V |Vbb| - 12V is used). To minimize power dissipation at reverse battery operation, the summarized current into the IN and IS pin should be about 120mA. The current can be provided by using a small signal diode D in parallel to the input switch, by using a MOSFET input switch or by proper adjusting the current through RIS and RV. Note that there is no reverse battery protection when using a diode without additional Z-diode VZL, VZb. Version c: Sometimes a neccessary voltage clamp is given by non inductive loads RL connected to the same switch and eliminates the need of clamping circuit: V bb IN Vbb PROFET OUT RL IS Semiconductor Group Page 9 1998-Nov.-2 BTS650P Inverse load current operation Maximum allowable load inductance for a single switch off L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω V bb + IN Vbb - IL PROFET IS OUT L [µH] 1000000 - V OUT + IIS V IN V IS 100000 - R IS 10000 The device is specified for inverse load current operation (VOUT > Vbb > 0V). The current sense feature is not available during this kind of operation (IIS = 0). With IIN = 0 (e.g. input open) only the intrinsic drain source diode is conducting resulting in considerably increased power dissipation. If the device is switched on (VIN = 0), this power dissipation is decreased to the much lower value RON(INV) * I2 (specifications see page 4). Note: Temperature protection during inverse load current operation is not possible! 1000 100 10 1 1A 10 A 100 A 1000 A Inductive load switch-off energy dissipation E bb E AS V V bb ELoad bb i L(t) IN PROFET OUT EL IL [A] Externally adjustable current limit If the device is conducting, the sense current can be used to reduce the short circuit current and allow higher lead inductance (see diagram above). The device will be turned off, if the threshold voltage of T2 is reached by IS*RIS . After a delay time defined by RV*CV T1 will be reset. The device is turned on again, the short circuit current is defined by IL(SC) and the device is shut down after td(SC) with latch function. Vbb IS I ZL { L IN RIS RL ER Energy stored in load inductance: EL = 1/2·L·I L While demagnetizing load inductance, the energy dissipated in PROFET is IN 2 V bb PROFET OUT EAS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt, with an approximate solution for RL > 0 Ω: IL· L IL·RL EAS= (V + |VOUT(CL)|) ln (1+ |V ) 2·RL bb OUT(CL)| IN Signal RV IS Rload T1 Signal GND CV T2 R IS Power GND Semiconductor Group Page 10 1998-Nov.-2 BTS650P Options Overview Type BTS 550P 555 650P X X X X 24 X) X X X24) X X Overtemperature protection with hysteresis Tj >150 °C, latch function23) Tj >150 °C, with auto-restart on cooling Short circuit to GND protection switches off when VON>6 V typ. (when first turned on after approx. 180 µs) Overvoltage shutdown Output negative voltage transient limit to Vbb - VON(CL) to VOUT = -19 V typ ) Latch except when V -V bb OUT < VON(SC) after shutdown. In most cases VOUT = 0 V after shutdown (VOUT ≠ 0 V only if forced externally). So the device remains latched unless Vbb < VON(SC) (see page 5). No latch between turn on and td(SC). 24) Can be "switched off" by using a diode DS (see page 8) or leaving open the current sense output. 23 Semiconductor Group Page 11 1998-Nov.-2 BTS650P Characteristics Current sense versus load current: IIS = f(IL), TJ= -40 ... +150 °C IIS [mA] 7 6 5 max 4 16000 3 2 min 1 0 0 20 40 60 80 12000 10000 0 20 40 60 80 min 14000 typ 18000 max Current sense ratio: IIS = f(IL), TJ= 25 °C kILIS 22000 20000 IL [A] Current sense ratio: KILIS = f(IL),TJ = -40°C kilis Current sense ratio: KILIS = f(IL),TJ = 150°C kilis IL [A] 30000 28000 26000 24000 22000 20000 18000 16000 14000 12000 10000 0 20 40 60 80 IL [A] max 22000 20000 18000 16000 14000 typ min max typ min 12000 10000 0 20 40 60 80 IL [A] Semiconductor Group Page 12 1998-Nov.-2 BTS650P Typ. current limitation characteristic IL = f (VON, Tj ) Typ. input current IIN = f (VbIN), VbIN = Vbb - VIN IIN [mA] 1.6 1.4 1.2 300 250 200 T J = 25°C 150 100 50 0 0 VON(F B) 5 10 15 20 T J = -40°C T J = 150°C VON > VON(S C) only for t < td(S C) (otherwis e immediate s hutdown) IL [A] 450 400 350 1 0.8 0.6 0.4 0.2 0 0 20 40 60 80 VON [V] In case of VON > VON(SC) (typ. 6 V) the device will be switched off by internal short circuit detection. Typ. on-state resistance RON = f (Vbb, Tj ); IL = 20 A; VIN = 0 VbIN [V] RON [mOhm] 14 12 10 8 6 25°C 4 2 0 0 5 10 15 40 -40°C Tj = 150°C 85°C static dynamic Vbb [V] Semiconductor Group Page 13 1998-Nov.-2 BTS650P Timing diagrams Figure 1a: Switching a resistive load, change of load current in on-condition: Figure 2b: Switching an inductive load: IIN IIN VOUT 90% t on dV/dton 10% t off dV/dtoff VOUT IL tslc(IS) t slc(IS) IL Load 1 Load 2 IIS t t IIS tson(IS) t soff(IS) The sense signal is not valid during a settling time after turn-on/off and after change of load current. Figure 3a: Short circuit: shut down by short circuit detection, reset by IIN = 0. Figure 2a: Switching motors and lamps: IIN IIN IL IL(SCp) VOUT td(SC) IIL IIS VOUT>>0 VOUT=0 t IIS t Shut down remains latched until next reset via input. Sense current saturation can occur at very high inrush currents (see IIS,lim on page 6). Semiconductor Group Page 14 1998-Nov.-2 BTS650P Figure 4a: Overtemperature Reset if Tj