C501G-L

C501 8-Bit Single-Chip Microcontroller User’s Manual 04.97 ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ Edition 04.97 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C501 User’s Manual Revision History : Previous Releases : Page (previous version) general Chapter 1 1-2 3-4 to 3-6 4-2 6-10 6-15 follo. 6-23 follo. 6-30 follo. chapter 7 8-2 chapter 9 9-6, 9-9 9-12 9-17 9-18 Chapter 1 1-2 3-2 to 3-7 4-4 4-5 6-10 6-15, 6-16 6-22, 6-23 6-29 chapter 7 8-4 chapter 9 chapter 10 10-3 10-6,10-8 10-10 10-13 10-15/16 10-18 10-21 chapter 11 Page (new version) 04.97 02.96, 08.94, 08.93 (Original Version) Subjects (changes since last revision) C501G-1E OTP version included (new chapter 9, AC/DC characteristics now in chapter 10) Several figures: update with C501-1E signal names and definitions; P-MQFP-44 package (pin configuration and pin numbers) added Feature list is updated Actualized design of the SFR tables Figure 4-1 moved Description of enhanced hooks emulation concept added Figure 6-6 corrected Improved timer 0/1 register description Improved timer 2 register description Improved serial port register description Improved description of the interrupt related functions: all enable, control, and request register bits now included Table 8-1 moved into chapter 8.4 New chapter 9 “OTP Memory Operation of the C501-1E” included Old chapter 9 (“Device Specifications”) is now chapter 10 “DC Characteristics for C501-1E” included Characteristics for “External Clock Drive” on three pages moved below “Ext. Data Memory Characteristics” Old figure 7 moved to figure 10-4 New chapter 10.8 “OTP Programming and Verification Characteristics” Figure 10-9: M-QFP-44 pin numbers for XTAL1/XTAL2 added M-QFP-44 package outline added Manual index information added C501 Table of Contents Page 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 5 5.1 5.2 6 6.1 6.1.1 6.1.1.1 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, “Code Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory, “Data Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . 4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . 6-7 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . 6-11 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 I-1 Semiconductor Group C501 Table of Contents Page 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.4 6.3.5 6.3.6 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 9.5 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Baud Rates Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Power Saving Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . 8-4 OTP Memory Operation of the C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Quick-Pulse Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Encryption Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 OTP Memory Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Semiconductor Group I-2 C501 Table of Contents Page 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 DC Characteristics for C501-L / C501-1R . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 DC Characteristics for C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 AC Characteristics for C501-L / C501-1R / C501-1E . . . . . . . . . . . . . . . . 10-5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 . . . . . . . . . . . 10-7 AC Characteristics for C501-L40 / C501-1R40 . . . . . . . . . . . . . . . . . . . . . 10-9 ROM Verification Characteristics for C501-1R . . . . . . . . . . . . . . . . . . . . . 10-14 OTP Programming and Verification Characteristics for C501-1E . . . . . . 10-15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Semiconductor Group I-3 Introduction C501 1 Introduction The C501-L, C501-1R, and C501-1E described in this document are compatible (also pincompatible) with the 80C52 and can be used in typical 80C52 applications. The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/write data memory, four ports, three 16-bit timers/counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted. Power Saving Modes T0 T2 T1 RAM 256 x 8 Port 0 Ι /O Port 1 CPU USART Port 2 Ι /O Ι /O 8K x 8 ROM (C501-1R) 8K x 8 OTP (C501-1E) Port 3 Ι /O MCA03238 Figure 1-1 C501G Functional Units Semiconductor Group 1-1 Introduction C501 Listed below is a summary of the main features of the C501: • • • • • • • • • • • • • Fully compatible to standard 8051 microcontroller Versions for 12/24/40 MHz operating frequency Program memory : completely external (C501-L) 8K × 8 ROM (C501-1R) 8K × 8 OTP memory (C501-1E) 256 × 8 RAM Four 8-bit ports Three 16-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C501-1E only) 2-Level program memory lock (C501-1E only) P-DIP-40, P-LCC-44, and P-MQFP-44 package Temperature ranges : SAB-C501 TA : 0 ˚C to 70 ˚C SAF-C501 TA : – 40 ˚C to 85 ˚C VCC VSS XTAL1 XTAL2 Port 0 8-Bit Digital Ι /O Port 1 8-Bit Digital Ι /O RESET EA /VPP ALE/PROG PSEN C501 Port 2 8-Bit Digital Ι /O Port 3 8-Bit Digital Ι /O MCL03217 Figure 1-2 Logic Symbol Semiconductor Group 1-2 Introduction C501 1.1 Pin Configuration This section shows the pin configuration of the C501 in the P-LCC-44, P-DIP-40, and P-MQFP-44 packages. P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 N.C VCC 6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 C501 18 19 20 21 22 23 24 25 26 27 28 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS N.C. P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 MCP03214 Figure 1-3 Pin Configuration P-LCC-44 Package (top view) Semiconductor Group 1-3 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 Introduction C501 T2/P1.0 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 C501 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 MCP03215 VSS Figure 1-4 Pin Configuration P-DIP-40 Package (top view) Semiconductor Group 1-4 Introduction C501 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC N.C. P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C501 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 N.C. VSS XTAL1 XTAL2 RD/P3.7 WR/P3.6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 MCP03216 Figure 1-5 Pin Configuration P-MQFP-44 Package (top view) Semiconductor Group 1-5 Introduction C501 1.2 Pin Definitions and Functions This section describes all external signals of the C501 with its function. Table 1-1 Pin Definitions and Functions Symbol P1.0 – P1.7 2–9 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 1–8 40–44, 1–3, I/O Port 1 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 1 also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: P1.0 T2 Input to counter 2 P1.1 T2EX Capture - Reload trigger of timer 2 / Up-Down count I/O*) Function 2 3 *) I = Input O = Output 1 2 40 41 Semiconductor Group 1-6 Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol P3.0 – P3.7 11, 13–19 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 10–17 5, 7–13 I/O Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 R×D receiver data input (asynchronous) or data input output (synchronous) of serial interface 0 P3.1 T×D transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 INT0 interrupt 0 input/timer 0 gate control P3.3 INT1 interrupt 1 input/timer 1 gate control P3.4 T0 counter 0 input P3.5 T1 counter 1 input P3.6 WR the write control signal latches the data byte from port 0 into the external data memory P3.7 RD the read control signal enables the external data memory to port 0 I/O*) Function 11 10 5 13 11 7 14 15 16 17 18 12 13 14 15 16 8 9 10 11 12 19 17 13 *) I = Input O = Output Semiconductor Group 1-7 Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol XTAL2 20 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 18 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. Port 2 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. I/O*) Function XTAL1 21 19 15 – P2.0 – P2.7 24–31 21–28 18–25 I/O *) I = Input O = Output Semiconductor Group 1-8 Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol PSEN 32 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 29 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. For the C501-1E this pin is also the program pulse input (PROG) during OTP memory programming. External Access Enable When held at high level, instructions are fetched from the internal ROM (C501-1R and C501-1E) when the PC is less than 2000H. When held at low level, the C501 fetches all instructions from external program memory. For the C501-L this pin must be tied low. This pin also receives the programming supply voltage VPP during OTP memory programming (C501-1E) only). I/O*) Function RESET 10 9 4 I ALE/PROG 33 30 27 I/O EA/VPP 35 31 29 I *) I = Input O = Output Semiconductor Group 1-9 Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol P0.0 – P0.7 43–36 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 39–32 37–30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code bytes during program verification in the C501-1R and C501-1E. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection I/O*) Function VSS VCC N.C. 22 44 1, 12, 23, 34 20 40 – 16 38 6, 17, 28, 39 – – – *) I = Input O = Output Semiconductor Group 1-10 Fundamental Structure C501 2 Fundamental Structure The C501 is fully compatible to the standard 8051 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051 microcontroller family, the C501 incorporates some enhancements in the timer 2 and fail save mechanism unit. Figure 2-6 shows a block diagram of the C501. V CC V SS XTAL1 XTAL2 C501 RAM C501-1R : ROM C501-1E : OTP 8K x 8 OSC & Timing 256 x 8 RESET ALE/PROG PSEN EA/VPP CPU Timer 0 Timer 1 Port 1 Timer 2 Port 2 Interrupt Unit Serial Channel (USART) Port 3 Port 3 8-Bit Digit. Ι /O Port 2 8-Bit Digit. Ι /O Port 0 8-Bit Digit. Ι /O Port 0 Port 1 8-Bit Digit. Ι /O MCB03219 Figure 2-6 Block Diagram of the C501 Semiconductor Group 2-1 Fundamental Structure C501 2.1 CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1.0 µs (24 MHz : 500 ns, 40 MHz : 300 ns). The CPU (Central Processing Unit) of the C501 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-2 Fundamental Structure C501 Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00 H-07H Bank 1 selected, data address 08 H-0FH Bank 2 selected, data address 10 H-17H Bank 3 selected, data address 18 H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-3 Fundamental Structure C501 2.2 CPU Timing A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logically operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-7 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-7 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C501 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-7 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. Semiconductor Group 2-4 Fundamental Structure C501 Figure 2-7 Fetch Execute Sequence Semiconductor Group 2-5 Memory Organization C501 3 Memory Organization The C501 CPU manipulates operands in the following four address spaces: – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C501. FFFF H FFFF H External External Indirect Address FF H Internal RAM 2000 H 1FFF H Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "Data Space" Internal RAM 80 H Direct Address Special Function Register 7F H 00 H FF H 80 H "Internal Data Space" MCD03224 Figure 3-1 C501 Memory Map Semiconductor Group 3-1 Memory Organization C501 3.1 Program Memory, “Code Space” The C501-1R/-1E has 8 Kbytes of read-only/OTP program memory, while the C501-L has no internal program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C501 executes out of internal program memory unless the address exceeds 1FFFH. Locations 2000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C501 fetches all instructions from the external program memory. 3.2 Data Memory, “Data Space” The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 and RS1, select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 Memory Organization C501 3.4 Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 3-1 and table 3-2. In table 3-2 they are organized in groups which refer to the functional blocks of the C501. Table 3-3 illustrates the contents (bits) of the SFRs. Semiconductor Group 3-3 Memory Organization C501 Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON 2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte Power Control Register Address E0H 1) F0H 1) 83H 82H D0H 1) 81H A8H1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C8H 1) C9H CBH CAH CDH CCH 87H Contents after Reset 00H 00H 00H 00H 00H 07H 0X000000B 3) XX000000B 3) FFH FFH FFH FFH 0XXX0000B 3) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 3) 00H 00H 00H 00H 0XXX0000B 3) Interrupt System Ports Serial Channel Timer 0 / Timer 1 Timer 2 Pow. Sav. PCON 2) Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group 3-4 Memory Organization C501 Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H2) P0 81H 82H 83H 87H SP DPL DPH PCON FFH 07H 00H 00H 0XXX0000B 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 0X000000B FFH XX000000B 00H XXXXXXX0B 00H 00H 00H 00H .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .5 .5 .5 .5 – TF0 M1 .5 .5 .5 .5 .5 SM2 .5 .5 ET2 T1 PT2 RCLK – .5 .5 .5 .5 .4 .4 .4 .4 – TR0 M0 .4 .4 .4 .4 .4 REN .4 .4 ES T0 PS TCLK – .4 .4 .4 .4 .3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 .3 TB8 .3 .3 ET1 INT1 PT1 .2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 .2 RB8 .2 .2 EX1 INT0 PX1 .1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 .1 TI .1 .1 ET0 TxD PT0 C/T2 – .1 .1 .1 .1 .0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 .0 RI .0 .0 EX0 RxD PX0 CP/ RL2 DCEN .0 .0 .0 .0 SMOD – TF1 GATE .7 .7 .7 .7 .7 SM0 .7 .7 EA RD – TF2 – .7 .7 .7 .7 TR1 C/T .6 .6 .6 .6 .6 SM1 .6 .6 – WR – EXF2 – .6 .6 .6 .6 88H2) TCON 89H 8AH 8BH TMOD TL0 TL1 8CH TH0 8DH TH1 90H 99H 2) P1 SBUF 98H2) SCON A0H2) P2 A8H2) IE B0H2) P3 B8H2) IP C8H2) T2CON C9H T2MOD CAH RC2L CBH RC2H CCH TL2 CDH TH2 EXEN2 TR2 – .3 .3 .3 .3 – .2 .2 .2 .2 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 3-5 Memory Organization C501 Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) D0H2) PSW E0H2) ACC F0H2) B 00H 00H 00H CY .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC .6 .6 F0 .5 .5 RS1 .4 .4 RS0 .3 .3 OV .2 .2 F1 .1 .1 P .0 .0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 3-6 External Bus Interface C501 4 External Bus Interface The C501 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FF H to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 External Bus Interface C501 a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN MCT03220 RD P2 P0 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 External Bus Interface C501 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: – whenever signal EA is active (low) or – whenever the program counter (PC) contains a number that is larger than 1FFF H. This requires the ROM-less version C501-L to have EA wired low to allow the lower 8K program bytes to be fetched from external memory. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). When the C501 executes instructions from external program memory, port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the C501 can never be used as general-purpose I/O. This means that port 0 and port 2 of the C501-L can never be used as general-purpose I/O. This also applies to the C501-1R/1E when they are operating with external program memory only. Semiconductor Group 4-3 External Bus Interface C501 4.2 PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 ALE, Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. 4.4 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C501 the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-4 External Bus Interface C501 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too (not true for the C509-l, because it lacks internal program memory). Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology TM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 4-5 System Reset C501 5 5.1 System Reset Hardware Reset The hardware reset function incorporated in the C501 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. The RESET input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the RESET pin for a specific time to effect a complete reset. A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0, 1, 2 and 3 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1, 2 and 3) output at one (1). The content of the internal RAM of the C501 is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-1 System Reset C501 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1’s etc. The RESET signal must be active for at least two machine cycles; after this time the C501 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. in PCL OUT PCH OUT P2 ALE MCT02092 Figure 5-3 CPU Timing after Reset Semiconductor Group 5-2 On-Chip Peripheral Components C501 6 On-Chip Peripheral Components I/O Ports The C501 has four 8-bit I/O portst. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. 6.1 Parallel I/O 6.1.1 Port Structures Digital I/O The C501 allows for digital I/O on 32 lines grouped into 4 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P3 are performed via their corresponding special function registers P0 to P3. Semiconductor Group 6-1 On-Chip Peripheral Components C501 Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 4 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a “read-pin” signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P3) activate the “read-latch” signal, while others activate the “read-pin” signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-4 Basic Structure of a Port Circuitry Semiconductor Group 6-2 On-Chip Peripheral Components C501 Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-5). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-5: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current ( IIL or ITL). For this reason these ports are sometimes called “quasi-bidirectional”. Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-5 Basic Output Driver Circuit of Ports 1, 2, and 3 Semiconductor Group 6-3 On-Chip Peripheral Components C501 In fact, the pullups mentioned before and included in figure 6-5 are pullup arrangements as shown in figure 6-6. One n-channel pulldown FET and three pullup FETs are used: Delay = 1 State VCC =1 _