C504

C504 8-Bit CMOS Microcontroller User's Manual 10.97 ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ Edition 1997-10-01 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. General Information C504 C504 Data Sheet Revision History : Previous Releases : 1997-10-01 06.96 (Original Version) Page (new Page (prev. Subjects (changes since last revision) version) version) general 1-1 1-4 1-6 2-1 3-3, 3-4 3-11 3-85-2 4-6 to 4-8 5-4 5-6, 5-7 6-7 – 6-8 6-14 6-18 6-26 6-33 6-36 6-42 6-41 6-45 6-50 6-51 6-52 6-58 6-70 Ch.6.3.4 6-80, 6-81 7-3 7-14 9-1 11-2 11-3, 11-4 11-15 to 11-18 Ch.12 several 1-1 1-4 1-6 2-1 4-6, 4-7 – 5-1 4-8 to 4-10 5-3 – 6-7 6-8 6-9 6-13 – – 6-31 6-34 6-40 6-39 6-43 6-48 6-49 6-50 6-56 6-68 Ch.6.3.4 – 7-3 7-13 9-1 10-2 11-3 – Ch.11 several C504-2E OTP version included (new chapter 10) C504-2E AC/DC characteristics are now in chapter 11 Figure 1-1 completed Figure 1-3 completed RESET pin desc. : “..for the duration of two machine cycl...“ corrected Figure 2-1 completed Chapter 3.4 “XRAM Operation“ moved from chapter 4 to chapter 3 Version register information added Figure 5-2 “Reset Circuitries“ added Chapter 4.6/4.7 “ROM Protection ....“ enhanced for OTP verification Figure 5-3/5-2 corrected Chapter 5.4 “Oscillator and Clock Circuit“ added Figure 6-5 corrected; modified sentence : “During this time, the P2 SFR remains unchanged while the P0 SFR has 1’s written to it.“ Figure 6-6 added Figure 6-6/6-7 corrected; also text in paragraph “The pullup FET p1 of...“ 2nd sentence modified : “activated for one state...“ Figure 6-11/6-10 corrected Timer 0/1 count register definitions added Timer 2 count and reload/capture register definitions added Figure 6-19 corrected Figure 6-21 corrected Sentence below table added Invalid characters in formulas corrected (“x“) Note in figure 6-26 below added 1. paragraph, 2nd line : ... or CCx and COUTx .. added Description of the two new CMSEL1 bits ESMC and NMCS added CMSEL table : upper 4 lines “ or analog input pins...“ deleted, see note Paragraph with active/passive state definition moved from 6-70/6-68 Text in last but one paragraph modified New wording :“4-phase“ multi-channel PWM mode instead of “4-pole“.. New chapter 6.3.4.5 added Figure 7-2/7-1b: address of bit EA in corrected External interrupts : description of the TCON bits added Corrected text in 1st paragraph : PCON/PCON1 have differert addr. VPP specification added New improved ICC specification added AC charcteristics of programming mode added Improved index with bold page numbers for main reference pages Writing errors corrected Semiconductor Group I-3 General Information C504 Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 4 4.1 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 5 5.1 5.2 5.3 5.4 6 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.1.3.4 6.1.4 6.1.5 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XRAM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode). . . . . . . . . Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlapping External Data and Program Memory Spaces. . . . . . . . . . . . . . . . . . . . ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM/OTP Protection for C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unprotected ROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protected ROM/OTP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-2 3-2 3-3 3-3 3-4 3-4 3-5 4-1 4-1 4-2 4-2 4-4 4-5 4-6 4-6 4-7 5-1 5-1 5-3 5-5 5-6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Port 1 and Port 3 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Type B Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Type C Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Type D Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Type E Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Port Loading and Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Semiconductor Group I-1 1997-10-01 General Information C504 Table of Contents 6.1.6 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.3 6.3.1 6.3.2 6.3.2.1 6.3.2.2 6.3.2.3 6.3.2.4 6.3.2.5 6.3.2.6 6.3.2.7 6.3.2.8 6.3.3 6.3.3.1 6.3.4 6.3.4.1 6.3.4.2 6.3.4.3 6.3.4.4 6.3.4.5 6.3.4.6 6.4 6.4.1 6.4.2 6.4.3 6.4.3.1 6.4.3.2 6.4.4 6.4.5 6.4.6 6.5 6.5.1 6.5.2 6.5.3 Page Read-Modify-Write Feature of Ports 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Timer/Counter 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Capture / Compare Unit (CCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 General Capture/Compare Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 CAPCOM Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 CAPCOM Unit Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 CAPCOM Unit Operating Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 CAPCOM Unit Operating Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 CAPCOM Unit Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Burst Mode of CAPCOM / COMP Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 CAPCOM Unit in Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 Trap Function of the CAPCOM Unit in Compare Mode . . . . . . . . . . . . . . . . . . . . . 6-44 CAPCOM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 Compare (COMP) Unit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 COMP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 Combined Multi-Channel PWM Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 Control Register BCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 Signal Generation in Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . . . . . . . 6-70 Block Commutation PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 Compare Timer 1 Controlled Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . 6-75 Software Controlled State Switching in Multi-Channel PWM Modes . . . . . . . . . . . 6-80 Trap Function in Multi-Channel Block Commutation Mode . . . . . . . . . . . . . . . . . . 6-81 Serial Interface (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82 Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 Serial Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95 10-bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98 A/D Converter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100 A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103 Semiconductor Group I-2 1997-10-01 General Information C504 Table of Contents 6.5.4 6.5.5 6.5.6 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 8 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 9 9.1 9.2 9.2.1 9.2.2 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.5 10.6 10.7 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Page A/D Conversion Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 A/D Converter Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108 A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Sources and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Prioritiy Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Reset and Watchdog Status Flag (WDTS) . . . . . . . . . . . . . . . . . . . . . . . Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit from Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-4 8-4 8-5 8-6 8-7 9-1 9-3 9-5 9-5 9-6 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Basic Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 AC Characteristics for C504-L / C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . 11-8 AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 . . . . . . . . . . . . . . . . 11-10 AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 . . . . . . . . . . . . . . . . 11-12 AC Characteristics of Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Semiconductor Group I-3 1997-10-01 General Information C504 Table of Contents 11.8 11.9 12 13 Page ROM/OTP Verification Characteristics for C504-2R / C504-2E . . . . . . . . . . . . . . 11-20 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Microelectronics Training Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 Information on Literature Semiconductor Group - Addresses Semiconductor Group I-4 1997-10-01 Introduction C504 1 Introduction T he C504 is a modified and extended version of the C501 Microcontroller. Its enhanced functionality, especially the capture compare unit (CCU), allows to use the MCU in motor control applications. Further, the C504 is compatible with the SAB 80C52/C501 microcontrollers and can replace it in existing applications. The C504-2R contains a non-volatile 16K × 8 read-only program memory, a volatile on-chip 512 × 8 read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/ compare unit, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the on-chip program memory The C504-2E is the OTP version in the C504 microcontroller with a 16Kx8 one-time programmable (OTP) program memory.The term C504 refers to all versions within this documentation unless otherwise noted. Oscillator Watchdog On-Chip Emulation Support Module 10-Bit ADC Timer 2 16-Bit Capture/Compare Unit 10-Bit Compare Unit Watchdog Timer T0 XRAM 256 x 8 RAM 256 x 8 Port 0 I/O Port 1 C500 Core 8-Bit USART Port 2 8-Bit Digital I/O 4-Bit Analog Inputs T1 I/O ROM/OTP 16 k x 8 Port 3 8-Bit Digital I/O 4-Bit Analog Inputs MCB02589 Figure 1-1 C504 Functional Units Semiconductor Group 1-1 1997-10-01 Introduction C504 Listed below is a summary of the main features of the C504: • • • • • • • • • • • • • • • • • • Fully compatible to standard 8051 microcontroller Up to 40 MHz external operating frequency 16K byte on-chip program memory – C504-2R : ROM version (with optional ROM protection) – C504-2E : programmable OTP version – C504-L : without on-chip program memory) – alternatively up to 64K byte external program memory 256 × 8 RAM 256× 8 XRAM Four 8-bit ports, (2 ports with mixed analog/digital I/O capability) Three 16-bit timers/counters (timer 2 with up/down counter feature) Capture/compare unit for PWM signal generation and signal capturing - 3-channel, 16-bit capture/compare unit - 1-channel, 10-bit compare unit USART 10-bit A/D Converter with 8 multiplexed inputs Twelve interrupt sources with two priority levels On-chip emulation support logic (Enhanced Hooks Technology TM) Programmable 15-bit Watchdog Timer Oscillator Watchdog Fast Power On Reset Power Saving Modes M-QFP-44 package Temperature ranges: SAB-C504 TA : 0 to 70°C TA : – 40 to 85°C SAF-C504 SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD) SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz) Semiconductor Group 1-2 1997-10-01 Introduction C504 Figure 1-2 Logic Symbol Semiconductor Group 1-3 1997-10-01 Introduction C504 1.1 Pin Configuration This section describes the pin configration of the C504 in the P-MQFP-44 package. 33 32 31 30 29 28 27 26 25 24 23 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V GND P1.0 / AN0 / T2 P1.1 / AN1 / T2EX P1.2 / AN2 / CC0 P1.3 / AN3 / COUT0 P1.4 / CC1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V CC V SS XTAL1 XTAL2 P3.7 / RD P3.6 / WR / INT2 P1.5 / COUT1 P1.6 / CC2 P1.7 / COUT2 RESET P3.0 / RxD CTRAP P3.1 / TxD P3.2 / AN4 / INT0 P3.3 / AN5 / INT1 P3.4 / AN6 / T0 P3.5 / AN7 / T1 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA COUT3 ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C504-LM C504-2RM C504-2EM 1 2 3 4 5 6 7 8 9 10 11 MCP02532 Figure 1-3 Pin Configuration (top view) Semiconductor Group 1-4 1997-10-01 Introduction C504 1.2 Pin Definitions and Functions This section describes all external signals of the C504 with its function. Table 1-1 Pin Definitions and Functions Symbol P1.0-P1.7 Pin Number (P-MQFP-44) 40-44, 1-3 I/O *) I/O Function Port 1 is an 8-bit bidirectional port. Port pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D-converter. As secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 / input to counter 2 P1.1 / AN1 / T2EX Analog input channel 1 / capture/reload trigger of timer 2 / updown count P1.2 / AN2 / CC0 Analog input channel 2 / input/output of capture/compare channel 0 P1.3 / AN3 / COUT0 Analog input channel 3 / output of capture/compare channel 0 P1.4 / CC1 Input/output of capture/compare channel 1 P1.5 / COUT1 Output of capture/compare channel 1 P1.6 / CC2 Input/output of capture/compare channel 2 P1.7 / COUT2 Output of capture/compare channel 2 RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. 40 41 42 43 44 1 2 3 RESET 4 I *) I = Input O = Output Semiconductor Group 1-5 1997-10-01 Introduction C504 Table 1-1 Pin Definitions and Functions (cont’d) Symbol P3.0-P3.7 Pin Number (P-MQFP-44) 5, 7-13 I/O *) I/O Function Port 3 is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, input and as an additional optinal function four of the analog inputs of the A/D-converter. Port 3 pins are assigned to be used as analog inputs by the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / AN4 / INT0 Analog input channel 4 / external interrupt 0 input / timer 0 gate control input P3.3 / AN5 / INT1 Analog input channel 5 / external interrupt 1 input / timer 1 gate control input P3.4 / AN6 / T0 Analog input channel 6 / timer 0 counter input P3.5 / AN7 / T1 Analog input channel 7 / timer 1 counter input P3.6 / WR / INT2 WR control output; latches the data byte from port 0 into the external data memory / external interrupt 2 input RD control output; enables the P3.7 / RD external data memory CCU Trap Input With CTRAP = low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode. 5 7 8 9 10 11 12 13 CTRAP 6 I *) I = Input O = Output Semiconductor Group 1-6 1997-10-01 Introduction C504 Table 1-1 Pin Definitions and Functions (cont’d) Symbol XTAL2 XTAL1 Pin Number (P-MQFP-44) 14 15 I/O *) – – Function XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. P2.0-P2.7 18-25 I/O PSEN 26 O ALE 27 O *) I = Input O = Output Semiconductor Group 1-7 1997-10-01 Introduction C504 Table 1-1 Pin Definitions and Functions (cont’d) Symbol COUT3 Pin Number (P-MQFP-44) 28 I/O *) O Function 10-Bit compare channel output This pin is used for the output signal of the 10-bit compare timer 2 unit. COUT3 can be disabled and set to a high or low state. External Access Enable When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H .When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification. Reference voltage for the A/D converter. Reference ground for the A/D converter. Ground (0V) Power Supply (+5V) EA 29 I P0.0-P0.7 30-37 I/O VAREF VAGND VSS VCC *) I = Input O = Output 38 39 16 17 – – – – Semiconductor Group 1-8 1997-10-01 Fundamental Structure C504 2 Fundamental Structure The C504 basically is fully compatible to the architecture of the standard 8051 microcontroller family. Especially it is functionally upward compatible with the SAB 80C52/C501 microcontrollers. While maintaining all architectural and operational characteristics of the SAB 80C52/C501, the C504 incorporates a genuine 10-bit A/D Converter, a capture/compare unit, a XRAM data memory as well as some enhancements in the Timer 2 and Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C504. VCC VSS XTAL1 XTAL2 Oscillator Watchdog XRAM 256 x 8 OSC & Timing RAM 256 x 8 ROM/OTP 16 k x 8 CPU RESET ALE PSEN EA Timer 0 Port 0 Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O 4-Bit Analog Inputs Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O 4-Bit Analog Inputs Timer 1 Port 1 Timer 2 Port 2 Interrupt Unit Port 3 USART COUT3 CTRAP Capture/Compare Unit VAREF VAGND A/D Converter 10-Bit Emulation Support Logic MCB02591 S&H MUX Figure 2-1 Block Diagram of the C504 Semiconductor Group 2-1 1997-10-01 Fundamental Structure C504 2.1 CPU The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12-MHz crystal, 58% of the instructions execute in 1.0 µs (40 MHz: 300 ns). The CPU (Central Processing Unit) of the C504 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, completement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-2 1997-10-01 Fundamental Structure C504 Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-3 1997-10-01 Fundamental Structure C504 2.2 CPU Timing A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logically operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C504 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. Semiconductor Group 2-4 1997-10-01 Fundamental Structure C504 Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-5 1997-10-01 Memory Organization C504 3 Memory Organization The C504 CPU manipulates operands in the following four address spaces: – – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C504. Figure 3-1 C504 Memory Map Semiconductor Group 3-1 1997-10-01 Memory Organization C504 3.1 Program Memory, "Code Space" The C504-2R has 16 Kbytes of read-only program memory, while the C504-L has no internal program memory. The C504-2E provides 16 Kbytes of OTP program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C504 executes out of internal ROM unless the program counter address exceeds 3FFFH. Locations 4000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C504 fetches all instructions from the external program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16-bit or an 8-bit address. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 1997-10-01 Memory Organization C504 3.4 XRAM Operation The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. The C504 maps 256 bytes of the external data space into the on-chip XRAM. Especially when using the 8-bit addressing modes this could prevent access to the external memory extension and might induce problems when porting software. Therefore, it is possible to enable and disable the on-chip XRAM using the bit XMAP in SFR SYSCON. When the XRAM is disabled (default after reset), all external data memory accesses will go to the external data memory area. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – 6 – 5 EALE 4 RMAP 3 – 2 – 1 – Reset Value : XX10XXX0B LSB 0 XMAP SYSCON The functions of the shaded bits are not described in this section. Bit – XMAP Function Not implemented. Reserved for future use. Enable XRAM XMAP=0 : XRAM disabled. XMAP=1 : XRAM enabled. If XRAM is enabled, 8-bit MOVX instructions using Ri always access the internal XRAM and do not generate external bus cycles. If XRAM is enabled, 16-bit MOVX instructions using DPTR, access the XRAM if the address is in the range of FF00H to FFFFH and do not generate external bus cycles in this address range. Reset Operation of the XRAM 3.4.1 The content of the XRAM is not affected by a reset. After power-up the content is undefined, while it remains unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value. After reset the access to the XRAM is disabled (bit XMAP of SYSCON = 0). Semiconductor Group 3-3 1997-10-01 Memory Organization C504 3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are: – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) Using these instructions with the XRAM disabled implies, that port 0 is used as address low/data bus, port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control to access up to 64 KB of external memory. If the XRAM is enabled and if the effective address stored in DPTR is in the range of 0000H to FEFFH, these instruction will access external memory. If XRAM is enabled and if the address is within FF00H to FFFFH, the physically internal XRAM of the C504 will be accessed. External memory, which is located in this address range, cannot be accessed in this case because no external bus cycles will generated. Therefore port 0, 2 and 3 can be used as general purpose I/O if only the XRAM memory space is addressed by the user program. 3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The C504 architecture provides also instructions for accesses to external data memory and XRAM which use an 8-bit address (indirect addressing with registers R0 or R1). These instructions are: – MOVX – MOVX A, @Ri @Ri, A (Read) (Write) Using these instructions with the XRAM disabled implies, that port 0 is used as address/data bus, port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control. Normally these instructions are used to access 256 byte pages of external memory. If the XRAM is enabled these instruction will only access the internal XRAM. External memory cannot be accessed in this case because no external bus cycle will be generated. Therefore port 0, 2 and 3 can be used as standard I/O, if only the internal XRAM is used. Semiconductor Group 3-4 1997-10-01 Memory Organization C504 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Three special function registers of the C504 (PCON1, P1ANA, P3ANA) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers of the C504 are located in the standard special function register area. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX10XXX0B LSB 0 XMAP SYSCON 6 – 5 EALE 4 RMAP 3 – 2 – 1 – The functions of the shaded bits are not described in this section. Bit – RMAP Function Not implemented. Reserved for future use. Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. As long as bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. There are also 128 directly addressable bits available within each SFR area (standard and mapped SFR area). All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 63 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C504 are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C504. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group 3-5 1997-10-01 Memory Organization C504 Table 3-1 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP Name Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H A8H1) A9H D6H B8H 1) B9H 9AH 80H 1) 90H 1) 90H 1) 4) A0H 1) B0H 1) B0H 1) 4) D8H 1 DCH D9H DAH 90H 4) B0H 4) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 07H XX10XXX0B 3) 0X000000B 3) XX000000B 3) 00H XX000000B 3) XX000000B 3) 00101010B FFH FFH XXXX1111B 3) FFH FFH XX1111XXB 3) XX000000B 3) 01XXX000B 3) 00H 00XXXXXXB 3) XXXX1111B 3) XX1111XXB 3) 000X0000B XXH 3) 00H 00H 00H 00H 00H 00H 00H Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer SYSCON System Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 3 Analog Input Selection Register Interrupt System IEN0 IEN1 CCIE 2) IP0 IP1 ITCON P0 P1 P1ANA 2) P2 P3 P3ANA 2) ADCON0 ADCON1 Ports A/DConverter A/D Converter Control Register 0 A/D Converter Control Register 1 ADDATH A/D Converter Data Register High Byte ADDATL A/D Converter Data Register Low Byte P1ANA 2) Port 1 Analog Input Selection Register P3ANA 2) Port 3 Analog Input Selection Register PCON 2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Serial Channels Timer 0/ Timer 1 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-6 1997-10-01 Memory Organization C504 Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Timer 2 Symbol T2CON T2MOD RC2H RC2L TH2 TL2 CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE 2) CT2CON CP2L CP2H CMP2L CMP2H BCON Name Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register Address Contents after Reset C8H 1) C9H CBH CAH CDH CCH E1H DEH DFH E6H E7H E3H E4H E2H CFH C2H C3H C4H C5H C6H C7H E5H D6H C1H D2H D3H D4H D5H D7H C0H 1) 86H 87H 88H 4) 00H XXXXXXX0B 3) 00H 00H 00H 00H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00B 3) 00H XXXXXX00B 3)) 00H XXXX0000B 3) 00H 000X0000B 3) 0XXXXXXXB 3) Capture / Compare Unit Watchdog WDCON Watchdog Timer Control Register WDTREL Watchdog Timer Reload Register Power Control Register Power Control Register 1 Power PCON 2) Save Mode PCON1 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-7 1997-10-01 Memory Organization C504 Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) P0 SP DPL DPH FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 2) 81H 82H 83H 86H 87H 88H 2) .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 – M1 .5 .5 .5 .5 .5 – SM2 .5 I2ETF .5 ET2 ECT1 .4 .4 .4 .4 .4 – TR0 – M0 .4 .4 .4 .4 .4 – REN .4 I2ETR .4 ES .3 .3 .3 .3 .3 GF1 IE1 – GATE .3 .3 .3 .3 .3 EAN3 TB8 .3 I1ETF .3 ET1 .2 .2 .2 .2 .2 GF0 IT1 – C/T .2 .2 .2 .2 .2 EAN2 RB8 .2 I1ETR .2 EX1 ECEM .1 .1 .1 .1 .1 PDE IE0 – M1 .1 .1 .1 .1 T2EX EAN1 TI .1 I0ETF .1 ET0 EX2 .0 .0 .0 .0 .0 IDLE IT0 – M0 .0 .0 .0 .0 T2 EAN0 RI .0 I0ETR .0 EX0 EADC WDTREL 00H PCON TCON 000X0000B SMOD PDS 88H 2)3) PCON1 89H 8AH 8BH 8CH 8DH 90H 2) TMOD TL0 TL1 TH0 TH1 P1 00H TF1 TR1 0XXX- EWPD – XXXXB 00H 00H 00H 00H 00H FFH XXXX1111B 00H XXH 00101010B FFH 0X000000B XX000000B GATE .7 .7 .7 .7 .7 – SM0 .7 IT2 .7 EA – C/T .6 .6 .6 .6 .6 – SM1 .6 IE2 .6 – – 90H 2)3) P1ANA 98H 2) 99H 9AH SCON SBUF ITCON A0H 2) P2 A8H 2) IEN0 A9H IEN1 ECCM ECT2 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-8 1997-10-01 Memory Organization C504 Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) FFH XX1111XXB RD – – – – – CT2P .7 .7 .7 .7 .7 .7 TF2 – .7 .7 .7 .7 CY .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H 2) P3 B0H 2)3) P3ANA B1H WR – – – – – T1 EAN7 EALE PT2 PCT1 – T0 EAN6 RMAP PS INT1 EAN5 – PT1 INT0 EAN4 – PX1 PCEM TxD – – PT0 PX2 RxD – XMAP PX0 PADC SWDT CLK0 .0 .0 .0 .0 .0 .0 CP/ RL2 DCEN .0 .0 .0 .0 P .0 SYSCON XX10XXX0B XX000000B XX000000B XXXX0000B B8H 2) IP0 B9H IP1 PCCM PCT2 – CT2 RES .4 .4 .4 .4 .4 .4 TCLK – .4 .4 .4 .4 RS1 .4 C0H 2) WDCON C1H C2H C3H C4H C5H C6H OWDS WDTS WDT CT2R .3 .3 .3 .3 .3 .3 CLK2 .2 .2 .2 .2 .2 .2 CLK1 .1 .1 .1 .1 .1 .1 C/T2 – .1 .1 .1 .1 F1 .1 CT2CON 00010000B CCL0 CCH0 CCL1 CCH1 CCL2 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 00H 00H 00H 00H 00H 00H 00H ECT2O STE2 .6 .6 .6 .6 .6 .6 EXF2 – .6 .6 .6 .6 AC .6 .5 .5 .5 .5 .5 .5 RCLK – .5 .5 .5 .5 F0 .5 C7H CCH2 C8H 2) T2CON C9H CAH CBH CCH CDH T2MOD RC2L RC2H TL2 TH2 EXEN2 TR2 – .3 .3 .3 .3 RS0 .3 – .2 .2 .2 .2 OV .2 CFH TRCON D0H 2) PSW D2H CP2L TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-9 1997-10-01 Memory Organization C504 Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) CP2H CMP2L CMP2H CCIE BCON XXXX. XX00B 00H XXXX. XX00B 00H 00H – .7 – ECTP BCMP BCEM – .9 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D3H D4H D5H D6H D7H – .6 – – .5 – – .4 – CC2 REN – .3 – CC1 FEN – .2 – CC1 REN .1 .1 .1 CC0 FEN BCM1 MX1 .3 – MX1 .1 .1 .1 CLK1 COUT 0I .0 .0 .0 CC0 REN BCM0 MX0 .2 – MX0 .0 .0 .0 CLK0 CC0I ECTC CC2 FEN PWM1 PWM0 EBCE – .8 .0 IADC .7 – BSY .6 – – .4 .4 .4 CT1 RES CC2I BCERR BCEN D8H 2) ADCON0 XX000000B D9H DAH DCH DEH DFH E1H E2H E3H E4H E5H E6H E7H F0H 2) ADM .5 – – .3 .3 .3 CT1R COUT 1I MX2 .4 – MX2 .2 .2 .2 CLK2 CC1I ADDATH 00H ADDATL 00XX- .1 XXXXB ADCON1 01XXX000B CCPL CCPH 00H 00H ADCL1 ADCL0 – .7 .7 .7 CTM COUT 3I .6 .6 .6 ETRP .5 .5 .5 STE1 E0H 2) ACC 00H CT1CON 00010000B COINI FFH COUT COUT XI 2I CMSEL0 00H CMSEL1 00H CCIR 00H CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 ESMC NMCS 0 0 CC2R .4 .4 .4 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 CT1FP CT1FC CC2F .7 .7 .7 .6 .6 .6 .5 .5 .5 CC1F .3 .3 .3 CC1R .2 .2 .2 CC0F .1 .1 .1 CC0R .0 .0 .0 CT1OFL 00H CT1OFH 00H B 00H 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 3-10 1997-10-01 Memory Organization C504 Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) VR0 VR1 VR2 C5H 04H 84H 6) 5) 5) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCH 3) 4) 1 0 1 .7 1 0 .6 0 0 .5 0 0 .4 0 0 .3 1 1 .2 0 0 .1 1 0 .0 FDH 3) 4) FEH 3) 4) 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These SFRs are read-only registers. 5) 04H is valid for the C504-2R, 84H is valid for the C504-2E, 6) The content of this SFR varies with the actual step of the C504 (see also table 10-4 in chapter 10). Semiconductor Group 3-11 1997-10-01 External Bus Interface C504 4 External Bus Interface The C504 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 1997-10-01 External Bus Interface C504 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustrated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. External Program Memory Access The external program memory is accessed under two conditions: – whenever signal EA is active: or – whenever the program counter (PC) contains a number that is larger than 3FFFH. This requires the ROM-less version C504-L to have EA wired low to allow the lower 16K program bytes to be fetched from external memory. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). Since the C504-L has no internal program memory, accesses to program memory are always external, and port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the C504-L can never be used as general-purpose I/O. This also applies to the C504-2R or C504-2E when they operat only with an external program memory. 4.2 PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 12 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C504 the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-2 1997-10-01 External Bus Interface C504 a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST IN PCL OUT PCL OUT valid b) S1 ALE PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST IN RD P2 P0 MCD02575 Figure 4-1 External Program Memory Execution Semiconductor Group 4-3 1997-10-01 External Bus Interface C504 4.4 ALE, Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. The C504 allows to switch off the ALE output signal. If the internal ROM is used (EA=1) and ALE is switched off by EALE=0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 3FFFH (external code memory fetches). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX10XXX0B LSB 0 XMAP SYSCON 6 – 5 EALE 4 RMAP 3 – 2 – 1 – The function of the shaded bit is not described in this section. Bit – EALE Function Not implemented. Reserved for future use. Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 3FFFH. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. Semiconductor Group 4-4 1997-10-01 External Bus Interface C504 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. Semiconductor Group 4-5 1997-10-01 External Bus Interface C504 4.6 ROM/OTP Protection for C504-2R / C504-2E The C504-2R ROM version allows to protect the content of the internal ROM against read out by non authorized people. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM protection has to be selected or not. The C504-2E OTP version allows also program memory protection in several levels (see chapter 10.6). The program memory protection for the C504-2E can be activated after programming of the device. The C504-2R devices, which operate from internal ROM, are always checked for correct ROM content during production test. Therefore, unprotected and also protected ROMs must provide a procedure to verify the ROM content. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C504-2R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different: ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the content of the ROM can read out and verify it with less effort. 4.6.1 Unprotected ROM Mode If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-3 is used to read out the content of the ROM (see also the AC specifications in chapter 10, not valid for C504-2E). Figure 4-3 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. P2.6 and P2.7 must be held at low level. Whenever the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2, after a delay time, port 0 outputs the content of the addressed internal program memory cell. In ROM verification mode 1, the C504-2R must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. Semiconductor Group 4-6 1997-10-01 External Bus Interface C504 4.6.2 Protected ROM/OTP Mode If the C504-2R ROM is protected by mask (or C504-2E OTP in protection level 1), the ROM/OTP verification mode 2 as shown in figure 4-4 is used to verify the content of the ROM/OTP. The detailed timing characteristics of the ROM/OTP verification mode is shown in the AC specifications (chapter 11). Figure 4-4 ROM Verification Mode 2 ROM/OTP verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM/OTP verification mode 2 sequence is started. The C504 outputs an ALE signal with a period of 12 tCLCL and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way: 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal ROM/OTP address 0000H content of internal ROM/OTP address 0001H content of internal ROM/OTP address 0002H content of internal ROM/OTP address 000FH The C504 does not output any address information during the ROM/OTP verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the ROM/OTP address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Semiconductor Group 4-7 1997-10-01 External Bus Interface C504 Between two ALE pulses the data at port 0 is latched (at 6 tCLCL after ALE rising edge) and compared internally with the ROM/OTP content of the actual address. If an verify error is detected, the error condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. P3.5 is always set or cleared after each 16 byte block of the verify sequence. In ROM/OTP verification mode 2, the C504 must be provided with a system clock at the XTAL pins. Figure 4-5 shows an application example of a external circuitry which allows to verify a protected ROM/OTP inside the C504 in ROM/OTP verification mode 2. With RESET going inactive, the C504 starts the ROM/OTP verify sequence. Its ALE is clocking an 14-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the content of the internal (protected) ROM/OTP. The verify detect logic typically displays the state of the verify error output P3.5. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal ROM/OTP has been handled, the C504 starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM/OTP verification. P3.5 Verify Detect Logic CY A0 - A13 ALE 2 kΩ CLK 14-Bit Address Counter R C504-2R C504-2E & VCC & RESET Port 0 Compare Code ROM D0 - D7 VCC EA P2.7 PSEN CS OE MCB02595 Figure 4-5 ROM/OTP Verification Mode 2 - External Circuitry Example Semiconductor Group 4-8 1997-10-01 Reset / System Reset C504 5 5.1 Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C504 allows an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. Additionally to the hardware reset, which is applied externally to the C504, there are two internal reset sources, the watchdog timer and the oscillator watchdog. The chapter at hand only deals with the external hardware reset. The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycle (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the reset pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. Semiconductor Group 5-1 1997-10-01 Reset / System Reset C504 The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. a) b) & RESET + C504 c) C504 + RESET C504 MCS03352 RESET Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0, 1, 2, and 3 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 to 3) output a one (1). The contents of the internal RAM and XRAM of the C504 is not affected by a reset. After power-up the contents are undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-2 1997-10-01 Reset / System Reset C504 5.2 Fast Internal Reset after Power-On The C504 uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C504 the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-2). Under worst case conditions (fast VCC rise time - e.g. 1µs, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is: – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VCC below 4.25V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-2, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-2, III). However, an externally applied reset still remains active (figure 5-2, IV) and the device does not start program execution (figure 5-2, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – – Termination of Software Power-Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal or ceramic resonator for clock generation, the external reset signal must be hold active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficient in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin. Semiconductor Group 5-3 1997-10-01 Reset / System Reset C504 Figure 5-2 Power-On Reset Timing of the C504 Semiconductor Group 5-4 1997-10-01 Reset / System Reset C504 5.3 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least one machine cycle; after this time the C504 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. in PCL OUT PCH OUT P2 ALE MCT02092 Figure 5-3 CPU Timing after Reset Semiconductor Group 5-5 1997-10-01 Reset / System Reset C504 5.4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-4 shows the recommended oscillator circuit. C XTAL2 3.5 - 40 MHz C XTAL1 C = 20 pF 10 pF for crystal operation MCS03353 C504 Figure 5-4 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Semiconductor Group 5-6 1997-10-01 Reset / System Reset C504 To internal timing circuitry **) XTAL2 *) XTAL1 C504 C1 C2 *) Crystal or ceramic resonator **) Resistor is only in the C504-2E MCS03354 Figure 5-5 On-Chip Oscillator Circuiry To drive the C504 with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-6. XTAL2 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL1. V CC N.C. C504 XTAL2 External Clock Signal XTAL1 MCS03355 Figure 5-6 External Clock Source Semiconductor Group 5-7 1997-10-01 On-Chip Peripheral Components C504 6 6.1 On-Chip Peripheral Components Parallel I/O The C504 has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. 6.1.1 Port Structures The C504 generally allows digital I/O on 32 lines grouped into 4 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P3 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. Therefore, the parallel I/O ports of the C504 can be grouped into five different types which are listed in table 6-1. Table 6-1 C504 Port Structures Type A B C D E Description Standard digital I/O ports which can be also used for external address/data bus. Standard multifunctional digital I/O port lines Mixed digital/analog I/O port lines with programmable analog input function Standard digital I/O port lines with push-pull drive capability Mixed digital/analog I/O port lines with push-pull drive capability and programmable analog input function Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 and provide alternate functions for the serial interface or are used as control outputs during external data memory accesses. The C504 provides eight analog input lines which are realized as mixed digital/analog inputs. The 8 analog inputs are split into two groups of four inputs each. Four analog inputs AN0-AN3 are located at the port 1 pins P1.0 to P1.3 and the other four analog inputs AN4-AN7 are located at the port 3 pins P3.2 to P3.5 (type C and type E port lines). After reset, all analog inputs are disabled and the related pins of port 1 and 3 are configured as digital inputs. The analog function of the specific port 1 and port 3 pins is enabled by bits in the SFRs P1ANA and P3ANA. Writing a 0 to a bit position of P1ANA or P3ANA assigns the corresponding pin to operate as analog input. Semiconductor Group 6-1 1997-10-01 On-Chip Peripheral Components C504 Note: P1ANA and P3ANA are mapped SFRs and can be only accessed if bit RMAP in SFR SYSCON is set (description see chapter 6.5.4). Type D and E port lines can be switched to push-pull drive capability when they are used as compare outputs of the CAPCOM unit. As already mentioned, port 1 and 3 are provided for multiple alternate functions. These second and third functions of the port 1 and 3 lines are listed in table 6-2: Table 6-2 Alternate Functions of Port 1 and 3 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Second / third Port Function Function Type AN0 / T2 AN1 / T2EX AN2 / CC0 AN3 / COUT0 CC1 COUT1 CC2 COUT2 RxD TxD AN4 / INT0 AN5 / INT1 AN6 / T0 AN7 / T1 WR / INT2 RD C C E E D D D D B B C C C C B B Analog input channel 0 / input to counter 2 Analog input channel 1 / capture-reload trigger of timer 2 / up down count Analog input channel 2 / CAPCOM channel 0 input/output Analog input channel 3 / CAPCOM channel 0 output CAPCOM channel 1 input/output CAPCOM channel 1 output CAPCOM channel 2 input/output CAPCOM channel 2 output Serial port’s receiver data input (asynchronous) or data input/ output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) Analog input channel 4 / External interrupt 0 input, timer 0 gate control Analog input channel 5 / External interrupt 1 input, timer 1 gate control Analog input channel 6 / Timer 0 external counter input Analog input channel 7 / Timer 1 external counter input External data memory write strobe / External interrupt 2 input External data momory read strobe Prior to the description of the port type specific port configurations the general port structure is described in the next section. Semiconductor Group 6-2 1997-10-01 On-Chip Peripheral Components C504 6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the four I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0, P2, P3) activate the "read-latch" signal, while others activate the "read-pin" signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-1 Basic Structure of a Port Circuitry Semiconductor Group 6-3 1997-10-01 On-Chip Peripheral Components C504 Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional". Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-2 Basic Output Driver Circuit of Ports 1, 2 and 3 Semiconductor Group 6-4 1997-10-01 On-Chip Peripheral Components C504 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Addr./Data Read Latch Control & VCC =1 Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q MUX Read Pin MCS02434 Figure 6-3 Port 0 Circuitry Semiconductor Group 6-5 1997-10-01 On-Chip Peripheral Components C504 6.1.2.2 Port 1 and Port 3 Circuitry The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-2. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Read Latch Alternate Output Function VCC Internal Pull Up Arrangement Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS01827 Read Pin Alternate Input Function Figure 6-4 Ports 1 and 3 Semiconductor Group 6-6 1997-10-01 On-Chip Peripheral Components C504 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1’s written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-5. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-6) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Addr. Read Latch Control VCC Internal Pull Up Arrangement Port Pin Int. Bus D Bit Latch CLK Q MUX Q =1 Write to Latch Read Pin MCS03228 Figure 6-5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. Note : during MOVX accesses to the internal XRAM no external bus cycles are generated. Semiconductor Group 6-7 1997-10-01 On-Chip Peripheral Components C504 Addr. Control VCC Q _