C505_9708

C505 C505C 8-Bit CMOS Microcontroller tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ User's Manual 08.97 ht C505 User’s Manual Revision History : Previous Releases : Page (previous version) Page (new version) 1997-08-01 Original Version Subjects (changes since last revision) Edition 1997-08-01 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997, All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. General Information C505 / C505C Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.7 4.7.1 4.7.2 4.8 5 5.1 5.2 5.3 5.4 5.5 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 XRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 XRAM/CAN Controller Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . 3-5 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) . . . . . . . . . 3-5 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Behaviour of Port 0 and Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . . . 4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 How the eight Datapointers of the C505 are realized . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 ROM Protection for the C505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Unprotected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Protected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Version Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-3 5-5 5-6 5-8 Semiconductor Group I-1 1997-08-01 General Information C505 / C505C Table of Contents 6 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.3 6.1.3.1 6.1.3.2 6.1.4 6.1.5 6.1.6 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.3.1 6.2.2.3.2 6.2.2.3.3 6.2.2.4 6.2.2.5 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.3.1 6.3.3.3.2 6.3.4 6.3.5 6.3.6 6.4 6.4.1 Page On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Port 1, Port 3 and Port 4 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Type B Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Type C Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Read-Modify-Write Feature of Ports 0 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Timer/Counter 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . . . . 6-23 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Timer 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Modulation Range in Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . . . . 6-38 Capture Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 Baud Rate in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Using the Internal Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 The On-Chip CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 Basic CAN Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 Semiconductor Group I-2 1997-08-01 General Information C505 / C505C Table of Contents 6.4.2 6.4.2.1 6.4.2.2 6.4.3 6.4.4 6.4.5 6.4.5.1 6.4.5.2 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.5 Page CAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 The Message Object Registers / Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 Handling of Message Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88 Configuration of the Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90 Hard Synchronization and Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92 Calculation of the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92 CAN Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93 CAN Controller in Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94 Configuration Examples of a Transmission Object . . . . . . . . . . . . . . . . . . . . . . . . . 6-95 Configuration Examples of a Reception Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96 The CAN Application Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98 A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100 A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 A/D Converter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105 A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Fail Save Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Down Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit from Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-2 8-3 8-4 8-5 8-5 8-6 9-1 9-1 9-3 9-5 9-6 9-6 9-7 9-8 Semiconductor Group I-3 1997-08-01 General Information C505 / C505C Table of Contents 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11 Page Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 AC Characteristics (16 MHz) for C505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 AC Characteristics (20 MHz) for C505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 ROM Verification Characteristics for C505-2R . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Semiconductor Group I-4 1997-08-01 Introduction C505 / C505C 1 Introduction The C505 microcontroller is a member of the Siemens C500 family of 8-bit microcontrollers. The C505 is fully compatible to the standard 8051 microcontroller. Additionally the C505 provides extended power save provisions, on-chip RAM, 16K of on-chip program memory, and RFI related improvements. The C505 does not have an internal clock prescaler and with a maximum external clock rate of 20 MHz it achieves a 300 ns instruction cycle time. The C505-2R operates with internal and/or external program memory. The C505-L is identical to the C505-2R, except that it lacks the on-chip porgram memory. The C505C-2R and C505C-L, are identical to the C505-2R and the C505-L respectively, except that they have, in addition, the full CAN interface. Therefore, the term C505 refers to all the above four versions within this documentation unless otherwise noted. Figure 1-1 shows the different functional units of the C505 and Figure 1-2 shows the simplified logic symbol of the C505. Oscillator Watchdog XRAM 256 x 8 T0 CPU T1 RAM 256 x 8 Port 0 Port 1 I/O 8 Analog Inputs / 8 Digit. I / O I/O I/O I / O (2-Bit I / O Port) On-Chip Emulation Support Module 8-Bit ADC Timer 2 Full-CAN Controller Watchdog Timer 8-Bit USART Port 2 Port 3 Port 4 8 Datapointers ROM 16k x 8 C505C only MCB03283 Figure 1-1 C505 Functional Units Semiconductor Group 1-1 1997-08-01 Introduction C505 / C505C Listed below is a summary of the main features of the C505 family: Fully compatible to standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers Up to 20 MHz operating frequency – 375 ns instruction cycle time @ 16 MHz – 300 ns instruction cycle time @ 20 MHz (50 % duty cycle) • 16K byte on-chip ROM (C505-2R and C505C-2R only) – Optional ROM protection available • 256 byte on-chip RAM • 256 byte on-chip XRAM • Five ports: 32 + 2 digital I/O lines(Port 1 with mixed analog/digital I/O capability) • Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation • Full CAN Module (C505C only) – 256 register/data bytes located in external data memory area – 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz – internal CAN clock prescaler when input frequency is over 10 MHz • Full duplex serial interface with programmable baudrate generator (USART) • 8-bit A/D Converter • Twelve interrupt sources with four priority levels • On-chip emulation support logic (Enhanced Hooks) • Programmable 15-bit Watchdog Timer • Oscillator Watchdog • Fast Power On Reset • Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through INT0 or P4.1 pin • P-MQFP-44 package • Pin configuration is compatible to C501, C504, C511/C513-family TA = 0 to 70 °C • Temperature ranges: SAB-C505 SAF-C505 TA = – 40 to 85 °C SAH-C505 TA = – 40 to 110 °C (max. operating frequency: TBD) SAK-C505 TA = – 40 to 125 °C (max. operating frequency: 8 MHz) • • • Semiconductor Group 1-2 1997-08-01 Introduction C505 / C505C V CC V SS V AREF V AGND Port 0 8-Bit Digital I / O XTAL1 XTAL2 Port 1 8-Bit Digital I / O / 8-Bit Analog Inputs C505 Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O Port 4 2-Bit Digital I / O RESET EA ALE PSEN RXDC TXDC C505C only MCL03284 Figure 1-2 Logic Symbol Semiconductor Group 1-3 1997-08-01 Introduction C505 / C505C 1.1 Pin Configuration This section shows the pin configuration of the C505 in the P-MQFP-44 package. 33 32 31 30 29 28 27 26 25 24 23 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V AGND P1.0 / AN0 / INT3 / CCO P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V CC V SS XTAL1 XTAL2 P3.7 / RD P3.6 / WR P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 RESET P3.0 / RxD P4.0 / TXDC P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P4.1 / RXDC ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C505 1 2 3 4 5 6 7 8 9 10 11 MCP03285 Figure 1-3 Pin Configuration (top view) Semiconductor Group 1-4 1997-08-01 Introduction C505 / C505C 1.2 Pin Definitions and Functions This section describes all external signals of the C505 with its function. Table 1-1 Pin Definitions and Functions Symbol P1.0-P1.7 Pin Number 40-44,1-3 I/O*) I/O Function Port 1 i s an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( I I L , i n the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 Interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ Interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / Interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 Interrupt 6 input / capture/compare channel 4 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / System clock output P1.7 / AN7 / T2 Analog input channel 7 / Counter 2 input Port 1 is used for the low-order address byte during program verification of the C505-2R. 40 41 42 43 44 1 2 3 *) I = Input O = Output Semiconductor Group 1-5 1997-08-01 Introduction C505 / C505C Table 1-1 Pin Definitions and Functions Symbol RESET Pin Number 4 I/O*) I Function RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. Port 3 i s an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I I L , i n the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input WR control output; latches the data P3.6 / WR byte from port 0 into the external data memory RD control output; enables the external P3.7 / RD data memory P3.0-P3.7 5, 7-13 I/O 5 7 8 9 10 11 12 13 *) I = Input O = Output Semiconductor Group 1-6 1997-08-01 Introduction C505 / C505C Table 1-1 Pin Definitions and Functions Symbol P4.0 P4.1 Pin Number 6 28 I/O*) I/O I/O Function Port 4 i s a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I I L , i n the DC characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C only): P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. XTAL2 XTAL1 14 15 O I *) I = Input O = Output Semiconductor Group 1-7 1997-08-01 Introduction C505 / C505C Table 1-1 Pin Definitions and Functions Symbol P2.0-P2.7 Pin Number 18-25 I/O*) I/O Function Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. PSEN 26 O ALE 27 O *) I = Input O = Output Semiconductor Group 1-8 1997-08-01 Introduction C505 / C505C Table 1-1 Pin Definitions and Functions Symbol EA Pin Number 29 I/O*) I Function External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 4000H. When held at low level, the C505 fetches all instructions from external program memory. This pin should not be driven during reset operation. For the C505-L and the C505C-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C505C-2R. External pullup resistors are required during program verification. Reference voltage for the A/D converter. Reference ground for the A/D converter. Ground (0V) Power Supply (+ 5 V) P0.0-P0.7 37-30 I/O VAREF VAGND VSS VCC *) I = Input O = Output 38 39 16 17 – – – – Semiconductor Group 1-9 1997-08-01 Fundamental Structure C505 / C505C 2 Fundamental Structure The C505 is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C505 incorporates a CPU with 8 datapointers, an 8-bit A/D converter, a 4-channel capture/compare unit, a Full-CAN controller unit (C505C only), an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C505. Semiconductor Group 2-1 1997-08-01 Fundamental Structure C505 / C505C V CC V SS C505 Oscillator Watchdog XRAM 256 x 8 RAM 256 x 8 ROM 16k x 8 XTAL1 OSC & Timing XTAL2 CPU 8 Datapointers RESET ALE PSEN EA Programmable Watchdog Timer Timer 0 Timer 1 Timer 2 USART Baudrate Generator 256 Byte Reg. / Data Port 2 Port 2 8-Bit Digit. I / O Port 3 8-Bit Digit. I / O Port 4 2-Bit Digit. I / O Port 0 Port 0 8-Bit Digit. I / O Port 1 8-Bit Digit. I / O 8-Bit Analog In Port 1 Port 3 Full-CAN Controller Port 4 Interrupt Unit V AREF V AGND A / D Converter 8-Bit Emulation Support Logic MCB03286 S&H MUX C505C only Figure 2-1 Block Diagram of the C505 Semiconductor Group 2-2 1997-08-01 Fundamental Structure C505 / C505C 2.1 CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 16 MHz external clock, 58% of the instructions execute in 375 ns (20 MHz : 300 ns). The CPU (Central Processing Unit) of the C505 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-set, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Additionally to the CPU functionality of the C501/8051 standard microcontroller, the C505 contains 8 datapointers. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-3 1997-08-01 Fundamental Structure C505 / C505C Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instructions. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instructions. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-4 1997-08-01 Fundamental Structure C505 / C505C 2.2 CPU Timing The C505 has no clock prescaler. Therefore, a machine cycle of the C505 consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C505 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. Semiconductor Group 2-5 1997-08-01 Fundamental Structure C505 / C505C S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL2) ALE Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) S5 S6 Read Next Opcode Again (a) 1-Byte, 1-Cycle Instruction, e. g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 Read Next Opcode (b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) Read Next Opcode Again S4 S5 S6 S5 S6 S1 S2 S3 (c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read Next Opcode (Discard) S5 ADDR S6 S1 Read Next Opcode Again No Fetch No Fetch No ALE S2 DATA MCD03287 S3 S4 S5 S6 (d) MOVX (1-Byte, 2-Cycle) Access of External Memory Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-6 1997-08-01 Memory Organization C505 / C505C 3 Memory Organization The C505 CPU manipulates operands in the following four address spaces: – – – – – – up to 64 Kbytes of program memory (16K on-chip program memory for C505-2R) up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory 256 bytes CAN controller registers / data memory (C505C only) a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C505. Alternatively FFFF H Internal XRAM (256 KByte) Ext. Data Memory Ext. Not used Int. CAN Contr. (256 Byte) F6FF H 4000 H 3FFF H Ext. Data Memory Indirect Addr. Internal RAM 80 H 7F H Internal RAM 0000 H "Code Space" C505C only "Data Space" 0000 H 00 H "internal Data Space" MCD03288 FFFF H FF00 H F7FF H F700 H Direct Addr. Special Function Regs. 80 H FF H FF H Int. (EA = 1) Ext. (EA = 0) Figure 3-1 C505 Memory Map Semiconductor Group 3-1 1997-08-01 Memory Organization C505 / C505C 3.1 Program Memory, "Code Space" The C505-2R has 16 Kbytes of read-only program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C505-2R executes program code out of the internal ROM unless the program counter address exceeds 3FFFH. Address locations 4000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C505 fetches all instructions from the external program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal CAN controller (C505C only) and the internal XRAM are located in the external memory address area at addresses F700H to F7FFH and FF00H to FFFFH respectively. The CAN controller registers and internal XRAM can therefore be accessed using MOVX instructions with addresses pointing to the respective address areas. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 1997-08-01 Memory Organization C505 / C505C 3.4 XRAM Operation The XRAM in the C505 is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. 3.4.1 XRAM/CAN Controller Access Control Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM/CAN controller accesses. CAN controller accesses are applicable only in the case of the C505C versions. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX100X01B LSB 0 SYSCON 6 – 5 EALE 4 3 2 – 1 RMAP CMOD XMAP1 XMAP0 The functions of the shaded bits are not described here. Bit XMAP1 Function XRAM/CAN controller visible access control Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. Global XRAM/CAN controller access enable/disable control XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. Reserved bits for future use. Read by CPU returns undefined values. XMAP0 – When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and WR become active and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted. Semiconductor Group 3-3 1997-08-01 Memory Organization C505 / C505C After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM and CAN controller are generally disabled. In this case, all accesses using MOVX instructions within the address range of F700H to FFFFH generate external data memory bus cycles. When XMAP0 is cleared, the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with an address in the range of F700H to F7FFH will access the CAN controller and FF00H to FFFFH will access the internal XRAM. Internal accesses (XMAP0=0) in the address range gap from F800H to FEFFH for the C505C (as shown in figure 3-1) will have undefined data. In the case of the pure C505 microcontroller (without CAN controller), internal accesses in the address range of F700H to FEFFH will have undefined data Bit XMAP0 is hardware protected. If it is cleared once (XRAM and CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an asymmetric latch at XMAP0 bit. An unintentional disabling of XRAM and CAN controller could be dangerous since indeterminate values could be read from the external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor is charged. So the reset state is a disabled XRAM and CAN controller. Because of the charge time of the capacitor, XMAP0 bit once written to '0' (that is, discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion (software hang up, noise,...) is not able to charge this capacitor, too. That is, the stable status is XRAM and CAN controller enabled. The clear instruction for the XMAP0 bit should be integrated in the program initialization routine before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant clear instructions. Note: The CAN controller peripheral exists in the C505C only. Semiconductor Group 3-4 1997-08-01 Memory Organization C505 / C505C 3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM and CAN controller can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are : – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of FF00H to FFFFH. For accessing the CAN controller, the effective address stored in DPTR must be in the range of F700H to F7FFH. 3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX MOVX A, @Ri @Ri, A (Read) (Write) Aspecial page register is implemented in the C505 to provide the possibility of accessing the XRAM or CAN controller also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM and CAN controller as Port 2 for external data memory. Special Function Register XPAGE (Address 91H) Bit No. MSB 7 91H .7 Reset Value : 00H LSB 0 .0 XPAGE 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 Bit XPAGE.7-0 Function XRAM/CAN controller high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM or CAN controller. Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differences in accessing XRAM/CAN controller, ext. RAM or what is to do when Port 2 is used as an I/O-port. Semiconductor Group 3-5 1997-08-01 Memory Organization C505 / C505C Port 0 Address/Data XPAGE Write to Port 2 Port 2 XRAM CAN-Controller Page Address MCS02761 Figure 3-2 Write Page Address to Port 2 “MOV P2,pageaddress“ will write the page address to port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM/CAN controller address range, the XRAM/CAN controller has to be disabled. When additional external RAM is to be addressed in an address range < F700H, the XRAM/CAN controller may remain enabled and there is no need to overwrite XPAGE by a second move. Semiconductor Group 3-6 1997-08-01 Memory Organization C505 / C505C Port 0 Address/Data XPAGE Write to XPAGE Port 2 XRAM CAN-Controller Address/ I/O Data MCS02762 Figure 3-3 Write Page Address to XPAGE “MOV XPAGE,pageaddress“ will write the page address only to the XPAGE register. Port 2 is available for addresses or I/O data. Semiconductor Group 3-7 1997-08-01 Memory Organization C505 / C505C Port 0 Address/Data XPAGE Write I/O Data to Port 2 Port 2 XRAM CAN-Controller I/O Data MCS02763 Figure 3-4 Use of Port 2 as I/O Port At a write to port 2, the XRAM/CAN controller address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register. So, whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address. Example : I/O data at port 2 shall be AAH. A byte shall be fetched from XRAM at address FF30H. MOV MOV MOV MOVX R0, #30H P2, #0AAH XPAGE, #0FFH A, @R0 ; ; P2 shows AAH and XPAGE contains AAH ; P2 still shows AAH but XRAM is addressed ; the contents of XRAM at FF30H is moved to accumulator Semiconductor Group 3-8 1997-08-01 Memory Organization C505 / C505C The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM/CAN Controller address range, an external access is performed. For the C505 the content of XPAGE must be F7H FFH in order to use the XRAM/CAN Controller. The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used : a) Access to XRAM/CAN Contr. : The upper address byte must be written to XPAGE or P2; both writes select the XRAM/CAN controller address range. b) Access to external memory : The upper address byte must be written to P2; XPAGE will be automatically loaded with the same address in order to deselect the XRAM. 3.4.4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset. After power-up the contents are undefined, while they remain unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value. 3.4.5 Behaviour of Port 0 and Port 2 The behaviour of port 0 and port 2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA. The table 3-1 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus:The pins work as external address/data bus. If (internal) XRAM/CAN controller is accessed, the data written to the XRAM/CAN controller can be seen on the bus in debug mode. I/0:The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal (XRAM/CAN controller) or external XDATA memory. The shaded areas describe the standard operation as each C5xx device without on-chip XRAM/ CAN controller behaves. Semiconductor Group 3-9 1997-08-01 Semiconductor Group 3-10 1997-08-01 EA = 0 XMAP1, XMAP0 00 MOVX @DPTR DPTR < XRAM/CAN address range DPTR ≥ XRAM/CAN address range MOVX @ Ri XPAGE < XRAM/CAN addr.page range XPAGE ≥ XRAM/CAN addr.page range a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus (RD/WR-Data) b)RD/WR inactive c)XRAM/CAN is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus (RD/WR-Data) P2→I/O b)RD/WR inactive c)XRAM/CAN is used 10 a)P0/P2→Bus b)RD/WR active c)ext.memory is used X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used 00 a)P0/P2→Bus b)RD/WR active c)ext.memory is used 10 EA = 1 XMAP1, XMAP0 X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus a)P0/P2→I/O (RD/WR-Data) b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM/CAN is c) ext.memory c)XRAM/CAN is used is used used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus (RD/WR-Data) b)RD/WR active b)RD/WR active c)XRAM/CAN is c) ext.memory used is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus a)P0→Bus a)P0/P2→I/O (RD/WR-Data) P2→I/O P2→I/O b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM/CAN is c)ext.memory is c)XRAM/CAN is used used used a)P0→Bus a)P0→Bus (RD/WR-Data) P2→I/O P2→I/O b)RD/WR active b)RD/WR active c)XRAM/CAN is c)ext.memory is used used Memory Organization C505 / C505C modes compatible to 8051/C501 family Table 3-1 - Behaviour of P0/P2 and RD/WR During MOVX Accesses Memory Organization C505 / C505C 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. One special function register of the C505 (PCON1) is located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH. Details about the access of these registers is described in section 3.4.1 of this chapter. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX100X01B LSB 0 SYSCON 6 – 5 EALE 4 3 2 – 1 RMAP CMOD XMAP1 XMAP0 The functions of the shaded bits are not described here. Bit RMAP Function Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. Reserved bits for future use. Read by CPU returns undefined values. – As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in table 3-2 and table 3-3. In table 3-2 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C only) are also included in table 3-2. Table 3-3 illustrates the contents of the SFRs in numeric order of their addresses. Table 3-4 list the CAN-SFRs in numeric order of their addresses. . Semiconductor Group 3-11 1997-08-01 Memory Organization C505 / C505C Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP SYSCON2) VR04) VR14) VR24) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register A/D Converter Start Register Port 1 Analog Input Selection Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register Address Contents after Reset E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H B1H FCH FDH FEH D8H 1) DCH D9H DAH 90H 4) A8H1) B8H 1) A9H B9H 88H 1) C8H 1) 98H 1) C0H 1) 00H 00H 00H 00H XXXXX000B 3) 00H 07H XX100X01B 3) C5H 05H 5) A/DADCON0 2) Converter ADCON1 ADDAT ADST P1ANA2) Interrupt System IEN0 2) IEN1 2) IP0 2) IP1 TCON 2) T2CON 2) SCON 2) IRCON XPAGE SYSCON2) Ports P0 P1 P1ANA 2) P2 P3 P4 00X00000B 3) 01XXX000B 3) 00H XXH 3) FFH 00H 00H 00H XX000000B 3) 00H 00X00000B 00H 00H 00H XX100X01B 3) FFH FFH FFH FFH FFH XXXXXX11B XRAM Page Address Register for Extended on-chip 91H XRAM and CAN Controller System Control Register B1H Port 0 80H 1) Port 1 90H 1) Port 1 Analog Input Selection Register 90H 1) 4) Port 2 A0H 1) Port 3 B0H 1) Port 4 E8H 1) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505 (eg. 01H for the first step) Semiconductor Group 3-12 1997-08-01 Memory Organization C505 / C505C Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Serial Channel Symbol ADCON0 2) PCON 2) SBUF SCON SRELL SRELH TCON TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN0 2) IEN1 2) Name A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Address Contents after Reset D8H 1 87H 99H 98H 1) AAH BAH 88H 1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 1) A8H1) B8H 1) 86H A8H1) B8H 1) A9H 87H 88H 1) 00X00000B 3) 00H XXH 3) 00H D9H XXXXXX11B 3) 00H 00H 00H 00H 00H 00H 00H 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 3) 00H 00H 00H 00H 00H 00H 00H 0XX0XXXXB 3) Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 Watchdog WDTREL IEN0 2) IEN1 2) IP0 2) Power Save Modes PCON 2) PCON14) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-13 1997-08-01 Memory Organization C505 / C505C Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers : Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 Address Contents after Reset F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H 5) F7n1H 5) F7n2H 5) F7n3H 5) F7n4H 5) F7n5H 5) F7n6H 5) F7n7H 5) F7n8H 5) F7n9H 5) F7nAH 5) F7nBH 5) F7nCH 5) F7nDH 5) F7nEH 5) 01H XXH 3) XXH 3) UUH 3) 0UUUUUUUB 3) CAN CR Controller SR (C505C) IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 UUH 3) UUU11111B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUUUUU00B3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation “n” (n= 1 to F) in the message object address definition defines the number of the related message object. Semiconductor Group 3-14 1997-08-01 Memory Organization C505 / C505C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 SP DPL DPH Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 2) P0 81H 82H 83H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 3) .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 – M1 .5 .5 .5 .5 T2EX EAN5 .5 – SM2 .5 .5 ET2 .5 .4 .4 .4 .4 .4 SD TR0 WS M0 .4 .4 .4 .4 .4 EAN4 .4 – REN .4 .4 ES .4 .4 .3 .3 .3 .3 .3 GF1 IE1 – GATE .3 .3 .3 .3 .3 EAN3 .3 – TB8 .3 .3 ET1 .3 .3 .2 .2 .2 .2 .2 GF0 IT1 – C/T .2 .2 .2 .2 INT5 EAN2 .2 .2 RB8 .2 .2 EX1 .2 .2 .1 .1 .1 .1 .1 PDE IE0 – M1 .1 .1 .1 .1 INT4 EAN1 .1 .1 TI .1 .1 ET0 .1 .1 .0 .0 .0 .0 .0 IDLE IT0 – M0 .0 .0 .0 .0 .0 EAN0 .0 .0 RI .0 .0 EX0 .0 .0 WDTREL 00H PCON PCON1 TMOD TL0 TL1 TH0 TH1 00H 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH FFH 00H XXXXX000B 00H XXH FFH 00H 00H D9H SMOD PDS TR1 EWPD – GATE .7 .7 .7 .7 T2 EAN7 .7 – SM0 .7 .7 EA .7 C/T .6 .6 .6 .6 CLKOUT EAN6 .6 – SM1 .6 .6 WDT .6 88H 2) TCON 90H 2) P1 90H 3) P1ANA 91H 92H XPAGE DPSEL 98H 2) SCON 99H A0H2) A8H2) A9H AAH SBUF P2 IEN0 IP0 SRELL OWDS WDTS .5 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-15 1997-08-01 Memory Organization C505 / C505C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) P3 FFH RD – SYSCON XX100X01B IEN1 IP1 SRELH 00H XX000000B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H 00H 00H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H2) B1H B8H2) B9H BAH WR – T1 EALE T0 INT1 INT0 TxD RxD RMAP CMOD – EX5 .4 – IEX5 EX4 .3 – IEX4 EX3 .2 – IEX3 XMAP1 XMAP0 ECAN .1 .1 SWI EADC .0 .0 IADC EXEN2 SWDT EX6 – – EXF2 – – TF2 .5 – IEX6 C0H2) IRCON C1H C2H C3H C4H C5H C6H C7H CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 COCA COCAL COCA COCAL COCA COCAL COCA COCAL H3 3 H2 2 H1 1 H0 0 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY BD .7 – .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .6 – .5 .5 .5 .5 .5 .5 – .5 .5 .5 .5 F0 – .5 – .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .4 – .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .3 – .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .2 – .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .1 – .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 .0 – C8H2) T2CON CAH CBH CCH CDH D0H 2) CRCL CRCH TL2 TH2 PSW D8H2) D9H DAH 00H ADCON0 00X00000B ADDAT ADST 00H XXXXXXXXB 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 3-16 1997-08-01 Memory Organization C505 / C505C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) ADCON1 01XXX000B ACC P4 B VR1 00H XXXXXX11B 00H C5H 05H 5) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DCH E0H2) E8H2) F0H2) FDH 3)4) ADCL1 ADCL0 – .7 – .7 1 0 .7 .6 – .6 1 0 .6 .5 – .5 0 0 .5 – .4 – .4 0 0 .4 – .3 – .3 0 0 .3 MX2 .2 – .2 1 1 .2 MX1 .1 RXDC .1 0 0 .1 MX0 .0 TXDC .0 1 1 .0 FCH3)4) VR0 FEH3)4) VR2 1) X means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual of the step C505 (eg. 01H for the first step). Semiconductor Group 3-17 1997-08-01 Memory Organization C505 / C505C Table 3-4 Contents of the CAN Registers in numeric order of their addresses (C505C only) Addr. Register Content Bit 7 n=1-FH after 1) Reset 2) F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 01H XXH XXH UUH 0UUU. 0 UUUUB UUH UUU1. 1111B UUH UUH UUH UUUU. U000B UUH UUH UUH UUUU. U000B UUH UUH UUH UUH UUH UUUU. U000B UUUU. UU00B ID4-0 DLC DIR ID20-18 ID12-5 0 XTD 0 0 0 0 MSGVAL RMTPND ID4-0 TXIE TXRQ ID20-18 ID12-5 0 RXIE MSGLST CPUUPD ID28-21 ID17-13 0 0 INTPND NEWDAT ID4-0 ID28-21 ID17-13 ID20-18 TEST BOFF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCE 0 0 EIE INTID SIE LEC2 IE LEC1 INIT LEC0 EWRN – RXOK TXOK SJW TSEG2 ID28-21 1 1 ID28-21 ID20-13 ID12-5 BRP TSEG1 1 1 1 0 0 0 F70CH UMLM0 F70DH UMLM1 F70EH F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG 1) The notation “n” (n= 1 to F) in the address definition defines the number of the related message object. 2) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation. Semiconductor Group 3-18 1997-08-01 Memory Organization C505 / C505C Table 3-4 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505C only) Addr. Register Content Bit 7 n=1-FH after 1) Reset 2) F7n7H F7n8H F7n9H F7nAH F7nBH DB0n DB1n DB2n DB3n DB4n XXH XXH XXH XXH XXH XXH XXH XXH .7 .7 .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 .0 .0 .0 F7nCH DB5n F7nDH DB6n F7nEH DB7n 1) The notation “n” (n= 1 to F) in the address definition defines the number of the related message object. 2) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation. Semiconductor Group 3-19 1997-08-01 External Bus Interface C505 / C505C 4 External Bus Interface The C505 allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C505 is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emissions of the system. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 1997-08-01 External Bus Interface C505 / C505C a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST IN PCL OUT PCL OUT valid b) S1 ALE PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST IN RD P2 P0 MCD02575 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 1997-08-01 External Bus Interface C505 / C505C 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: - whenever signal EA is active (low); or - whenever the program counter (PC) content is greater than 3FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN, Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C505 the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-3 1997-08-01 External Bus Interface C505 / C505C 4.4 ALE, Address Latch Enable The C505 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 and PC ≤ 3FFFH) and ALE is switched off by EALE=0, then, ALE will only go active during external data memory accesses (MOVX instructions). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX100X01B LSB 0 SYSCON 6 – 5 EALE 4 3 2 – 1 RMAP CMOD XMAP1 XMAP0 The shaded bits are not described in this section. Bit EALE Function Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. Reserved bits for future use. Read by CPU returns undefined values. – Semiconductor Group 4-4 1997-08-01 External Bus Interface C505 / C505C 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1) “Enhanced Hooks Technology” is a trademark and patent of MetaLink Corporation licenced to Siemens. Semiconductor Group 4-5 1997-08-01 External Bus Interface C505 / C505C 4.6 Eight Datapointers for Faster External Bus Access 4.6.1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be handled bytewise. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. 4.6.2 How the eight Datapointers of the C505 are realized Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C505 contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C505 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 4-3 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx. Special Function Register DPSEL (Address 92H) Bit No. MSB 7 92H – Reset Value : XXXXX000B LSB 0 .0 DPSEL 6 – 5 – 4 – 3 – 2 .2 1 .1 Bit DPSEL.2-0 Function Data pointer select bits DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7. Semiconductor Group 4-6 1997-08-01 External Bus Interface C505 / C505C ----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 .2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory MCD00779 DPTR0 DPH(83 H ) DPL(82 H) Figure 4-3 Accessing of External Data Memory via Multiple Datapointers 4.6.3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM. 4.6.4 Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H Semiconductor Group 4-7 1997-08-01 External Bus Interface C505 / C505C Example 1 : Using only One Datapointer (Code for a C501) Initialization Routine MOV MOV MOV MOV LOW(SRC_PTR), #0FFH HIGH(SRC_PTR), #1FH LOW(DES_PTR), #0A0H HIGH(DES_PTR), #2FH ;Initialize shadow_variables with source_pointer ;Initialize shadow_variables with destination_pointer Table Look-up Routine under Real Time Conditions PUSH PUSH MOV MOV ;INC ;CJNE MOVC MOV MOV MOV MOV INC MOVX MOV MOV POP POP ; DPL DPH DPL, LOW(SRC_PTR) DPH, HIGH(SRC_PTR) DPTR … A,@DPTR LOW(SRC_PTR), DPL HIGH(SRC_PTR), DPH DPL, LOW(DES_PTR) DPH, HIGH(DES_PTR) DPTR @DPTR, A LOW(DES_PTR), DPL HIGH(DES_PTR),DPH DPH DPL ; Number of cycles ;Save old datapointer 2 ; 2 ;Load Source Pointer 2 ; 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and 2 ;load destination_pointer 2 ; 2 ; 2 ;Increment destination_pointer ;(ex. time not relevant) – ;Transfer byte to destination address 2 ;Save destination_pointer 2 ; 2 ;Restore old datapointer 2 ; 2 Total execution time (machine cycles) : 28 Semiconductor Group 4-8 1997-08-01 External Bus Interface C505 / C505C Example 2 : Using Two Datapointers (Code for a C505) Initialization Routine MOV MOV MOV MOV DPSEL, #06H DPTR, #1FFFH DPSEL, #07H DPTR, #2FA0H ;Initialize DPTR6 with source pointer ;Initialize DPTR7 with destination pointer Table Look-up Routine under Real Time Conditions PUSH MOV ;INC ;CJNE MOVC MOV MOVX POP DPSEL DPSEL, #06H DPTR … A,@DPTR DPSEL, #07H @DPTR, A DPSEL ; Number of cycles ;Save old source pointer 2 ;Load source pointer 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and ;load destination_pointer 2 ;Transfer byte to destination address 2 ;Save destination pointer and ;restore old datapointer 2 Total execution time (machine cycles) : 12 ; The above example shows that utilization of the C505’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that a C505 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use. Semiconductor Group 4-9 1997-08-01 External Bus Interface C505 / C505C 4.7 ROM Protection for the C505 The C505-2R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C505-2R version has to define whether ROM protection has to be selected or not. The C505-2R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected as well as protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C505-2R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different : ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort. The behaviour of the move code instruction, when the code is executed from the external ROM, is in such a way that accessing a code byte from a protected on-chip ROM address is not possible. In this case the byte accessed will be invalid. 4.7.1 Unprotected ROM Mode If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-4 is used to read out the contents of the ROM. The AC timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). P1.0 - P1.7 P2.0 - P2.5 Address Port 0 Data OUT Inputs : PSEN, P2.6, P2.7 = VSS ALE, EA = VIH RESET = VIH1 MCD02626 Figure 4-4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. Then the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines. After a delay time, port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C505 must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. Semiconductor Group 4-10 1997-08-01 External Bus Interface C505 / C505C 4.7.2 Protected ROM Mode If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). RESET 6 CLP 1. ALE pulse after reset ALE Latch Port 0 Data for Addr. 0 Latch Data for Addr. 1 Data for Ad. X 16 - 1 3 CLP Latch Data for Addr. X 16 Latch Data for Addr. X 16 + 1 P3.5 Inputs : ALE = V SS PSEN, EA = V IH RESET = Low: Verify Error High: Verify ok MCT03289 Figure 4-5 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C505 outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way : 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal ROM address 0000H content of internal ROM address 0001H content of internal ROM address 0002H content of internal ROM address 000FH The C505-2R does not output any address information during the ROM verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the ROM content of the actual address. If an verify error is detected, the error Semiconductor Group 4-11 1997-08-01 External Bus Interface C505 / C505C condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the time when the following 16 bytes are checked. In ROM verification mode 2, the C505 must be provided with a system clock at the XTAL pins. Figure 4-6 shows an application example of an external circuitry which allows to verify a protected ROM inside the C505-2R in ROM verification mode 2. With RESET going inactive, the C505-2R starts the ROM verify sequence. Its ALE is clocking a 14-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the contents of the internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the verify operation. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal ROM has been handled, the C505-2R starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM verification. P3.5 Verify Detect Logic Carry CLK 2K 14 - Bit Address Counter S A0 - A13 ALE C505-2R & RESET Campare Code ROM V CC & Port 0 D0 - D7 V CC EA PSEN CS OE MCS03290 Figure 4-6 ROM Verification Mode 2 - External Circuitry Example Semiconductor Group 4-12 1997-08-01 External Bus Interface C505 / C505C 4.8 Version Registers Version registers are typically used for adapting the programming firmware to specific device characteristics such as ROM / OTP size etc. Three version registers are implemented in the C505. They can be read during normal program execution mode as mapped SFRs when the bit RMAP in SFR SYSCON is set. The first step of the C505 will contain the following information in the version registers. Version register 2 will be incremented with each new step of the C505. Contents of Version registers Name Version Register 0 Version Register 1 Version Register 2 Address FCH FDH FEH C505-2R C5H 05H 01H Semiconductor Group 4-13 1997-08-01 System Reset C505 / C505C 5 5.1 System Reset Hardware Reset Operation The hardware reset function incorporated in the C505 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. Additional to the hardware reset, which is applied externally to the C505, there are two internal reset sources, the watchdog timer and the oscillator watchdog. This chapter deals only with the external hardware reset. The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained, when VCC is applied, by connecting the reset pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. Semiconductor Group 5-1 1997-08-01 System Reset C505 / C505C The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. VCC + a) C505 RESET & b) C505 RESET VCC c) C505 RESET + MCS03291 Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0 to 4 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1,3 and 4) output a one (1). Port 2 lines output a zero (or one) after reset, if the EA is held low (or high). The internal SFRs are set to their initial states as defined in table 3-2. The contents of the internal RAM and XRAM of the C505 are not affected by a reset. After powerup the contents are undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-2 1997-08-01 System Reset C505 / C505C 5.2 Fast Internal Reset after Power-On The C505 uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C505 the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-2). Under worst case conditions (fast VCC rise time - e.g. 1µs, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VCC below 4.25V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-2, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-2, III). However, an externally applied reset still remains active (figure 5-2, IV) and the device does not start program execution (figure 5-2, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – – Termination of Software Power-Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficent in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin. Semiconductor Group 5-3 1997-08-01 Semiconductor Group RESET II III IV V Clock from RC-Oscillator; RESET at Ports Port remains in RESET because of active ext. RESET Signal Start of Program Execution MCD02627 Ports Undef. Figure 5-2 Power-On Reset of the C505 On-Chip Osc. RC Osc. 5-4 On-Chip Osc. starts; Final RESET Sequence by Osc.-WD; (max. 768 RC Clock Cycles) VCC RESET I Power On; undef.Ports typ. 18 µ s max. 34 µ s System Reset C505 / C505C 1997-08-01 System Reset C505 / C505C 5.3 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least one machine cycle; after this time the C505 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. in PCL OUT PCH OUT P2 ALE MCT02092 Figure 5-3 CPU Timing after Reset Semiconductor Group 5-5 1997-08-01 System Reset C505 / C505C 5.4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-4 shows the recommended oscillator circuit. C XTAL1 2 - 20 MHz C XTAL2 C = 20 pF 10 pF for crystal operation MCS03292 C505 Figure 5-4 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Semiconductor Group 5-6 1997-08-01 System Reset C505 / C505C To internal timing circuitry XTAL2 *) XTAL1 C505 C1 C2 *) Crystal or ceramic resonator MCS03293 Figure 5-5 On-Chip Oscillator Circuiry To drive the C505 with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-6. XTAL2 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL1. V CC N.C. C505 XTAL2 External Clock Signal XTAL1 MCS03294 Figure 5-6 External Clock Source Semiconductor Group 5-7 1997-08-01 System Reset C505 / C505C 5.5 System Clock Output For peripheral devices requiring a system clock, the C505 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON0), a clock signal with 1/6 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset. Special Function Register ADCON0 (Address D8H) MSB DFH BD Reset Value : 00X000000B LSB D8H MX0 ADCON0 Bit No. D8H DEH CLK DDH – DCH BSY DBH ADM DAH MX2 D9H MX1 The shaded bits are not used for clock output control. Bit CLK Function Clockout enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/6 of the oscillator frequency. Reserved bits for future use. Read by CPU returns undefined values. – The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 5-7. Note : During slow-down operation the frequency of the CLKOUT signal is divided by 32. Semiconductor Group 5-8 1997-08-01 System Reset C505 / C505C S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-7 Timing Diagram - System Clock Output Semiconductor Group 5-9 1997-08-01 On-Chip Peripheral Components C505 / C505C 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C505 except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET . Port 4 is 2-bit I/O port with CAN controller specific alternate functions. This port has no available bits at bit positions 2-7. 6.1.1 Port Structures The C505 generally allows digital I/O on 34 lines grouped into 4 bidirectional 8-bit ports and one 2-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P4 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. Therefore, the parallel I/O ports of the C505 can be grouped into three different types which are listed in table 6-1. Table 6-1 C505 Port Structure Types Type A B C Description Standard digital I/O ports which can also be used for external address/data bus. Standard multifunctional digital I/O port lines Mixed digital/analog I/O port lines with programmable analog input function Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 and port 4 to provide alternate functions for the serial interface and CAN controller I/O lines respectively, or are used as control outputs during external data memory accesses. The C505 provides eight analog input lines which are realized as mixed digital/analog inputs (type C). The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog input. Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set. Semiconductor Group 6-1 1997-08-01 On-Chip Peripheral Components C505 / C505C As already mentioned, port 1, 3 and 4 are provided for multiple alternate functions. These functions are listed in table 6-2: Table 6-2 Alternate Functions of Port 1, 3 and 4 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 Second / third Port Function Function Type AN0 / INT3 / CC0 AN1 / INT4 / CC1 AN2 / INT5 / CC2 AN3 / INT6 / CC3 AN4 AN5 / T2EX AN6 / CLKOUT AN7 / T2 RxD TxD INT0 INT1 T0 T1 WR RD TXDC RXDC C C C C C C C C B B B B B B B B B B Analog input channel 0 / External Interrupt 3 input / Capture/compare 0 input/output Analog input channel 1 / External Interrupt 4 input / Capture/compare 1 input/output Analog input channel 2 / External Interrupt 5 input / Capture/compare 2 input/output Analog input channel 3 / External Interrupt 6 input / Capture/compare 3 input/output Analog input channel 4 Analog input channel 5 / Timer 2 external reload/trigger input Analog input channel 6 / System clock output Analog input channel 7 / Timer 2 external count input Serial port’s receiver data input (asynchronous) or data input/ output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data memory read strobe CAN controller transmit output (C505C only) CAN controller receive input (C505C only) Prior to the description of the port type, specific port configurations the general port structure is described in the next section. Semiconductor Group 6-2 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P4) activate the "read-latch" signal, while others activate the "read-pin" signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-1 Basic Structure of a Port Circuitry Semiconductor Group 6-3 1997-08-01 On-Chip Peripheral Components C505 / C505C The output drivers of Port 1 to 4 have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1 to 4 the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are called "quasi-bidirectional". Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-2 Basic Output Driver Circuit of Ports 1 to 4 Semiconductor Group 6-4 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1’s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Addr./Data Read Latch Control & VCC =1 Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q MUX Read Pin MCS02434 Figure 6-3 Port 0 Circuitry Semiconductor Group 6-5 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.2.2 Port 1, Port 3 and Port 4 Circuitry The pins of ports 1, 3 and 4 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-2. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Read Latch Alternate Output Function VCC Internal Pull Up Arrangement Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS01827 Read Pin Alternate Input Function Figure 6-4 Ports 1, 3 and 4 The alternate functions of Port 4 pins are available for the C505C only. Semiconductor Group 6-6 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-3. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-5a) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Addr. Read Latch Control VCC Internal Pull Up Arrangement Port Pin Int. Bus D Bit Latch CLK Q MUX Q =1 Write to Latch Read Pin MCS03228 Figure 6-5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. Semiconductor Group 6-7 1997-08-01 On-Chip Peripheral Components C505 / C505C Addr. Control VCC Q _ 1 V SS Enable Analog Input (Bits of SFR P1ANA) Input Data (Read Pin) =1 =1 to A / D Converter MCT03295 Figure 6-7 Driver Circuit of Type C Port Pins Semiconductor Group 6-11 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.4 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-8 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain reqirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. S4 P1 XTAL2 P2 P1 S5 P2 P1 S6 P2 P1 S1 P2 P1 S2 P2 P1 S3 P2 Input sampled: e.g. MOV A, P1 P1 active for 1 State (driver transistor) Port Old Data New Data MCT03231 Figure 6-8 Port Timing Semiconductor Group 6-12 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.5 Port Loading and Interfacing The output buffers of ports 1 to 4 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the Data Sheet of the C505 or in chapter 10 of this User’s Manual. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1 to 4 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 as well as port 1 programmed to analog input function, however, have floating inputs when used for digital input. Semiconductor Group 6-13 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.1.6 Read-Modify-Write Feature of Ports 0 to 4 Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P0, P2 and P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in table 6-3 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. Table 6-3 "Read-Modify-Write"-Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y,C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P4 Decrement byte; e.g. DEC P5 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transitor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch. However, reading the latch rather than the pin will return the correct value of "1". Semiconductor Group 6-14 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.2 Timers/Counters The C505 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 6 oscillator periods, the counter rate is 1/6 of the oscillator frequency. In "counter" function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0, T1, or T2 (alternate functions of P3.4, P3.5 and P1.7 resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) to recognize a 1to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. 6.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the C505 are fully compatible with timer / counter 0 and 1 of the C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/ counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1. Semiconductor Group 6-15 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 .7 Reset Value : 00H Reset Value : 00H Reset Value : 00H Reset Value : 00H LSB 0 .0 TL0 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 8AH 8CH .7 .6 .5 .4 .3 .2 .1 .0 TH0 8BH .7 .6 .5 .4 .3 .2 .1 .0 TL1 8DH .7 .6 .5 .4 .3 .2 .1 .0 TH1 Bit TLx.7-0 x=0-1 Function Timer/counter 0/1 low register Operating Mode Description 0 1 2 3 "TLx" holds the 5-bit prescaler value. "TLx" holds the lower 8-bit part of the 16-bit timer/counter value. "TLx" holds the 8-bit timer/counter value. TL0 holds the 8-bit timer/counter value; TL1 is not used. THx.7-0 x=0-1 Timer/counter 0/1 high register Operating Mode Description 0 1 2 3 "THx" holds the 8-bit timer/counter value. "THx" holds the higher 8-bit part of the 16-bit timer/counter value "THx" holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used. Semiconductor Group 6-16 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register TCON (Address 88H) Bit No. MSB 7 8FH 88H TF1 6 8EH TR1 5 8DH TF0 4 8CH TR0 3 8BH IE1 2 8AH IT1 1 89H IE0 Reset Value : 00H LSB 0 88H IT0 TCON The shaded bits are not used for controlling timer/counter 0 and 1. Bit TR0 TF0 Function Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 TF1 Semiconductor Group 6-17 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register TMOD (Address 89H) Bit No. 89H MSB 7 Gate Reset Value : 00H LSB 0 M0 TMOD 6 C/T 5 M1 4 M0 3 Gate 2 C/T 1 M1 Timer 1 Control Timer 0 Control Bit GATE Function Gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. Counter or timer select bit Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). Mode select bits M1 0 M0 0 Function 8-bit timer/counter: "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows Timer 0 : TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops C/T M1 M0 0 1 1 0 1 1 Semiconductor Group 6-18 1997-08-01 On-Chip Peripheral Components C505 / C505C 6.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-9. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3). OSC ÷6 C/T = 0 TL0 (5 Bits) C/T = 1 TH0 (8 Bits) TF0 Interrupt P3.4/T0 Control Gate =1 _ 1 Machine Cycle b) Transition-Activated Interrupt High-Level Threshold e.g. P3.x/INTx Low-Level Threshold > 1 Machine Cycle Transition to be detected > 1 Machine Cycle MCT01921 Figure 7-5 External Interrupt Detection Semiconductor Group 7-16 1997-08-01 Interrupt System C505 / C505C 7.5 Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. If an interrupt of equal or higer priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP0, IP1 the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV). Thus a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles. Semiconductor Group 7-17 1997-08-01 Fail Save Mechanisms C505 / C505C 8 Fail Save Mechanisms The C505 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to approx. 412.5 ms at 16 MHz. – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. 8.1 Programmable Watchdog Timer To protect the system against software upset, the user’s program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of fOSC/12 upto fOSC/192. The machine clock of the C505 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. Figure 8-1 shows the block diagram of the watchdog timer unit. 0 7 WDTL 14 8 WDTH f OSC / 6 2 16 WDT Reset - Request IP0 (A9 H ) OWDS WDTS WDTPSEL External HW Reset 76 WDTREL (86 H ) Control Logic WDT SWDT 0 IEN0 (A8 H ) IEN1 (B8 H ) MCB03306 Figure 8-1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8-1 1997-08-01 Fail Save Mechanisms C505 / C505C 8.1.1 Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C505. There is a prescaler available, which is software selectable and defines the input clock rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at fOSC = 12 and 16 MHz. Special Function Register WDTREL (Address 86H) MSB Bit No. 7 86H WDT PSEL Reset Value : 00H LSB 0 WDTREL 6 5 4 3 Reload Value 2 1 Bit WDTPSEL Function Watchdog timer prescaler select bit. When set, the watchdog timer is clocked through an additional divide-by16 prescaler . Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT. WDTREL.6 - 0 Table 8-1 Watchdog Timer Time-Out Periods WDTREL 00H 80H 7FH Time-Out Period Comments This is the default value Maximum time period Minimum time period fOSC = 12 MHz 32.768 ms 524.2 ms 256 µs fOSC = 16 MHz 24.576 ms 393.2 ms 192 µs Semiconductor Group 8-2 1997-08-01 Fail Save Mechanisms C505 / C505C 8.1.2 Watchdog Timer Control / Status Flags The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one status flag (located in SFR IP0). Special Function Register IEN0 (Address A8H) Special Function Register IEN1 (Address B8H) Special Function Register IP0 (Address A9H) MSB AFH A8H EAL BFH B8H Bit No. A9H Reset Value : 00H Reset Value : 00H Reset Value : 00H LSB A8H EX0 B8H IEN1 IEN0 AEH WDT BEH ADH ET2 BDH EX6 5 IP0.5 ACH ES BCH EX5 4 IP0.4 ABH ET1 BBH EX4 3 IP0.3 AAH EX1 BAH EX3 2 IP0.2 A9H ET0 B9H EXEN2 SWDT 7 6 ECAN EADC 1 IP0.1 0 IP0.0 OWDS WDTS IP0 The shaded bits are not used for fail save control. Bit WDT Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. Watchdog timer start flag. Set to activate the Watchdog Timer. When directly set after setting WDT, a watchdog timer refresh is performed. Watchdog timer status flag. Set by hardware when a watchdog Timer reset occured. Can be cleared and set by software. SWDT WDTS Immediately after start, the Watchdog Timer is initialized to the reload value programmed in WDTREL.0-WDTREL.6. After an external HW reset, an oscillator watchdog power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time. Semiconductor Group 8-3 1997-08-01 Fail Save Mechanisms C505 / C505C 8.1.3 Starting the Watchdog Timer The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in IP0 is set). A refresh of the watchdog timer is done by setting bits WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). It is not possible to use the idle mode in combination with the watchdog timer function. Therefore, even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally. Semiconductor Group 8-4 1997-08-01 Fail Save Mechanisms C505 / C505C 8.1.4 Refreshing the Watchdog Timer At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (IEN0.6) and by the next instruction setting SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB SWDT). This double-instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. The reload register WDTREL can be written to at any time, as already mentioned. Therefore, a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer. Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software. 8.1.5 Watchdog Reset and Watchdog Status Flag lf the software fails to refresh the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler selection (either 8 cycles or 128 cycles). This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS (watchdog timer status, bit 6 in SFR IP0) is set. Figure 8-2 shows a block diagram of all reset requests in the C505 and the function of the watchdog status flags. The WDTS flag is a flip-flop, which is set by a watchdog timer reset and cleared by an external HW reset. Bit WDTS allows the software to eamine from which source the reset was activated. The watchdog timer status flag can also be cleared by software. OWD Reset Request WDT Reset Request Set Set IP0 (A9 H ) >1 OWDS WDTS RESET Clear External HW Reset Request Synchro- Internal Reset nization Internal Bus MCT03307 Figure 8-2 Watchdog Timer Status Flags and Reset Requests Semiconductor Group 8-5 1997-08-01 Fail Save Mechanisms C505 / C505C 8.2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog reset is released and the part starts program execution from address 0000H again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. – Control of external wake-up from software power-down mode When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Note: The oscillator watchdog unit is always enabled. Figure 8-3 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator. It also shows the additional provisions for integration of the wake-up from power down mode. Special Function Register IP0 (Address A9H) MSB Bit No. 7 A9H Reset Value : 00H LSB 0 IP0.0 IP0 6 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 OWDS WDTS The shaded bits are not used for fail save control. Bit OWDS Function Oscillator Watchdog Status Flag. Set by hardware when an oscillator watchdog reset occured. Can be set and cleared by software. Semiconductor Group 8-6 1997-08-01 Fail Save Mechanisms C505 / C505C EWPD (PCON1.7) P4.1 / RXDC P3.2 / INT0 Control Logic WS (PCON1.4) Power - Down Mode Activated Power-Down Mode Wake - Up Interrupt Control Logic Internal Reset Start / Stop RC Oscillator f RC 3 MHz Start / Stop 10 f1 Frequency Comparator f 2 1 XTAL1 XTAL2 On-Chip Oscillator f2 IP0 (A9 H ) OWDS Int. Clock MCB03308 Figure 8-3 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 10 and compared to the on-chip oscillator's frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal clock system to the output of the RC oscillator. This means that the part is being clocked even if the on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state. The reset is performed because clock is available from the RC oscillator. This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions: The Watchdog Timer Status flag WDTS is not reset (the Watchdog Timer is, however, stopped); and bit OWDS is set. This allows the software to examine error conditions detected by the Watchdog unit even if meanwhile an oscillator failure occured. The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the frequency derived from the on-chip oscillator is again higher than the reference, the watchdog starts a final reset sequence which takes typ. 1 ms. Within that time the clock is still supplied by the RC Semiconductor Group 8-7 1997-08-01 Fail Save Mechanisms C505 / C505C oscillator and the part is held in reset. This allows a reliable stabilization of the on chip oscillator. After that, the watchdog switches the clock supply back to the on-chip oscillator and releases the oscillator watchdog reset. If no other reset is applied at this time the part will start program execution. If an external reset or a watchdog timer reset is active, however, the device will retain the reset state until the other reset request disappears. Furthermore, the status flag OWDS is set if the oscillator watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS). If software power-down mode is activated the RC oscillator and the on-chip oscillator are stopped. Both oscillators are again started in power-down mode when a low level is detected at either the P3.2/INT0 input pin or the P4.1/RXDC pin and when bit EWPD in SFR PCON1 is set (wake-up from power-down mode enabled). The wake-up source is chosen from one of P3.2/INT0 and P4.1/RXDC by bit WS in SFR PCON1. In this case the oscillator watchdog does not execute an internal reset during startup of the on-chip oscillator. After the start-up phase of the on-chip oscillator, the watchdog generates a power-down mode wake-up interrupt. Detailed description of the wake-up from software power-down mode is given in section 9.4.2. Fast Internal Reset after Power-On The C505 can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally the members of the 8051 family (e. g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an undefined state which could have severe effects e.g. to actuators connected to port pins. In the C505 the oscillator watchdog unit avoids this situation. After power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). Then the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip. This allows correct resetting of the part and brings all ports to the defined state (see also chapter 5 of this manual). Semiconductor Group 8-8 1997-08-01 Power Saving Modes C505 / C505C 9 Power Saving Modes The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. 9.1 Power Saving Mode Control Registers The functions of the power saving modes are controlled by bits which are located in the special function registers PCON and PCON1. The SFR PCON is located at SFR address 87H. PCON1 is located in the mapped SFR area (RMAP=1) at SFR address 88H. Bit RMAP, which controls the access to the mapped SFR area, is located in SFR SYSCON (B1H). The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle. For this, an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. Special Function Register PCON (Address 87H) Bit No. MSB 7 87H SMOD Reset Value : 00H LSB 0 IDLE PCON 6 PDS 5 IDLS 4 SD 3 GF1 2 GF0 1 PDE The function of the shaded bit is not described in this section. Symbol PDS Function Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode. Slow down mode bit When set, the slow down mode is enabled General purpose flag General purpose flag Power down enable bit When set, starting of the power down is enabled Idle mode enable bit When set, starting of the idle mode is enabled IDLS SD GF1 GF0 PDE IDLE Semiconductor Group 9-1 1997-08-01 Power Saving Modes C505 / C505C Special Function Register PCON1 (Mapped Address 88H) Bit No. MSB 7 88H EWPD Reset Value : 0XX0XXXXB LSB 0 – PCON1 6 – 5 – 4 WS 3 – 2 – 1 – Symbol EWPD Function External wake-up from power down enable bit Setting EWPD before entering power down mode, enables the external wakeup from power down mode capability (more details see section 9.4.2). Wake-up from power-down source select WS = 0 : wake-up via pin P3.2/INT0. WS = 1 : wake-up via pin P4.1/RXDC. Pin P3.2/INT0 is selected as wake-up source after reset. Reserved bits for future use. Read by CPU returns undefined values. WS – Semiconductor Group 9-2 1997-08-01 Power Saving Modes C505 / C505C 9.2 Idle Mode In the idle mode the oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the CAN controller (C505C only), and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature depends on the number of peripherals running. If all timers are stopped and the A/D converter, and the serial interfaces are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode ICC. Thus, the user has to take care which peripheral should continue to run and which has to be stopped during idle mode. Also the state of all port pins – either the pins controlled by their latches or controlled by their secondary functions – depends on the status of the controller when entering idle mode. Normally, the port pins hold the logical state they had at the time when the idle mode was activated. If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on. This especially applies to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN are held at logic high levels. As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either for a predefined time, or until an external event reverts the controller to normal operation, as discussed below. The watchdog timer is the only peripheral which is automatically stopped during idle mode. Semiconductor Group 9-3 1997-08-01 Power Saving Modes C505 / C505C The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these register bits is read the value that appears is 0. This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer's task of system protection without effect. Note: PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is obtained by byte-handling instructions, as shown in the following example: ORL ORL PCON,#00000001B PCON,#00100000B ;Set bit IDLE, bit IDLS must not be set ;Set bit IDLS, bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode. There are two ways to terminate the idle mode: – The idle mode can be terminated by activating any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLS. – The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset. Semiconductor Group 9-4 1997-08-01 Power Saving Modes C505 / C505C 9.3 Slow Down Mode Operation In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current, a reduction of the operating frequency results in reduced power consumption. In the slow down mode all signal frequencies that are derived from the oscillator clock are divided by 32. The slow down mode is activated by setting the bit SD in SFR PCON. If the slow down mode is enabled, the clock signals for the CPU and the peripheral units are reduced to 1/32 of the nominal system clock rate. The controller actually enters the slow down mode after a short synchronization period (max. two machine cycles). The slow down mode is terminated by clearing bit SD. The slow down mode can be combined with the idle mode by performing the following double instruction sequence: ORL ORL PCON,#00000001B PCON,#00110000B ; preparing idle mode: set bit IDLE (IDLS not set) ; entering idle mode combined with the slow down mode: ; (IDLS and SD set) There are two ways to terminate the combined Idle and Slow Down Mode : – The idle mode can be terminated by activation of any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD. Nevertheless the slow down mode keeps enabled and if required has to be terminated by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow-down mode power saving. – The other possibility of terminating the combined idle and slow down mode is a hardware reset. Since the oscillator is still running, the hardware reset has to be held active for only two machine cycles for a complete reset. Semiconductor Group 9-5 1997-08-01 Power Saving Modes C505 / C505C 9.4 Software Power Down Mode In the software power down mode, the RC oscillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE and PSEN held at logic low level (see table 9–1). In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level before the power down mode is terminated. The software power down mode can be left either by an active reset signal or by a low signal at one of the wake-up source pins. Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state. Using either the P3.2/INT0 pin or the P4.1/RXDC pin for power down mode exit starts the RC oscillator and the on-chip oscillator and maintains the state of the SFRs, which have been frozen when power down mode is entered. Leaving power down mode should not be done before VCC is restored to its nominal operating level. 9.4.1 Invoking Software Power Down Mode The software power down mode is entered by two consecutive instructions. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, does not initiate the power down mode. Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0. This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly ”freeze” the chip's activity in an undesired status. PCON is not a bit-addressable register, so the above mentioned sequence for entering the power down mode is obtained by byte-handling instructions, as shown in the following example: ORL ORL PCON,#00000010B PCON,#01000000B ;set bit PDE, bit PDS must not be set ;set bit PDS, bit PDE must not be set, enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode. When the double instruction sequence shown above is used, the power down mode can only be left by a reset operation. If the external wake-up from power down capability has also to be used, its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above. ORL ORL ANL SYSCON,#00010000B PCON1,#80H SYSCON,#11101111B ;set RMAP ;enable wake-up from power down via P3.2/INT0 ;reset RMAP (for future SFR accesses) Setting EWPD automatically disables all interrupts still maintaining all actual values of the interrupt enable bits. In the above sequence the value of register PCON1 should be modified for choosing a wake-up via the P4.1/RXDC (bit PCON1.4 should be set). Note : Before entering the power down mode, an A/D conversion in progress must be stopped. Semiconductor Group 9-6 1997-08-01 Power Saving Modes C505 / C505C 9.4.2 Exit from Software Power Down Mode If power down mode is exit via a hardware reset, the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal that terminates the power down mode also restarts the RC oscillator and the on-chip oscillatror. The reset operation should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). Figure 9-1 shows the procedure which must is executed when power down mode is left via the P3.2/INT0 or the P4.1/RXDC wake-up capability. Execution of interrupt at 007B H 4) P3.2 / INT0 or P4.1 / RXDC Power Down Mode 1) Latch Phase 2) Watchdog Circuit Oscillator Start-Up Phase 3) min. 10 µs Detailed Timing of Beginning of Phase 4 ALE PSEN P2 P0 Invalid Address typ. 5 ms RETI Insruction 00H 7BH 1 st instr. of ISR Invalid Address / Data MCT03309 Figure 9-1 Wake-up from Power Down Mode Procedure When the power down mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to entering power down mode and bit WS in SFR PCON1 is cleared, the power down mode can be exit via INT0 while executing the following procedure : 1. In power down mode pin P3.2/INT0 must be held at high level. 2. Power down mode is left when P3.2/INT0 goes low for at least 10 µs (latch phase). After this delay the internal RC oscillator and the on-chip oscillator are started, the state of pin P3.2/INT0 is internally latched, and P3.2/INT0 can be set again to high level if required. Thereafter, the oscillator watchdog unit controls the wake-up procedure in its start-up phase. Semiconductor Group 9-7 1997-08-01 Power Saving Modes C505 / C505C 3. The oscillator watchdog unit starts operation. When the on-chip oscillator clock is detected for stable nominal frequency, the microcontroller starts again with its operation initiating the power down wake-up interrupt. The interrupt address of the first instruction to be executed after wakeup is 007BH. ALE and PSEN are in their power-down state up to this time. At the end of phase 3 the CPU processes the interrupt call and during these two machine cycles, ALE and PSEN behave as shown in figure 9-1 (i.e. at the begining of phase 4). Instruction fetches during the interrupt call are, however, discarded. 4. After the RETI instruction of the power down wake-up interrupt routine has been executed, the instruction which follows the initiating power down mode double instruction sequence will be executed. The peripheral units timer 0/1/2 , CAN controller, and WDT are frozen until end of phase 4. All interrupts of the C505 are disabled from phase 2) until the end of phase 4). Other Interrupts can be first handled after the RETI instruction of the wake-up interrupt routine. The procedure to exit the software power down mode via the P4.1/RXDC pin is identical to the above procedure except that in this case pin P4.1/RXDC replaces pin P3.2/INT0, and bit WS in SFR PCON1 should be set prior to entering software power down mode. 9.5 State of Pins in Software Initiated Power Saving Modes In the idle mode and in the power down mode the port pins of the C505 have a well defined status which is listed in the following table 9-1. This state of some pins also depends on the location of the code memory (internal or external). Table 9-1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Internal Code Memory Idle ALE PSEN PORT 0 PORT 2 PORT 1, 3, 4 High High Data Data Data / alternate outputs Power Down Low Low Data Data Data / last output Last Instruction Executed from External Code Memory Idle High High Float Address Data / alternate outputs Power Down Low Low Float Data Data / last output Semiconductor Group 9-8 1997-08-01 Device Specifications C505 / C505C 10 Device Specifications 10.1 Absolute Maximum Ratings Ambient temperature under bias (TA) .............................................................. – 40 ˚C to + 125 ˚C Storage temperature (TST) ...............................................................................– 65 ˚C to + 150 ˚C Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ..............................................– 0.5 V to VCC + 0.5 V Input current on any pin during overload condition..........................................– 10 mA to + 10 mA Absolute sum of all input currents during overload condition ..........................| 100 mA | Power dissipation.............................................................................................TBD Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Semiconductor Group 10-1 1997-08-01 Device Specifications C505 / C505C 10.2 DC Characteristics VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C TA = – 40 to 125 °C for the SAB-C505 for the SAF-C505 for the SAH-C505 for the SAK-C505 Parameter Input low voltages all except EA, RESET EA pin RESET pin Input high voltages all except XTAL1, RESET XTAL1 pin RESET pin Output low voltages Ports 1, 2, 3, 4 Port 0, ALE, PSEN Output high voltages Ports 1, 2, 3, 4 Port 0 in external bus mode, ALE, PSEN Logic 0 input current Ports 1, 2, 3, 4 Logical 0-to-1 transition current Ports 1, 2, 3, 4 Input leakage current Port 0, AN0-7 (Port 1), EA Pin capacitance Overload current Symbol min. Limit Values max. Unit Test Condition VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH VOH2 – 0.5 – 0.5 – 0.5 0.2 VCC - 0.1 V 0.2 VCC - 0.3 V 0.2 VCC + 0.1 V V V V V V V V V V µA µA – – – – – – 0.2 VCC + 0.9 VCC + 0.5 0.7 VCC VCC + 0.5 0.6 VCC VCC + 0.5 – – 2.4 0.9 VCC 2.4 0.9 VCC – 10 – 65 0.45 0.45 – – – – – 70 – 650 IOL = 1.6 mA 1) IOL = 3.2 mA 1) IOH = – 80 µA IOH = – 10 µA IOH = – 800 µA IOH = – 80 µA 2) VIN = 0.45 V VIN = 2 V IIL ITL ILI CIO IOV – – – ±1 10 ±5 µA pF mA 0.45 < VIN < VCC fc = 1 MHz, TA = 25 °C 8) 9) Semiconductor Group 10-2 1997-08-01 Device Specifications C505 / C505C Power Supply Current Parameter Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled Power down current 16 MHz 20 MHz 16 MHz 20 MHz 16 MHz 20 MHz 16 MHz 20 MHz Symbol Limit Values typ. 10) max.11) TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA µA 26 32 14.8 17.8 TBD TBD TBD TBD TBD Unit Test Condition ICC ICC ICC ICC ICC ICC ICC ICC IPD VCC = 5 V 4) VCC = 5 V 5) VCC = 5 V 6) VCC = 5 V 7) VCC = 2…5.5 V3) 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VSS ; RESET = VCC ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. 4) ICC (active mode) is measured with: XTAL1 driven with tR , tF = 5 ns , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; EA = Port 0 = VCC ; RESET = VSS ; all other pins are disconnected. ICC would be slightly higher if the crystal oscillator is used (approx. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected; 6) ICC (active mode with slow-down mode) is measured : TBD 7) ICC (idle mode with slow-down mode) is measured : TBD 8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 9) Not 100% tested, guaranteed by design characterization 10)The typical ICC values are periodically measured at TA = + 25 ˚C but not 100% tested. 11)The maximum ICC values are measured under worst case conditions (TA = 0 ˚C or – 40 ˚C and VCC = 5.5 V). Semiconductor Group 10-3 1997-08-01 Device Specifications C505 / C505C 10.3 A/D Converter Characteristics VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C TA = – 40 to 125 °C for the SAB-C505 for the SAF-C505 for the SAH-C505 for the SAK-C505 4 V ≤ VAREF ≤ VCC + 0.1 V ; VSS – 0.1 V ≤ VAGND ≤ Vss + 0.2 V Parameter Analog input voltage Sample time Symbol Limit Values min. max. Unit V ns Test Condition 1) VAIN tS VAGND 0.2 – VAREF + 0.2 64 x tIN 32 x tIN 16 x tIN 8 x tIN 320 x tIN 160 x tIN 80 x tIN 40 x tIN ±2 -1 Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 2) Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 3) VSS+0.5V ≤ VAIN ≤ VCC-0.5V 4) Conversion cycle time tADCC – ns Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. TUE – – – – LSB RAREF RASRC CAIN tADC / 500 kΩ tS / 500 -1 50 pF kΩ tADC in [ns] tS in [ns] 6) 5) 6) 2) 6) Clock calculation table : Clock Prescaler ADCL1, 0 Ratio ÷ 32 ÷ 16 ÷8 ÷4 1 1 0 0 1 0 1 0 tADC 32 x tIN 16 x tIN 8 x tIN 4 x tIN tS 64 x tIN 32 x tIN 16 x tIN 8 x tIN tADCC 320 x tIN 160 x tIN 80 x tIN 40 x tIN Further timing conditions : tADC min = 800 ns tIN = 1 / fOSC = tCLP Semiconductor Group 10-4 1997-08-01 Device Specifications C505 / C505C Notes: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively. 2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE (max.) is tested at –40 ≤ TA ≤ 125 °C ; VCC ≤ 5.5 V; VAREF ≤ VCC + 0.1 V and VSS ≤ VAGND. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Semiconductor Group 10-5 1997-08-01 Device Specifications C505 / C505C 10.4 AC Characteristics (16 MHz) for C505 VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C for the SAB-C505 for the SAF-C505 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 16-MHz clock Duty Cycle 0.4 to 0.6 min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Unit Variable Clock 1/CLP = 2 MHz to 16 MHz min. CLP - 15 max. – ns ns ns ns ns ns max. – – – 75 – – 38 – 15 – 95 – tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV tAVIV tAZPL *) 48 10 10 – 10 73 – 0 – 20 – -5 TCLHmin -15 – TCLHmin -15 – – 2 CLP - 50 TCLLmin -15 – CLP+ – TCLHmin -15 – 0 – TCLLmin - 5 – -5 CLP+ ns TCLHmin- 50 – – ns ns TCLLmin -10 ns 2 CLP + ns TCLHmin -55 – ns Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 10-6 1997-08-01 Device Specifications C505 / C505C AC Characteristics (16 MHz) for C505 (cont’d) External Data Memory Characteristics Parameter Symbol 16-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. – – – 100 – 51 200 200 103 – 40 – – – 0 Limit Values Variable Clock 1/CLP= 2 MHz to 16 MHz Unit min. 3 CLP - 30 3 CLP - 30 CLP- 15 – 0 – – – CLP + TCLLmin - 15 2 CLP - 30 TCLHmin - 15 TCLLmin - 20 3 CLP + TCLLmin - 50 TCLHmin - 20 – max. – – – 2 CLP+ TCLHmin - 50 – CLP - 12 4 CLP - 50 4 CLP + TCLHmin -75 CLP+ TCLLmin+ 15 – TCLHmin + 15 – – – 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 158 158 48 – 0 – – – 73 95 10 5 163 5 – Semiconductor Group 10-7 1997-08-01 Device Specifications C505 / C505C AC Characteristics (16 MHz) for C505 (cont’d) External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 62.5 25 25 – – 0.4 25 max. 62.5 – – 10 10 0.6 37.5 Variable CPU Clock 1/CLP = 2 to 16 MHz min. 62.5 25 25 – – 25 / CLP CLP * DCmin max. 500 CLP - TCLL CLP - TCLH 10 10 1 - 25 / CLP ns ns ns ns ns – Unit tR tF DC TCL CLP * DCmax ns Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. Semiconductor Group 10-8 1997-08-01 Device Specifications C505 / C505C 10.5 AC Characteristics (20 MHz) for C505 VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C for the SAB-C505 for the SAF-C505 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 20-MHz clock Duty Cycle 0.5 to 0.5 min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Unit Variable Clock 1/CLP = 2 MHz to 20 MHz min. CLP - 15 max. – ns ns ns ns ns ns max. – – – 55 – – 25 – 20 – 65 – tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV *) tAVIV tAZPL 35 10 10 – 10 60 – 0 – 20 – -5 TCLHmin - 15 – TCLHmin - 15 – – 2 CLP - 45 TCLLmin - 15 – CLP + – TCLHmin - 15 – 0 – TCLLmin - 5 – -5 CLP + ns TCLHmin - 50 – TCLLmin - 5 – ns ns ns 2 CLP + ns TCLHmin - 60 – ns Interfacing the C505 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 10-9 1997-08-01 Device Specifications C505 / C505C AC Characteristics (20 MHz) for C505 (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 20-MHz clock Duty Cycle 0.5 to 0.5 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. – – – 75 – 38 150 150 90 – 40 – – – 0 Variable Clock 1/CLP = 2 MHz to 20 MHz min. 3 CLP-30 3 CLP-30 CLP-15 – 0 – – – CLP + TCLLmin-15 2 CLP-30 TCLHmin-15 TCLLmin-20 3 CLP+ TCLLmin-50 TCLHmin-20 – max. – – – 2 CLP+ TCLHmin-50 – CLP-12 4 CLP-50 4 CLP + TCLHmin-75 CLP + TCLLmin+15 – TCLHmin+15 – – – 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 120 120 35 – 0 – – – 60 70 10 5 125 5 – Semiconductor Group 10-10 1997-08-01 Device Specifications C505 / C505C External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 2 MHz to 20 MHz min. Oscillator period High time Low time Rise time Fall time CLP TCLH TCLL tR tF 50 25 25 – – max. 500 CLP-TCLL CLP-TCLH 10 10 ns ns ns ns ns Unit Note: The 20 MHz values in the tables are given as an example for a typical duty cycle of the oscillator clock of 50 %. Semiconductor Group 10-11 1997-08-01 Device Specifications C505 / C505C t LHLL ALE t AVLL t LLIV t PLPH t LLPL t PLIV PSEN t AZPL t LLAX t PXAV t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Program Memory Read Cycle Semiconductor Group 10-12 1997-08-01 Device Specifications C505 / C505C t WHLH ALE PSEN t LLDV t LLWL RD t RLRH t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL Data IN t RHDZ t RHDX A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Data Memory Read Cycle Semiconductor Group 10-13 1997-08-01 Device Specifications C505 / C505C t WHLH ALE PSEN t LLWL WR t WLWH t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN Port 0 t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Data Memory Write Cycle TCL H tR tF XTAL1 TCL L CLP 0.7 V CC 0.2 V CC - 0.1 MCT03310 External Clock Drive on XTAL1 Semiconductor Group 10-14 1997-08-01 Device Specifications C505 / C505C 10.6 ROM Verification Characteristics for C505-2R ROM Verification Mode 1 Parameter Address to valid data Symbol min. Limit Values max. 5 CLP ns – Unit tAVQV P1.0 - P1.7 P2.0 - P2.5 Address t AVQV Port 0 Address : P1.0 - P1.7 = A0 - A7 P2.0 - P2.5 = A8 - A13 Data : P0.0 - P0.7 = D0 - D7 Data OUT Inputs : P2.6, P2.7, PSEN = VSS ALE, EA = V IH RESET = VIH1 MCT02629 ROM Verification Mode 1 Semiconductor Group 10-15 1997-08-01 Device Specifications C505 / C505C ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ CLP 6 CLP – – TCLH – max. – – 2 CLP – – 6 ns ns ns ns ns MHz – – – 4 CLP – 4 Unit tAWD tACY tDVA tDSA tAS 1/ CLP t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.5 MCT02613 ROM Verification Mode 2 Semiconductor Group 10-16 1997-08-01 Device Specifications C505 / C505C VCC -0.5 V 0.2 VCC+0.9 Test Points 0.2 VCC -0.1 MCT00039 0.45 V AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. AC Testing: Input, Output Waveforms VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points VOH -0.1 V VOL +0.1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ±20 mA AC Testing : Float Waveforms Crystal Oscillator Mode C XTAL2 2 - 20 MHz C XTAL1 Driving from External Source N.C. XTAL2 External Oscillator Signal XTAL1 Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance) MCS03311 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 10-17 1997-08-01 Device Specifications C505 / C505C 10.7 Package Information Plastic Package, P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Pack) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 10-18 1997-08-01 GPM05622 Index C505 / C505C 11 Index Note: Bold page numbers refer to the main definition part of SFRs or SFR bits. A A/D converter . . . . . . . . . . . . . 6-98 to 6-109 Analog input pin selection. . . . . . . . 6-109 Block Diagram . . . . . . . . . . . . . . . . . 6-99 Clock selection . . . . . . . . . . . . . . . . 6-104 Conversion time calculation . . . . . . 6-108 Conversion timing . . . . . . . . . . . . . . 6-105 General operation . . . . . . . . . . . . . . . 6-98 Registers. . . . . . . . . . . . . . 6-100 to 6-103 System clock relationship . . . . . . . . 6-106 A/D converter characteristics . . 10-5 to 10-6 Absolute maximum ratings . . . . . . . . . . 10-1 AC . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 AC characteristics . . . . . . . . . 10-7 to 10-12 AC Testing Float waveforms . . . . . . . . . . . . . . . 10-18 Input/output waveforms . . . . . . . . . 10-18 ACC . . . . . . . . . . . . . . . . . . . 2-3, 3-12, 3-17 ADCL0 . . . . . . . . . . . . . . . . . . . . . . . . 6-102 ADCL1 . . . . . . . . . . . . . . . . . . . 3-17, 6-102 ADCON0 3-12, 3-13, 3-16, 5-8, 6-46, 6-101 ADCON1 . . . . . . . . . . . . . 3-12, 3-17, 6-101 ADDAT . . . . . . . . . . . . . . . 3-12, 3-16, 6-100 ADM . . . . . . . . . . . . . . . . . . . . . 3-16, 6-101 ADST . . . . . . . . . . . . . . . . 3-12, 3-16, 6-100 ALE signal . . . . . . . . . . . . . . . . . . . . . . . 4-4 B B . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-12, 3-17 Basic CPU timing . . . . . . . . . . . . . . . . . . 2-5 BD . . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-46 Block diagram. . . . . . . . . . . . . . . . . . . . . 2-2 BOFF . . . . . . . . . . . . . . . . . . . . . 3-18, 6-68 BRP . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-71 BSY . . . . . . . . . . . . . . . . . . . . . 3-16, 6-101 BTR0 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-71 BTR1 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-71 C C/T . . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-18 CAN controller . . . . . . . . . . . . . 6-60 to 6-97 Access control . . . . . . . . . . . . . . . . . . 3-3 Basic function . . . . . . . . . . . . . . . . . . 6-61 Bit time calculation . . . . . . . . . . . . . . 6-92 Bit timing configuration . . . . . . . . . . . 6-90 Block diagram . . . . . . . . . . . . . . . . . 6-62 Configuration examples . . . . . . . . . . 6-95 Idle mode . . . . . . . . . . . . . . . . . . . . . 6-94 Initialization . . . . . . . . . . . . . . . . . . . 6-88 Interface signals . . . . . . . . . . . . . . . . 6-97 Interrupt handling . . . . . . . . . . . . . . . 6-93 Power down mode . . . . . . . . . . . . . . 6-94 Registers . . . . . . . . . . . . . . . 6-65 to 6-81 Address map . . . . . . . . . . . . . . . . 6-66 General registers . . . . . . . . . . . . . 6-65 Message object address map. . . . 6-75 Message object handling . 6-81 to 6-87 Message object registers . . . . . . . 6-75 Slow down mode . . . . . . . . . . . . . . . 6-94 Synchronization . . . . . . . . . . . . . . . . 6-92 CCE . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 CCEN. . . . . . . . . . . . . . . . . 3-13, 3-16, 6-29 CCH1 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCH2 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCH3 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL1 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL2 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL3 . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CLK . . . . . . . . . . . . . . . . . . . . . . . 3-16, 5-8 CLKOUT . . . . . . . . . . . . . . . . . . . 3-15, 5-8 CMOD . . . . . . . . . . . . . . . . . . . . 3-16, 6-89 COCAH0 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAH1 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAH2 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAH3 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAL0 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAL1 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAL2 . . . . . . . . . . . . . . . . . . 3-16, 6-29 COCAL3 . . . . . . . . . . . . . . . . . . 3-16, 6-29 CPU Accumulator . . . . . . . . . . . . . . . . . . . . 2-3 B register . . . . . . . . . . . . . . . . . . . . . . 2-4 Basic timing . . . . . . . . . . . . . . . . . . . . 2-5 Fetch/execute diagram. . . . . . . . . . . . 2-6 Functionality . . . . . . . . . . . . . . . . . . . . 2-3 Program status word . . . . . . . . . . . . . 2-3 Stack pointer . . . . . . . . . . . . . . . . . . . 2-4 CPU timing. . . . . . . . . . . . . . . . . . . . . . . 2-6 CPUUPD . . . . . . . . . . . . . . . . . . 3-18, 6-77 CR . . . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-67 CRCH . . . . . . . . . . . . . . . . . . . . 3-13, 6-27 CRCL . . . . . . . . . . . . . . . . . . . . . 3-13, 6-27 Semiconductor Group 11-1 1997-08-01 Index C505 / C505C CY . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 D Datapointers . . . . . . . . . . . . . . . . . 4-6 to 4-9 Application examples . . . . . . . . 4-7 to 4-9 DPSEL register . . . . . . . . . . . . . . . . . . 4-6 Functionality . . . . . . . . . . . . . . . . . . . . 4-6 DB0 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB1 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB2 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB3 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB4 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB5 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB6 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DB7 . . . . . . . . . . . . . . . . . . 3-14, 3-19, 6-81 DC characteristics . . . . . . . . . . 10-2 to 10-4 Device Characteristics . . . . . . 10-1 to 10-19 AC characteristics 16 MHz timing . . . . . . . . . . 10-7 to 10-9 20 MHz timing . . . . . . . . 10-10 to 10-12 DIR . . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-80 DLC . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-80 DPH . . . . . . . . . . . . . . . . . . . 3-12, 3-15, 4-7 DPL . . . . . . . . . . . . . . . . . . . 3-12, 3-15, 4-7 DPSEL . . . . . . . . . . . . . . . . . 3-12, 3-15, 4-6 EX1 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 EX3 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EX4 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EX5 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EX6 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 Execution of instructions . . . . . . . . 2-5, 2-6 EXEN2 . . . . . . . . . . . . . . . . . 3-16, 6-28, 7-6 EXF2 . . . . . . . . . . . . . . . . . . 3-16, 6-28, 7-9 External bus interface . . . . . . . . . . . . . . 4-1 ALE signal . . . . . . . . . . . . . . . . . . . . . 4-4 ALE switch-off control . . . . . . . . . . . . 4-4 Overlapping of data/program memory 4-3 Program memory access . . . . . . . . . . 4-3 Program/data memory timing. . . . . . . 4-2 PSEN signal . . . . . . . . . . . . . . . . . . . . 4-3 Role of P0 and P2 . . . . . . . . . . . . . . . 4-1 F F0. . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 F1. . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 Fail save mechanisms . . . . . . . . . 8-1 to 8-8 Fast power-on reset. . . . . . . . . . . . 5-3, 8-8 Features. . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional units . . . . . . . . . . . . . . . . . . . 1-1 Fundamental structure. . . . . . . . . . . . . . 2-1 E EA. . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 EADC . . . . . . . . . . . . . . . . . 3-16, 6-103, 7-6 EALE . . . . . . . . . . . . . . . . . . . 1-8, 3-16, 4-4 EAN0 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN1 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN2 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN3 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN4 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN5 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN6 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN7 . . . . . . . . . . . . . . . . . . . . 3-15, 6-109 EAN7-0. . . . . . . . . . . . . . . . . . . . . . . . 6-109 ECAN . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EIE . . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 Emulation concept . . . . . . . . . . . . . . . . . 4-5 ES. . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 ET0. . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 ET1. . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 ET2. . . . . . . . . . . . . . . . . . . . 3-15, 6-28, 7-5 EWPD. . . . . . . . . . . . . . . . . . . . . . 3-15, 9-2 EWRN . . . . . . . . . . . . . . . . . . . . 3-18, 6-68 EX0. . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-5 Semiconductor Group G GATE . . . . . . . . . . . . . . . . . . . . . 3-15, 6-18 GF0 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 GF1 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 GMS0. . . . . . . . . . . . . . . . . 3-14, 3-18, 6-72 GMS1. . . . . . . . . . . . . . . . . 3-14, 3-18, 6-72 H Hardware reset . . . . . . . . . . . . . . . . . . . 5-1 I I/O ports . . . . . . . . . . . . . . . . . . . 6-1 to 6-14 I3FR . . . . . . . . . . . . . . . . . . . 3-16, 6-26, 7-8 IADC . . . . . . . . . . . . . . . . . 3-16, 6-103, 7-9 ID12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 ID17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 ID20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 ID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 ID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 IDLE. . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 Idle mode . . . . . . . . . . . . . . . . . . . 9-3 to 9-4 IDLS. . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 IE . . . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 IE0 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 11-2 1997-08-01 Index C505 / C505C IE1 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 IEN0 . . . . . . 3-12, 3-13, 3-15, 6-28, 7-5, 8-3 IEN1 3-12, 3-13, 3-16, 6-28, 6-103, 7-6, 8-3 IEX3 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 IEX4 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 IEX5 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 IEX6 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 INIT. . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 INT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 INT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Interrupt system . . . . . . . . . . . . . 7-1 to 7-17 Interrupts Block diagram . . . . . . . . . . . . . . 7-2 to 7-4 Enable registers . . . . . . . . . . . . 7-5 to 7-6 External interrupts. . . . . . . . . . . . . . . 7-16 Handling procedure . . . . . . . . . . . . . 7-14 Priority registers . . . . . . . . . . . . . . . . 7-12 Priority within level structure . . . . . . . 7-13 Request flags . . . . . . . . . . . . . 7-7 to 7-11 Response time . . . . . . . . . . . . . . . . . 7-17 Sources and vector addresses . . . . . 7-15 INTID . . . . . . . . . . . . . . . . . . . . . 3-18, 6-70 INTPND . . . . . . . . . . . . . . . . . . . 3-18, 6-76 IP0 . . . . . . . 3-12, 3-13, 3-15, 7-12, 8-3, 8-6 IP1 . . . . . . . . . . . . . . . . . . . 3-12, 3-16, 7-12 IR . . . . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-70 IRCON . . . . . . 3-12, 3-16, 6-28, 6-103, 7-9 IT0 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 IT1 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 MCR1. . . . . . . . . . . . . . . . . 3-14, 3-18, 6-76 Memory organization . . . . . . . . . . . . . . . 3-1 Data memory . . . . . . . . . . . . . . . . . . . 3-2 General purpose registers . . . . . . . . . 3-2 Memory map . . . . . . . . . . . . . . . . . . . 3-1 Program memory . . . . . . . . . . . . . . . . 3-2 MSGLST . . . . . . . . . . . . . . . . . . 3-18, 6-77 MSGVAL . . . . . . . . . . . . . . . . . . 3-18, 6-76 MX0 . . . . . . . . . . . . . . . . . 3-16, 3-17, 6-101 MX1 . . . . . . . . . . . . . . . . . 3-16, 3-17, 6-101 MX2 . . . . . . . . . . . . . . . . . 3-16, 3-17, 6-101 N NEWDAT . . . . . . . . . . . . . . . . . . 3-18, 6-77 O Oscillator operation . . . . . . . . . . . 5-6 to 5-7 External clock source . . . . . . . . . . . . . 5-7 On-chip oscillator circuitry . . . . . . . . . 5-7 Recommended oscillator circuit . . . . . 5-6 Oscillator watchdog . . . . . . . . . . . 8-6 to 8-8 Behaviour at reset . . . . . . . . . . . . . . . 5-3 Block diagram . . . . . . . . . . . . . . . . . . 8-7 OV . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 OWDS . . . . . . . . . . . . . . . . . . . . . 3-15, 8-6 P P . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 P0 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P1 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P1ANA . . . . . . . . . . . 3-12, 3-15, 6-1, 6-109 P2 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P3 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-16 P4 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 Package information . . . . . . . . . . . . . 10-19 Parallel I/O . . . . . . . . . . . . . . . . . 6-1 to 6-14 PCON . . . . . . . . . . . . 3-13, 3-15, 6-46, 9-1 PCON1 . . . . . . . . . . . . . . . . 3-13, 3-15, 9-2 PDE . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 PDS . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 Pin Configuration . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and functions . . . . . . . . . 1-5 Ports . . . . . . . . . . . . . . . . . . . . . 6-1 to 6-14 Alternate functions . . . . . . . . . . . . . . . 6-2 Loading and interfacing . . . . . . . . . . 6-13 Output drivers circuitry . . . . . . . . . . . . 6-9 Mixed digital/analog I/O pins . . . . 6-11 Multifunctional digital I/O pins. . . . . 6-9 Output/input sample timing . . . . . . . 6-12 L LAR0 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-79 LAR1 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-79 LEC0 . . . . . . . . . . . . . . . . . . . . . 3-18, 6-69 LEC1 . . . . . . . . . . . . . . . . . . . . . 3-18, 6-69 LEC2 . . . . . . . . . . . . . . . . . . . . . 3-18, 6-69 LGML0 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-73 LGML1 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-73 LMLM0 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-74 LMLM1 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-74 Logic symbol . . . . . . . . . . . . . . . . . . . . . 1-3 M M0 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-18 M1 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-18 MCFG. . . . . . . . . . . . . . . . . 3-14, 3-18, 6-80 MCR0 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-76 Semiconductor Group 11-3 1997-08-01 Index C505 / C505C Read-modify-write operation. . . . . . . 6-14 Types and structures . . . . . . . . . . . . . 6-1 Port 0 circuitry . . . . . . . . . . . . . . . . . 6-5 Port 1/3/4 circuitry . . . . . . . . . . . . . . 6-6 Port 2 circuitry . . . . . . . . . . . . . . . . . 6-7 Standard I/O port circuitry . . . 6-3 to 6-4 Power down mode by software . . . . . . . . . . . . . . . . 9-6 to 9-8 Power saving modes . . . . . . . . . . 9-1 to 9-8 Control registers . . . . . . . . . . . . 9-1 to 9-2 Idle mode . . . . . . . . . . . . . . . . . 9-3 to 9-4 Slow down mode . . . . . . . . . . . . . . . . 9-5 Software power down mode . . . 9-6 to 9-8 Entry procedure. . . . . . . . . . . . . . . . 9-6 Exit (wake-up) procedure . . . . . . . . 9-7 State of pins . . . . . . . . . . . . . . . . . . . . 9-8 Protected ROM verify timing . . . . . . . . 4-11 PSEN signal . . . . . . . . . . . . . . . . . . . . . . 4-3 PSW . . . . . . . . . . . . . . . . . . . 2-4, 3-12, 3-16 R RB8 . . . . . . . . . . . . . . . . . . 3-15, 6-44, 6-45 RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Recommended oscillator circuits . . . . 10-18 REN . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-45 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Fast power-on reset . . . . . . . . . . . . . . 5-3 Hardware reset timing. . . . . . . . . . . . . 5-5 Power-on reset timing. . . . . . . . . . . . . 5-4 Reset circuitries . . . . . . . . . . . . . . . . . 5-2 RI . . . . . . . . . . . . . . . 3-15, 6-44, 6-45, 7-11 RMAP . . . . . . . . . . . . . . . . . . . . . 3-11, 3-16 RMTPND . . . . . . . . . . . . . . . . . . 3-18, 6-77 ROM protection . . . . . . . . . . . . . . . . . . 4-10 Protected ROM mode . . . . . . . . . . . . 4-11 Protected ROM verification example 4-12 Unprotected ROM mode. . . . . . . . . . 4-10 RS0 . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 RS1 . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 RxD . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-43 RXDC . . . . . . . . . . . . . . . . . . . . . 3-17, 6-97 RXIE . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-76 RXOK . . . . . . . . . . . . . . . . . . . . . 3-18, 6-68 Baudrate generation. . . . . . . . . . . . . 6-46 with internal baud rate generator . 6-48 with timer 1 . . . . . . . . . . . . . . . . . . 6-50 Multiprocessor communication. . . . . 6-44 Operating mode 0 . . . . . . . . 6-51 to 6-53 Operating mode 1 . . . . . . . . 6-54 to 6-56 Operating mode 2 and 3 . . . 6-57 to 6-59 Registers . . . . . . . . . . . . . . . . . . . . . 6-44 SIE . . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 SJW . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-71 SM0 . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-45 SM1 . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-45 SM2 . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-45 SMOD . . . . . . . . . . . . . . . . . . . . 3-15, 6-46 SP . . . . . . . . . . . . . . . . . . . . 2-4, 3-12, 3-15 Special Function Registers . . . . . . . . . 3-11 Access with RMAP. . . . . . . . . . . . . . 3-11 CAN registers - address ordered . 3-18 to 3-19 Table - address ordered. . . . 3-15 to 3-17 Table - functional order . . . . 3-12 to 3-14 SR . . . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-68 SRELH. . . . . . . . . . . . . . . . 3-13, 3-16, 6-49 SRELL . . . . . . . . . . . . . . . . 3-13, 3-15, 6-49 SWDT . . . . . . . . . . . . . . . . . . . . . 3-16, 8-3 SWI . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 SYSCON . . 3-3, 3-11, 3-12, 3-16, 4-4, 6-89 System clock output. . . . . . . . . . . 5-8 to 5-9 T T0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 T1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 T2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 T2CM . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 T2CON. . . . . . . . 3-12, 3-13, 3-16, 6-26, 7-8 T2EX . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 T2I0 . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 T2I1 . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 T2PS . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 T2R0 . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 T2R1 . . . . . . . . . . . . . . . . . . . . . 3-16, 6-26 TB8 . . . . . . . . . . . . . . . . . . 3-15, 6-44, 6-45 TCON. . . . . . . . . 3-12, 3-13, 3-15, 6-17, 7-7 TEST . . . . . . . . . . . . . . . . . . . . . 3-18, 6-67 TF0 . . . . . . . . . . . . . . . . . . . 3-15, 6-17, 7-7 TF1 . . . . . . . . . . . . . . . . . . . 3-15, 6-17, 7-7 TF2 . . . . . . . . . . . . . . . . . . . 3-16, 6-28, 7-9 TH0 . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16 S SBUF . . . . . . . . . . . . 3-13, 3-15, 6-44, 6-45 SCON . . . 3-12, 3-13, 3-15, 6-44, 6-45, 7-11 SD . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-1 Serial interface (USART) . . . . . 6-43 to 6-59 Semiconductor Group 11-4 1997-08-01 Index C505 / C505C TH1. . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16 TH2. . . . . . . . . . . . . . . . . . . 3-13, 3-16, 6-27 TI . . . . . . . . . . . . . . . 3-15, 6-44, 6-45, 7-11 Timer/counter . . . . . . . . . . . . . . . . . . . . 6-15 Timer/counter 0 and 1. . . . . . 6-15 to 6-22 Mode 0, 13-bit timer/counter . . . . . 6-19 Mode 1, 16-bit timer/counter . . . . . 6-20 Mode 2, 8-bit rel. timer/counter . . . 6-21 Mode 3, two 8-bit timer/counter. . . 6-22 Registers . . . . . . . . . . . . . . 6-16 to 6-18 Timer/counter 2. . . . . . . . . . . 6-23 to 6-42 Block diagram . . . . . . . . . . . . . . . . 6-24 Capture function . . . . . . . . 6-40 to 6-42 Compare function . . . . . . . 6-32 to 6-37 Compare mode 0 . . . . . . . 6-32 to 6-35 Compare mode 1 . . . . . . . 6-36 to 6-37 Compare mode interrupts . . . . . . . 6-38 General operation . . . . . . . . . . . . . 6-30 Port functions . . . . . . . . . . . . . . . . 6-23 Registers . . . . . . . . . . . . . . 6-25 to 6-29 Reload configuration . . . . . . . . . . . 6-31 Timings Data memory read cycle. . . . . . . . . 10-14 Data memory write cycle . . . . . . . . 10-15 External clock timing. . . . . . . . . . . . 10-15 Program memory read cycle. . . . . . 10-13 ROM verification mode 1 . . . . . . . . 10-16 ROM verification mode 2 . . . . . . . . 10-17 TL0 . . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16 TL1 . . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16 TL2 . . . . . . . . . . . . . . . . . . . 3-13, 3-16, 6-27 TMOD. . . . . . . . . . . . . . . . . 3-13, 3-15, 6-18 TR0. . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-17 TR1. . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-17 TSEG1 . . . . . . . . . . . . . . . . . . . . 3-18, 6-71 TSEG2 . . . . . . . . . . . . . . . . . . . . 3-18, 6-71 TxD. . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-43 TXDC . . . . . . . . . . . . . . . . . . . . . 3-17, 6-97 TXIE . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-76 TXOK . . . . . . . . . . . . . . . . . . . . . 3-18, 6-68 TXRQ . . . . . . . . . . . . . . . . . . . . . 3-18, 6-77 UMLM1 . . . . . . . . . . . . . . . 3-14, 3-18, 6-74 Unprotected ROM verify timing . . . . . . 4-10 V Version registers . . . . . . . . . . . . . . . . . 4-13 VR0 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13 VR1 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13 VR2 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13 W Watchdog timer . . . . . . . . . . . . . . 8-1 to 8-5 Block diagram . . . . . . . . . . . . . . . . . . 8-1 Control/status flags . . . . . . . . . . . . . . 8-3 Input clock selection. . . . . . . . . . . . . . 8-2 Refreshing of the WDT. . . . . . . . . . . . 8-5 Reset operation . . . . . . . . . . . . . . . . . 8-5 Starting of the WDT . . . . . . . . . . . . . . 8-4 Time-out periods . . . . . . . . . . . . . . . . 8-2 WDT. . . . . . . . . . . . . . . . . . . . . . . 3-15, 8-3 WDTPSEL . . . . . . . . . . . . . . . . . . 3-15, 8-2 WDTREL . . . . . . . . . . . . . . . 3-13, 3-15, 8-2 WDTS . . . . . . . . . . . . . . . . . . . . . 3-15, 8-3 WR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 WS . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-2 X XMAP0. . . . . . . . . . . . . . . . . . . . . 3-3, 3-16 XMAP1. . . . . . . . . . . . . . . . . . . . . 3-3, 3-16 XPAGE . . . . . . . . . . . . . . . . 3-5, 3-12, 3-15 XRAM operation . . . . . . . . . . . . . . . . . . 3-3 Access control . . . . . . . . . . . . . . . . . . 3-3 Accessing through DPTR. . . . . . . . . . 3-5 Accessing through R0/R1 . . . . . . . . . 3-5 Behaviour of P2/P0 . . . . . . . . . . . . . . 3-9 Reset operation . . . . . . . . . . . . . . . . . 3-9 Table - P0/P2 during MOVX instr. . . 3-10 XPAGE register . . . . . . . . . . . . . . . . . 3-5 Use of P2 as I/O port . . . . . . . . . . . 3-8 Write page address to P2 . . . . . . . . 3-6 Write page address to XPAGE . . . . 3-7 XTD . . . . . . . . . . . . . . . . . . 3-18, 6-61, 6-80 U UAR0 . . . . . . . . . . . . . . . . . UAR1 . . . . . . . . . . . . . . . . . UGML0 . . . . . . . . . . . . . . . . UGML1 . . . . . . . . . . . . . . . . UMLM0. . . . . . . . . . . . . . . . 3-14, 3-18, 6-79 3-14, 3-18, 6-79 3-14, 3-18, 6-73 3-14, 3-18, 6-73 3-14, 3-18, 6-74 Semiconductor Group 11-5 1997-08-01