C511

C511/C511A C513/C513A C513A-H 8-Bit CMOS Microcontroller tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ User’s Manual 06.96 ht User’s Manual C511/C511A/C513/C513A/C513A-H Revision History : Current Version : 06.96 Previous Releases : Page Several 10-14 10-15 02.96, 05.95 Subjects (changes since last revision) Corrections of text Figure 10-12 : external clock configuration corrected Updated package outline Edition 06.96 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C511 / C513 Table of Contents 1 2 2.1 2.2 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.4.1 6.1.4.2 6.1.4.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 XRAM Operation (C513A/A-H only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . . . 3-3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) . . . . . . . . . . . 3-3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN - Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 ALE - Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 XRAM Access Enable (SAB-C513A/A-H only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . . . . . 4-4 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Read-Modify-Write Feature of Ports 1, 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Timer/Counter 2 (SAB-C513/C513A/C513A-H only) . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Semiconductor Group I-1 C511 / C513 Table of Contents 6.2.2.1 6.2.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.4 6.3.5 6.3.6 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.7.1 6.4.7.2 6.4.8 6.4.8.1 6.4.8.2 6.4.8.3 6.4.8.4 6.4.8.5 6.4.8.6 7 7.1 7.2 7.2.1 7.2.2 7.3 7.4 7.5 8 8.1 8.2 9 9.1 9.2 9.2.1 9.2.2 Page Auto-Reload Mode (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 General Purpose Serial Interface USART (SAB-C513/C513AC513A-H only) . . . . . . 6-27 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Synchronous Serial Channel (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 SSC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 Write Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 SSC Control Register SSCCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 SSC Interrupt Enable Register SCIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Status Register SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Data Registers STB and SRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Mode Test Register SSCMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Location of Bitaddressable Control and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Interrupt Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 EEPROM Programming Interface of the SAB-C513A-H . . . . . . . . . . . . . . . . . . . . . .9-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Selection of the Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Resetting the Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Semiconductor Group I-2 C511 / C513 Table of Contents 9.2.3 9.2.4 9.2.4.1 9.2.4.2 9.2.4.3 9.2.4.4 9.2.5 9.2.5.1 9.2.5.2 9.2.5.3 10 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.4 10.4.1 10.5 Page Interface Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Programming Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Programming Control Register PCNTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Memory Select Register PMSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Data Register PDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Address Low Register PADRL and PADRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 EEPROM Access Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 AC Characteristics (applies to all C511/513 Family Microcontrollers) . . . . . . . . . . . . 10-16 Program Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 SSC Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 External Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 ROM Verification Characteristics (only C511/C511A/C513/C513A) . . . . . . . . . . . . 10-22 AC Characteristics of C513A-H Programming Interface . . . . . . . . . . . . . . . . . . . . . . 10-23 Reset Characteristics (C513A-H only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 Semiconductor Group I-3 Introduction 1 Introduction The C511-R, C511A-R, C513-R, C513A-R, C513A-2R, and C513A-H are members of a family of low cost microcontrollers, which are software compatible with the components of the SAB 8051, SAB 80C51 and C500 families. The five versions with the “-R” extension contain a non-volatile read-only program memory (ROM). The C513A-H is a version with a 12 Kbyte EEPROM instead of ROM. This device can be used for prototype designs which have a demand for reprogrammable on-chip code memory. The microcontroller versions differ in functionality according table 1-1. They offer different ROM sizes, different RAM/XRAM sizes and a different timer/USART configuration. Common to all devices is an advanced SSC serial port, a second synchronous serial interface, which is compatible to the SPI serial bus industry standard. Except the EEPROM size, the functionality of the C513A-H is a superset of all ROM versions of the C511/513 family. In this user manual the microcontroller family is also referenced with the term C511/513 and the ROM versions are referenced without the “-R” extension. If some of the features described are applicable to selected family members only, this will be explicitly stated. Table 1-1 Functionality of the C511/513 MCUs Device C511 C511A C513 C513A C513A-H ROM Size 2.5 KB 4 KB 8 KB 12/16 KB – EEPROM Size – – – – 12 KB RAM Size 128 B 256 B 256 B 256 B 256 B XRAM Size – – – 256 B 256 B Timers 1) T0, T1 T0, T1 T0, T1, T2 T0, T1, T2 T0, T1, T2 USART 2) SSC 3) – –         Note: 1) T0 and T1 are the standard 16-bit timer. T2 is the 16-bit timer with autoreload. 2) USART is the Universal Synchronous/Asynchronous Receive/Transmit interface. 3) SSC is the Synchronous Serial Channel (SPI compatible interface). According table 1-1, figure 1-1 to figure 1-4 show the functional units of the members of the C511/ 513 family microcontrollers. Semiconductor Group 1-1 Introduction Figure 1-1 C511 Functional Units Figure 1-2 C511A Functional Units Semiconductor Group 1-2 Introduction Figure 1-3 C513 Functional Units Figure 1-4 C513A / C513A-H Functional Units Semiconductor Group 1-3 Introduction Listed below is a summary of the main features of the C511/513 family members: – Fully software compatible to standard 8051/8052 microcontrollers – Up to 12 MHz operating frequency – Up to 12 K × 8 ROM / EEPROM – Up to 256 × 8 RAM – Up to 256x8 XRAM – Four 8-bit ports – Up to three 16-bit Timers / Counters (Timer 2 with Up/Down and 16-bit autoreload feature) – Synchronous Serial Channel (SSC) – Optional USART – Up to seven interrupt sources, two priority levels – Power Saving Modes – P-LCC-44 package (C513A also in P-MQFP-44 package) – Temperature ranges: SAB-C511 / 511A / 513 / 513A / C513A-H TA : 0 °C to 70 °C SAF-C513A TA : -40 °C to 85 °C Figure 1-5 C511/C513 Logic Symbol If the C513A-H is used in programming mode, its logic symbol is different from figure 1-5 (see figure 9-1). Semiconductor Group 1-4 Introduction Pin Configuration (top view) Figure 1-6 P-LCC-44 Package Pin Configuration (Top View) Semiconductor Group 1-5 Introduction Figure 1-7 P-MQFP-44 Package Pin Configuration of the C513A (Top View) If the C513A-H is used in programming mode, the pin configuration is different to figure 1-6 or figure 1-7. (see figure 9-2) If the C513A-H is used in programming mode, the pin definitions and functions are different to table 1-2 (see table 9-1). Semiconductor Group 1-6 Introduction Table 1-2 Pin Definitions and Functions Symbol Pin Number P-LCC- P-MQFP44 44 P1.7-P1.0 9-2 3-1, 44-40 I/O Port 1 is a bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains the timer 2 and SSC pins as secondary function. In general the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. For the outputs of the SSC (SCLK, STO) special circuitry is implemented, providing true push-pull capability. The STO output in addition will have true tristate capability. When used for SSC inputs, the pull-up resistors will be switched off and the inputs will float (high ohmic inputs). The alternate functions are assigned to port 1, as follows: 2 3 4 5 6 7 40 41 42 43 44 1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 1) I/O*) Function T2 T2EX SCLK SRI STO SLS Input to counter 2 1) Capture -Reload trigger of timer 2 Up-Down count SSC Master Clock Output SSC Slave Clock Input SSC Receive Input SSC Transmit Output Slave Select Input 1) not available in the C511/511A *) I = Input O = Output Semiconductor Group 1-7 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC- P-MQFP44 44 P3.0-P3.7 11, 13-19 5, 7-13 I/O Port 3 is a bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3 as follows: 11 5 P3.0 13 7 P3.1 14 15 16 17 18 8 9 10 11 12 TXD RXD Receiver data input (asynchronous) or data input/output (synchronous) of serial interface (USART) 1) Transmitter data output (USART) 1) (asynchronous) or clock output (synchronous) of serial interface Interrupt 0 input / timer 0 gate control Interrupt 1 input / timer 1 gate control Counter 0 input Counter 1 input Write control signal : latches the data byte from port 0 into the external data memory Read control signal : enables the external data memory to port 0 I/O*) Function P3.2 P3.3 P3.4 P3.5 P3.6 INT0 INT1 T0 T1 WR 19 13 P3.7 RD 1) not available in the C511/511A XTAL2 20 14 – XTAL2 Output of the inverting oscillator amplifier. *) I = Input O = Output Semiconductor Group 1-8 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC- P-MQFP44 44 XTAL1 21 15 – XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal resistor to VSS permits power-on reset using only an external capacitor to VCC. I/O*) Function P2.0-P2.7 24-31 18-25 I/O PSEN 32 26 O RESET 10 4 I *) I = Input O = Output Semiconductor Group 1-9 Introduction Table 1-2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC- P-MQFP44 44 ALE 33 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. If no external memory is used, the ALE signal generation can be inhibited, reducing system RFI, by clearing register bit EALE in the SYSCON register. External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than the size of the internal ROM : C511 0A00H C511A 1000H C513 2000H C513A/A-H 3000H C513A-2R 4000H When held at low level, the microcontroller fetches all instructions from external program memory. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1s. External pullup resistors are required during program verification. Circuit ground potential Power Supply terminal for all operating modes No connection, do not connect externally I/O*) Function EA 35 29 I P0.0-P0.7 43-36 37-30 I/O VSS VCC N.C. 22 44 1, 12, 23, 34 16 38 6, 17, 28, 39 – – – *) I = Input O = Output Semiconductor Group 1-10 Fundamental Structure 2 Fundamental Structure The SAB-C511/513 family microcontrollers are based on the SAB-C501 architecture. Therefore they are also fully compatible to the standard 8051 microcontroller family. The completely new units compared to the SAB-C501 are the synchronous serial channel, the XRAM, and the EEPROM code memory. Figure 2-8 shows a block diagram of the SAB-C511/513 family microcontrollers. Figure 2-8 Block Diagram of the SAB-C511/513 Semiconductor Group 2-1 Fundamental Structure 2.1 CPU The SAB-C511/513 microcontrollers are efficient both as a controller and as an arithmetic processor. It have extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% onebyte, 41% two-byte, and 15% three-byte instructions. With an 8 MHz clock, 58% of the instructions are executed in 1.5 µs. The CPU (Central Processing Unit) of the SAB-C511/513 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers, and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, completement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-2 Fundamental Structure Special Function Register PSW (Address D0H) MSB 7 CY Reset Value : 00H LSB 0 P PSW Bit No. D0H 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 Bit CY AC F0 RS1 RS0 0 0 0 1 1 0 1 1 OV F1 P Function Carry Flag Auxiliary Carry Flag (for BCD operations) General Purpose Flag Register Bank select control bits Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH Overflow Flag General Purpose Flag Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07 H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-3 Fundamental Structure 2.2 CPU Timing A machine cycle consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logical operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2-9 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2-9 a) and b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most SAB-C511/513 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2-9 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. Semiconductor Group 2-4 Fundamental Structure Figure 2-9 Fetch Execute Sequence Semiconductor Group 2-5 Memory Organization 3 Memory Organization The C511/513 CPU manipulates operands in the following four address spaces: – – – – – – up to 64 Kbyte of external program memory up to 16 Kbyte of internal program memory up to 64 Kbyte of external data memory up to 256 bytes of internal data memory (includes bitaddressable area of 128 bits) 256 bytes additional internal data memory (XRAM) a 128 byte special function register area with 16 bitaddressable registers (128 bits) Figure 3-10 illustrates the memory address spaces of the C511/513. Figure 3-10 Memory Map Semiconductor Group 3-1 Memory Organization 3.1 Program Memory The C511/513 family members have up to 12 Kbytes of on-chip read-only program memory (depending on version). The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C511/513 executes out of internal ROM unless the address exceeds the upper limit of the on-chip program memory (upper limit table see figure 3-10). Instructions at addresses above this limit are then fetched from the external program memory. If the EA pin is held low, the C511/513 fetches all instructions from the external program memory. 3.2 Data Memory The data memory address space consists of an internal and an external memory space. The different versions of the C511/513 microcontroller family provide 128 (C511 only) or 256 byte (all other members) of internal data memory. The C513A/A-H contain another 256 byte of on-chip RAM additional to its 256 byte internal RAM. This RAM is referenced as XRAM (‘eXtended RAM’). 3.2.1 Internal Data Memory The internal data memory is divided into four physically separate and distinct blocks: – – – – the lower 128 byte of RAM including four register banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area a 256 byte XRAM area which is accessed like external RAM (MOVX-instructions), but is implemented on-chip (C513A/A-H only). 3.2.2 External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect addressing. A 16-bit external memory addressing mode is supported by the MOVX instructions using the 16-bit datapointer DPTR for addressing. For 8-bit addressing MOVX instructions in combination with registers R0 and R1 can be used. Note that there are restrictions with the C513A/A-H and 8-bit addressing mode when accessing external data memory (details see chapters 3.3.2 and 3.3.3). Semiconductor Group 3-2 Memory Organization 3.3 XRAM Operation (C513A/A-H only) The XRAM is a memory area that is logically located in the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register (see chapter 4.4). 3.3.1 Reset Operation of the XRAM The content of the XRAM is not affected by a reset. After power-up the content is undefined, while it remains unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle which the reset is detected at (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value. After reset the XRAM is disabled. 3.3.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) There are a read and a write instruction to access the XRAM which use the 16-bit DPTR for indirect addressing. The instructions are : – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) Use of these instructions normally implies, that port 0 is used as address low/data bus, port 2 for high address output and parts of port 3 for control to access upto 64 KB of external memory. If the XRAM is disabled, this will happen as with the other members of the C511/513 family. If it is enabled and if the effective address is in the range of 0000 H to FEFFH, these instruction also will access external memory. If XRAM is enabled and if the address is within FF00 H to FFFFH, the physically internal XRAM of the C513A/A-H will be accessed. Physically external memory in this address range cannot be accessed in this case, because no external bus cycles will generated. Therefore port 0, 2 and 3 can be used as general purpose I/O if only the XRAM memory space is addressed by the user program. 3.3.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The C511/513 architecture provides also instructions for accesses to external data memory which use only an 8-bit address (indirect addressing with registers R0 or R1). These instructions are : – MOVX – MOVX A, @Ri @Ri, A (Read) (Write) Use of these instructions implies, that port 0 is used as address/data bus, port 2 for high address output and parts of port 3 for control. Normally these instructions are used to access up to 256 byte of external memory. If the XRAM is disabled, this will happen as with the other members of the C511/513 components and the external memory is accessed. Semiconductor Group 3-3 Memory Organization If the XRAM is enabled these instruction will only access the internal XRAM. External memory cannot be accessed in this case because no external bus cycle will be generated. Therefore, port 0 and 3 can be used as standard I/O, if only the internal XRAM is used. 3.4 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word PSW, RS1 and RS0, select the active register bank (see description of the PSW in chapter 2.1). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. After reset register bank 0 is selected. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction opcode indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. 3.5 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area. The 34 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C511/513. Table 3-2 illustrates the contents of the SFRs, e.g. the bits of the SFRs. Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content after Reset 1) FFH 07H 00H 00H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 81H 82H 83H P0 SP DPL DPH .7 .7 .7 .7 .6 .6 .6 .6 .5 .5 .5 .5 .4 .4 .4 .4 .3 .3 .3 .3 .2 .2 .2 .2 .1 .1 .1 .1 .0 .0 .0 .0 Semiconductor Group 3-4 Memory Organization Table 3-1 SFRs - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP SYSCON IE IP P0 P1 P2 P3 SSCCON STB SRB SCF SCIEN SSCMOD PCON SBUF SCON TCON TMOD TL0 TL1 TH0 TH1 T2CON T2MOD RC2L RC2H TL2 TH2 2) 2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Stack Pointer System Control Reg. C511/C511A C513/C513A/C513A-H Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Power Control Register Serial Channel Buffer Register Serial Channel 1 Control Register Timer Control Register Timer Mode Register Timer 0, Low Byte Timer 1, Low Byte Timer 0, High Byte Timer 1, High Byte Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, Low Byte Timer 2 Reload/Capture Register, High Byte Timer 2 Low Byte Timer 2 High Byte Power Control Register Address E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H B1H A8H1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) E9H EAH F8H 1) F9H EBH 87H 99H 98H 1) 88H 1) 89H 8AH 8BH 8CH 8DH C8H 1) C9H CAH CBH CCH CDH 87H Contents after Reset 00H 00H 00H 00H 00H 07H 101X0XXXB 3) 101X0XX0B 3) 00H X0000000B 3) FFH FFH FFH FFH 07H XXH 3) XXH 3) XXXXXX00B 3) XXXXXX00B 3) 00H 0XXX0000B 3) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 3) 00H 00H 00H 00H 0XXX0000B 3) Interrupt System Ports SSC USART Timer 0 / Timer 1 Timer 2 Power PCON Save Mode 1) 2) 3) Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved Semiconductor Group 3-5 Memory Organization Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after Reset 1) 0XXX0000B 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 00H FFH 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 87H 88H 89H 8AH 8BH 8CH 8DH 90H 98H 99H A0H A8H B0H B1H B8H C8H C9H CAH CBH CCH CDH D0H E0H E8H E9H EAH EBH F0H F8H PCON TCON TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF P2 IE P3 SYSCON IP T2CON T2MOD RC2L RC2H TL2 TH2 PSW ACC SSCCON STB SRB SSCMOD B SCF SMOD TF1 GATE .7 .7 .7 .7 – SM0 .7 .7 EAL RD 1 – TF2 – .7 .7 .7 .7 CY .7 SCEN .7 .7 0 .7 – – TR1 C/T .6 .6 .6 .6 – SM1 .6 .6 ESSC WR 0 PSSC EXF2 – .6 .6 .6 .6 AC .6 TEN .6 .6 0 .6 – – TF0 M1 .5 .5 .5 .5 SLS SM2 .5 .5 ET2 T1 EALE PT2 RCLK – .5 .5 .5 .5 F0 .5 MSTR .5 .5 0 .5 – – TR0 M0 .4 .4 .4 .4 STO REN .4 .4 ES0 T0 – PS TCLK – .4 .4 .4 .4 RS1 .4 CPOL .4 .4 0 .4 – GF1 IE1 GATE .3 .3 .3 .3 SRI TB8 .3 .3 ET1 INT1 0 PT1 EXEN2 – .3 .3 .3 .3 RS0 .3 CPHA .3 .3 0 .3 – GF0 IT1 C/T .2 .2 .2 .2 SCLK RB8 .2 .2 EX1 INT0 – PX1 TR2 – .2 .2 .2 .2 OV .2 BRS2 .2 .2 0 .2 – PDE IE0 M1 .1 .1 .1 .1 T2EX TI .1 .1 ET0 TxD – PT0 C/T2 – .1 .1 .1 .1 F1 .1 BRS1 .1 .1 0 .1 WCOL IDLE IT0 M0 .0 .0 .0 .0 T2 RI .0 .0 EX0 RxD XMAP2) PX0 CP/ RL2 DCEN .0 .0 .0 .0 P .0 BRS0 .0 .0 0 .0 TC X0000000B 00H XXXXXXX0B 00H 00H 00H 00H 00H 00H 07H XXH XXH 00H 3) 00H XXXXXX00B Semiconductor Group 3-6 Memory Organization Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after Reset 1) XXXXXX00B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F9H 1) 2) SCIEN – – – – – – WCEN TCEN 3) X means that the value is indeterminate and the location is reserved. The availability of the XMAP bit and the reset value of SYSCON depends on the specific microcontroller : C511/511A : 101X0XXXB - bit XMAP is not available C513/513A/513A-H 101X0XX0B - bit XMAP is available This register ist only used for test purposes and must not be written. Otherwise unpredictable results may occur. Shaded registers are bit-addressable special function registers. Semiconductor Group 3-7 External Bus Interface 4 External Bus Interface The SAB-C511/513 microcontrollers allow external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the SAB-C511/513 is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated and no more generated externally. This feature reduces RFI emmisions of the system. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware. Accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR (alternate functions of P3.7 and P3.6) to strobe the memory. Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used (MOVX @DPTR), the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If the XRAM is enabled (only SAB-C513A/A-H) at 16-bit address accesses with an address value within the XRAM address space, no external bus cycle will be seen, but the internal XRAM will be accessed. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. If the XRAM is enabled at the SAB-C513A/A-H no external bus cycle will be seen regardless of the address. Semiconductor Group 4-1 External Bus Interface Figure 4-11 External Program Memory Execution Semiconductor Group 4-2 External Bus Interface 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustrated in figure 4-11 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: – whenever signal EA is active or – whenever EA is high and the program counter (PC) contains an address that is higher than the internal ROM size. This requires ROM-less versions of the SAB-C511/513 family components to have EA wired to ground to allow the program to be fetched from external memory only. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an address output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN - Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 12 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-11 a) and b). 4.3 ALE - Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-11 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. In systems that do not use external memory at all and do not use ALE as clock, external ALE generation can be suppressed by resetting the EALE bit in the SYSCON register. This can help to reduce system RFI. Because ALE Semiconductor Group 4-3 External Bus Interface can be enabled/disabled dynamically, it is also possible to enable ALE only when external memory is accessed. This can be useful, if the external memory is accessed very seldom only. 4.4 XRAM Access Enable (SAB-C513A/A-H only) The SAB-C513A/A-H maps 256 bytes of the external data space into the on-chip XRAM. Especially when using the 8-bit addressing modes this could prevent access to the external memory extension and might induce problems when porting software. Therefore it is possible to enable and disable the on-chip XRAM. When the XRAM is disabled (default after reset) all accesses will go to the external memory/IO. Special Function Registers SYSCON (Address B1H) MSB 7 1 LSB 0 XMAP SYSCON Bit No. B1H 6 0 5 EALE 4 – 3 0 2 – 1 – Bit – 7, 6, 3 XMAP Function Not implemented. Reserved for future use. Reserved bits; these bits must be always written with the values shown above. Enable XRAM (SAB-C513A/A-H only). XMAP=0 : XRAM disabled. XMAP=1 : XRAM enabled. Note: This bit is don’t care for the other members of the SAB-C511/513 family, but should be written with “0“ for compatibility reasons when writing to the SYSCON register. When reading the bit in non-SAB-C513A versions, it will be undefined. Enable ALE generation. If EALE=0, ALE signal will not be generated. If EALE=1, ALE signal will be generated. EALE Reset Value (C513/513A/A-H) : 101X0XX0B Reset Value (C511/C511A/C513) : 101X0XXXB 4.5 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the SAB-C511/C513 the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-4 System Reset 5 5.1 System Reset Hardware Reset The hardware reset function built in the SAB-C511/513 microcontrollers allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated (see power-down description chapter 8). The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During RESET active, the pins ALE and PSEN are configured as inputs and should not be active driven externally. An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins. At the RESET pin a pulldown resistor is internally connected to VSS to allow a power-up reset operation with an external capacitor only. An automatic reset can be obtained when power supply is applied by connecting the reset pin via an external capacitor to VCC. After the power supply has been turned on, the capacitor must hold the voltage level at the reset pin for a specified time to effect a complete reset. A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0, 1, 2 and 3 default in FF H. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1, 2 and 3) output a one (1). The contents of the internal RAM (conventional and XRAM) of the SAB-C511/513 is not affected by a reset. After power-up the contents is undefined, while it remains unchanged during a reset if the power supply is not turned off. Note: For the SAB-C513A-H (EEPROM version) the RESET signal has to be activated for at least 10 ms if power is applied to the device. The reason for this is that the reference voltage generator of the EEPROM device needs some time to come up from power-down state. In the power-on behaviour there are no differences between the EEPROM and ROM versions. This reset behaviour of the EEPROM version has to be taken into account for systems that also will uses ROM versions of the SAB-C511/513 family and that use its software power down features. Semiconductor Group 5-1 System Reset 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1’s etc. The RESET signal must be active for at least two machine cycles; after this time the SAB-C511/513 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-12 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. in PCL OUT PCH OUT P2 ALE MCT02092 Figure 5-12 CPU Timing after Reset Semiconductor Group 5-2 On-Chip Peripheral Units 6 6.1 On-Chip Peripheral Components Parallel I/O The SAB-C511/513 has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Port 1 pins used for SSC outputs are true push-pull outputs. When used as SSC inputs they float (no pull-up). 6.1.1 Port Structures Each port bit consists of a latch, an output driver(s) and an input buffer. Read and write accesses to the I/O ports P0, P1, P2 and P3 are performed via the corresponding special function registers. Figure 6-13 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the four I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. Both the output of the latch as well as the actual state of the port pins can be read, depending on the instruction used for accessing the port. Figure 6-13 Basic Structure of a Port Circuitry Semiconductor Group 6-1 On-Chip Peripheral Units Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-6-14). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional". Figure 6-14 Basic Output Driver Circuit of Ports 1, 2 and 3 Semiconductor Group 6-2 On-Chip Peripheral Units In fact, the pullups mentioned before and included in figure 6-2 are pullup arrangements shown in figure 6-6-15a. One n-channel pulldown FET and three pullup FETs are used: Figure 6-15a Output Driver Circuit of Ports 1, 2 and 3 (except P1.2, P1.3, P1.4 and P1.5) – The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable of sinking high currents (IOL); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no ”0“ must be programmed into the latch of a pin that is used as input. – The pullup FET p1 is of p-channel type. It is activated for two oscillator periods (S1P1 and S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin. – The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch, thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level. – The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL . If, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output. Semiconductor Group 6-3 On-Chip Peripheral Units The described activating and deactivating of the four different transistors results in four states which can be : – – – – input low state (IL), p2 active only input high state (IH) = steady output high state (SOH), p2 and p3 active forced output high state (FOH), p1, p2 and p3 active output low state (OL), n1 active If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (=SOH) state. If it is is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds the drive capability of p2 (IIL), the pin might remain in the IL state and provide a week "1" until the first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities. If the load exceeds IIL the pin can be forced to “1“ by writing a “0“ followed by a “1“ to the port pin.. The driver and control structure of the port pins used for the alternate functions of the SSC have been modified to provide the following features: – P1.2 when used as SSC clock output will become a true push-pull output – P1.3 when used as SSC receiver input will become an input without pullups. – P1.4 when used as SSC transmitter output will become a true push-pull output with tristate capability – P1.5 when used as SSC slave select input will directly control the tristate condition of P1.4. The modified port structure is illustrated in figures 6-b and 6-c. Semiconductor Group 6-4 On-Chip Peripheral Units Figure 6-15b Driver Circuit of Port 1 pins P1.2 and P1.4 (when used for SLCK and STO) Pin Control for SCLK When the SSC is disabled, both Enable Push-pull and Tristate will be inactive, the pin behaves like a standard IO pin. In master mode and with SSC enabled, Enable Push-pull will be active and Tristate will be inactive. In slave mode and with SSC enabled, Enable Push-pull will be inactive and Tristate will be active. Pin Control for STO When the SSC is disabled, both Enable Push-pull and Tristate will be inactive. In master mode and SSC enabled, Enable Push-pull will be active and Tristate will be inactive. In slave mode and SSC enabled, Enable Push-pull will be active. If the transmitter is enabled (SLS and TEN active), Tristate will be inactive. If the transmitter is disabled (either SLS or TEN inactive), Tristate will be active. Semiconductor Group 6-5 On-Chip Peripheral Units Figure 6-15c Driver Circuit of Port 1 pins P1.3 and P1.5 (when used for SRI and SLS) When enabling the SSC, inputs used for the SSC will be switched into a high-impedance mode. For P1.3/SRI, Tristate will be enabled, when the SSC is enabled. For P1.5/SLS, Tristate will be enabled, when the SSC is enabled and is switched to slave mode. In master mode this pin will remain a regular I/O pin. Semiconductor Group 6-6 On-Chip Peripheral Units Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-16a) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Figure 6-16a Port 0 Circuitry Semiconductor Group 6-7 On-Chip Peripheral Units 6.1.2 Port 0 and Port 2 used as Address/Data Bus As shown in figure 6-16a and below in figure 6-16b, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1’s written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-16a. When a 16-bit address is used, port 2 uses the additional strong pullups p1 to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Read Latch Addr. Control V CC Internal Pull Up Arrangement Int. Bus Write to Latch D Bit Latch CLK Q MUX Q =1 Port Pin Read Pin MCS02123 Figure 6-16b Port 2 Circuitry Semiconductor Group 6-8 On-Chip Peripheral Units 6.1.3 Alternate Functions The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement alternate functions (special inputs/outputs for on-chip peripherals) as listed in table 6-6-3. Figure 6-17a shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Read Latch Alternate Output Function VCC Internal Pull Up Arrangement Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS01827 Read Pin Alternate Input Function Figure 6-17a Ports 1 and 3 For port pins P1.2 to P1.5 different structures apply, see figures 6-17b and 6-17c. Semiconductor Group 6-9 On-Chip Peripheral Units Figure 6-17b Port pins P1.2, P1.3 and P1.5 (when used as inputs to SSC) Figure 6-17c Port pins P1.2 and P1.4 (when used as outputs by SSC) Semiconductor Group 6-10 On-Chip Peripheral Units Ports 1 and 3 provide several alternate functions as listed in table 6-3: Table 6-3 Alternate Functions of Port 1 and 3 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Symbol T2 T2EX SCLK SRI STO SLS RXD TXD INT0 INT1 T0 T1 WR RD Function Input to counter 2 (SAB-C513/513A/C513A-H only) Capture-reload trigger of timer 2 / up-down count (SAB-C513/513A/C513A-H only) SSC master clock output, slave clock input SSC serial data in SSC serial data out SSC slave select Serial port’s receiver data input (asynchronous) or data input/output (synchronous, not available at SAB-C511/C511A) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous, not available at SAB-C511/C511A) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data memory read strobe Semiconductor Group 6-11 On-Chip Peripheral Units 6.1.4 Port Handling 6.1.4.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-18 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain requirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. Figure 6-18 Port Timing Semiconductor Group 6-12 On-Chip Peripheral Units 6.1.4.2 Port Loading and Interfacing The output buffers of ports 1, 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be be seen in the Data Sheet of the SAB-C511/513 family members. The corresponding DC parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1, 2 and 3 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 has floating inputs when used for digital input. 6.1.4.3 Read-Modify-Write Feature of Ports 1, 2 and 3 Some port-reading instructions read the latch and others read the pin (see figure 6-13). The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-4. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P0, P1, P2 and P3; for example, "MOV A, P1" reads the value from port 3 pins, while "ANL P1, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in table 6-4 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. Table 6-4 "Read-Modify-Write"-Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y,C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P1 Decrement byte; e.g. DEC P1 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x Semiconductor Group 6-13 On-Chip Peripheral Units The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rater than the pin will return the correct value of "1". Semiconductor Group 6-14 On-Chip Peripheral Units 6.2 Timers/Counters The SAB-C511/513 microcontrollers contains two (SAB-C511/C511A) or three (SAB-C513/C513A/ C513A-H) 16-bit timers/counters which are useful in many applications for timing and counting functions. In timer function, the register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency. In counter function, the register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the counter is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Semiconductor Group 6-15 On-Chip Peripheral Units 6.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the SAB-C511/513 family components are fully compatible with timer / counter 0 and 1 of the 8051 microcontroller and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is split into one 8-bit timer/counter and one 8-bit timer when programmed to this mode. Timer/counter 1 set to this mode will simply hold its count. The effect is the same as setting TR1 = 0, disabling the counter. The external inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1. Special Function Register TCON (Address 88H) MSB 7 TF1 Reset Value : 00H LSB 0 IT0 TCON Bit No. 88H 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 These bits are not used in controlling timer/counter 0 and 1. Bit TR0 TF0 TR1 TF1 Function Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Semiconductor Group 6-16 On-Chip Peripheral Units Special Function Register TMOD (Address 89H) MSB 7 Gate Reset Value : 00H LSB 0 M0 TMOD Bit No. 89H 6 C/T 5 M1 4 M0 3 Gate 2 C/T 1 M1 Timer 1 Control Timer 0 Control Bit Gate Function Gating control. When set, timer/counter "x" is enabled only while "INTx" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. Counter or timer select bit. Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). M0 0 Timer modes select bits 8-bit timer/counter. "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler. 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler. 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows. Timer 0: TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1: Timer/counter 1 stops C/T M1 0 0 1 1 1 0 1 1 1 Semiconductor Group 6-17 On-Chip Peripheral Units 6.2.1.1 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-19 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-19. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3). OSC ÷ 12 C/T = 0 TL0 (5 Bits) TH0 (8 Bits) Interrupt TF0 C/T = 1 P3.4/T0 Control TR0 _