C515

C515 8-Bit CMOS Microcontroller User’s Manual 04.98 ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ Edition 04.98 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1998 All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C515 User’s Manual Revision History : Previous Releases: Page (new version) 1-2 1-3 1-4, 1-5 1-5 1-6 to 1-10 04.98 08.97 Page (prev. Subjects (changes since last revision) version) 1-2 1-3 1-4 1-4 1-5 to 1-10 P-LCC-68 package is inlcuded in the features list PE pin is corrected as PE/SWD Pin configuration of P-LCC-68 package is included. PE pin is corrected as PE/SWD The Pin Definitions and Functions are added for P-LCC-68 package. The pin description is modified in ascending order starting from first pin of P-LCC-68 package 1-6 1-9 The pin name and description is corrected for PE/SWD 2-1 2-1 PE pin is corrected as PE/SWD in Figure 2.1 3-4 3-4 SYSCON register description is updated 3-6 3-6 PCON and SYSCON register descriptions are updated 4-4 4-4 A note is added describing the non availability of ALE switch off feature in C515-LN/1RN versions 6-65 6-65 The voltage specifications of VAREF and VAGND are changed 8-1 8-1 The description on starting of watchdog timer is modified to include the automatic start by strapping the pin PE/SWD to VCC. The content is modified with detailed subheadings. 8-2 8-2 In Figure 8-1 PE/SWD is added to include the option for the automatic start of watchdog timer 9-1 9-1 A detailed description is added for “Hardware Enable for the Use of Power Saving Modes” and “Application Example for Switching Pin PE/SWD” The description of Slow down mode bit (SD) is modified to indicate the 9-2 9-1 availability of this feature for C515-LM/1RM versions only 10-2, 10-5, 10-2, 10-5, The device specifications are valid for ROMless versions also. So 10-6 & 10-8 10-6 & 10-8 C515-1RM is modified to C515 in all these pages. CLKOUT timing table for 16 MHz is included 10-6 10-6 10-8 10-13 10-14 10-8 10-12 10-13 CLKOUT timing table for 24 MHz is included Timing diagram for CLKOUT timing is included The title “ROM Verification Characteristics for the C515-1RM” is modified to “ROM Verification Characteristics for the C515-1R” The package information is added for P-LCC-68 (SMD) 10-17 10-16 General Information C515 Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 5 5.1 5.2 5.3 5.4 6 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 Page Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . .4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 ROM Protection for the C515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 Unprotected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 Protected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 Port 1, Port 3 to Port 5 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 Read-Modify-Write Feature of Ports 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 5 Semiconductor Group General Information C515 Table of Contents 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.3.1 6.2.2.3.2 6.2.2.3.3 6.2.2.4 6.2.2.5 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.3.1 6.3.3.3.2 6.3.4 6.3.5 6.3.6 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.4.2.3 6.4.2.4 6.4.3 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1 8.1.2 8.1.2.1 Page Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 Timer/Counter 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . .6-22 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24 Timer 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . . . . . .6-31 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-31 Modulation Range in Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-33 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . .6-37 Capture Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-39 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-41 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-44 Baud Rate in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Using the Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59 A/D Converter Control Register ADCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59 A/D Converter Data Register ADDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-60 A/D Converter Interrupt Control Bits in IEN1 and IRCON . . . . . . . . . . . . . . . . . . .6-61 Programmable Reference Voltages of the A/D Converter (DAPR Register) . . . . .6-62 A/D Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 The First Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . .8-1 Semiconductor Group 6 General Information C515 Table of Contents 8.1.2.2 8.1.3 8.1.4 8.1.5 9 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 11 Page The Second Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . .8-1 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 WDT Control and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Hardware Enable for the Use of the Power Saving Modes . . . . . . . . . . . . . . . . . . .9-1 Power Saving Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Slow Down Mode Operation (C515-LM/1RM only) . . . . . . . . . . . . . . . . . . . . . . . . .9-5 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Invoking Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Exit from Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 State of Pins in the Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5 AC Characteristics (16 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 AC Characteristics (24 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8 ROM Verification Characteristics for the C515-1R . . . . . . . . . . . . . . . . . . . . . . .10-14 Package Information (P-LCC-68) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-17 Package Information (P-MQFP-80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-18 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 Semiconductor Group 7 Introduction C515 1 Introduction The C515 is a member of the Siemens C500 family of 8-bit microcontrollers. lt is functionally fully upward compatible with the SAB-80C515/80C535 microcontrollers. The C515 basically operates with internal and/or external program memory. The C515-L is identical to the C515-1R, except that it lacks the on-chip porgram memory. Therefore, in this documentation the term C515 refers to all versions within this specification unless otherwise noted. Figure 1-1 shows the different functional units of the C515 and figure 1-2 shows the simplified logic symbol of the C515. On-Chip Emulation Support Module Power Saving Modes Watchdog Timer RAM 256 x 8 Port 0 I/O T0 8-Bit A/D Converter T2 T1 CPU USART Port 1 I/O Port 2 I/O Port 6 Port 5 Port 4 ROM 8K x 8 Port 3 I/O Analog/ Digital Input I/O I/O MCA03198 Figure 1-1 C515 Functional Units Semiconductor Group 1-1 Introduction C515 Listed below is a summary of the main features of the C515: ¥ Full upward compatibility with SAB 80C515 ¥ Up to 24 MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation ¥ 8K byte on-chip ROM (with optional ROM protection) – alternatively up to 64K byte external program memory ¥ Up to 64K byte external data memory ¥ 256 byte on-chip RAM ¥ On-chip emulation support logic (Enhanced Hooks Technology TM) ¥ Six 8-bit parallel I/O ports ¥ One input port for analog/digital input ¥ Full duplex serial interface (USART) – 4 operating modes, fixed or variabie baud rates ¥ Three 16-bit timer/counters – Timer 0 / 1 (C501 compatible) – Timer 2 for 16-bit reload, compare, or capture functions ¥ 8-bit A/D converter – 8 multiplexed analog inputs – programmable reference voltages ¥ 16-bit watchdog timer ¥ Power saving modes – Idle mode – Slow down mode (can be combined with idle mode) – Software power-down mode ¥ 12 interrupt sources (7 external, 5 internal) selectable at four priority levels ¥ ALE switch-off capability (C515-LM/1RM only) ¥ P-LCC-68 and P-MQFP-80 packages ¥ Temperature Ranges: SAB-C515 TA = 0 to 70 °C SAF-C515 TA = -40 to 85 °C SAH-C515 TA = -40 to 110 °C (max. operating frequency: 16 MHz) Semiconductor Group 1-2 Introduction C515 VCC VSS XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD Port 0 8 Bit Digital I/O Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O C515 Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Input MCL03199 VAREF VAGND Figure 1-2 Logic Symbol Semiconductor Group 1-3 Introduction C515 1.1 Pin Configurations This section describes the pin configuration of the C515. RESET VAREF VAGND P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 10 P4.7 P4.6 P4.5 P4.4 P4.3 PE/SWD P4.2 P4.1 P4.0 V CC P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 9 1 68 61 60 P5.7 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 MCP00092 C515-LN/1RN 26 27 44 43 Figure 1-3 Pin Configuration of P-LCC-68 Package (top view) Semiconductor Group WR/P3.6 RD/P3.7 T2/P1.7 CLKOUT/P1.6 T2EX/P1.5 INT2/P1.4 CC3/INT6/P1.3 CC2/INT5/P1.2 CC1/INT4/P1.1 CC0/INT3/P1.0 VCC VSS XTAL2 XTAL1 P2.0 P2.1 P2.2 1-4 Introduction C515 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 N.C. VCC N.C. N.C. P4.0 P4.1 P4.2 PE/SWD P4.3 P4.4 P4.5 P4.6 P4.7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 N.C. VSS VCC N.C. P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2 P1.5/T2EX P1.6/CLKOUT P1.7/T2 N.C. P3.7/RD P3.6/WR RESET N.C. VAREF VAGND P6.7/AIN7 P6.6/AIN6 P6.5/AIN5 P6.4/AIN4 P6.3/AIN3 P6.2/AIN2 P6.1/AIN1 P6.0/AIN0 N.C. N.C. P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P5.7 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 N.C. N.C. EA ALE PSEN N.C. P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 C515 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCP03200 N.C. pins must not be connected Figure 1-4 Pin Configuration of P-MQFP-80-1 Package (top view) Semiconductor Group 1-5 Introduction C515 1.2 Pin Definitions and Functions This section describes all external signals of the C515 with its function. Table 1-1 Pin Definitions and Functions Symbol Pin Number P-LCC68 1-3, 5-9 Pin I/O*) Function Number P-MQFP80 72-74, 76-80 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Power saving mode enable/Start watchdog timer A low level at this pin allows the software to enter the power saving modes(idle mode, slow down mode and power down mode). It is impossible to enter the software controlled power saving modes if this pin is held at high level. A high level during the reset performs an automatic start of watchdog timer immidiately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515. A small internal pullup resistor permits poweron reset using only a capacitor connected to VSS . Reference voltage for the A/D converter Reference ground for the A/D converter Port 6 is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. P4.0-P4.7 PE/SWD 4 75 I RESET 10 1 I VAREF VAGND P6.0-P6.7 11 12 13-20 3 4 5-12 – – I *) I = Input O = Output Semiconductor Group 1-6 Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 21-28 Pin I/O*) Function Number P-MQFP80 15-22 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input WR control output; latches the data P3.6 / WR byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory P3.0-P3.7 21 22 23 24 25 26 27 15 16 17 18 19 20 21 28 22 *) I = Input O = Output Semiconductor Group 1-7 Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 36-29 Pin I/O*) Function Number P-MQFP80 31-24 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the loworder address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / INT3 / CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 / INT4 / CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 / INT5 / CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 / INT6 / CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 / INT2 Interrupt 2 input P1.5 / T2EX Timer 2 external reload / trigger input P1.6 / CLKOUT System clock output P1.7 / T2 Counter 2 input Ground (0 V) Supply voltage during normal, idle, and power-down operation. P1.0 - P1.7 36 31 35 30 34 29 33 28 32 31 30 29 VSS VCC *) I = Input O = Output 27 26 25 24 34 33, 69 – – 38 37, 68 Semiconductor Group 1-8 Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 39 Pin I/O*) Function Number P-MQFP80 36 – XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL1 Output of the inverting oscillator amplifier. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. XTAL2 XTAL1 P2.0-P2.7 40 41-48 37 38-45 – I/O PSEN 49 47 O *) I = Input O = Output Semiconductor Group 1-9 Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 50 Pin I/O*) Function Number P-MQFP80 48 O The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. External Access Enable When held high, the C515 executes instructions from the internal ROM (C515-1R) as long as the program counter is less than 2000H. When held low, the C515 fetches all instructions from ext. program memory. For the C515-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515-1R. External pullup resistors are required during program verification. Port 5 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Not connected These pins of the P-MQFP-80 package must not be connected. ALE EA 51 49 I P0.0-P0.7 52-59 52-59 I/O P5.ß-P5.7 67-60 67-60 I/O N.C. – 2, 13, 14, – 23, 32, 35, 46, 50, 51, 68, 70, 71 *) I = Input O = Output Semiconductor Group 1-10 Fundamental Structure C515 2 Fundamental Structure The C515 is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C515 incorporates a 8-bit A/D converter, a timer 2 with capture/compare functions, as well as some enhancements in the Fail Save Mechanism unit. Figure 2-1 shows a block diagram of the C515. C515 XTAL1 XTAL2 ALE PSEN EA PE/SWD RESET Timer 0 Port 0 Port 0 8 Bit Digital I/O Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O Port 5 8 Bit Digital I/O Port 6 8 Bit Digital I/O Digital Input Programmable Watchdog Timer CPU Emulation Support Logic RAM 256 x 8 OSC & Timing ROM 8K x 8 Timer 1 Port 1 Timer 2 Port 2 USART Baud Rate Generator Port 3 Interrupt Unit VAREF VAGND Port 4 Programmable Reference Voltages 8-Bit A/D Converter S&H Port 5 Analog MUX Port 6 MCB03201 Figure 2-1 Block Diagram of the C515 Semiconductor Group 2-1 Fundamental Structure C515 2.1 CPU The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz external clock, 58% of the instructions execute in 1.0 ms (24 MHz 500 ns). The CPU (Central Processing Unit) of the C515 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-2 Fundamental Structure C515 Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-3 Fundamental Structure C515 2.2 CPU Timing A machine cycle of the C515 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C515 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. Semiconductor Group 2-4 Fundamental Structure C515 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL1) ALE Read Opcode S1 a) 1-Byte, S2 S3 S4 Read next Opcode (Discard) S5 S6 Read next Opcode again 1-Cycle Instruction, e.g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 # Data Read next Opcode again Read Opcode S1 S2 S3 S4 Read next Opcode (Discard) S5 S6 S1 S2 S3 S4 S5 S6 Read next Opcode b) 2-Byte, 1-Cycle Instruction, e.g. ADD A, c) 1-Byte, 2-Cycle Instruction, e.g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read next Opcode (Discard) S5 ADDR S6 S1 Read next Opcode again No Fetch No ALE S2 DATA MCD03218 No Fetch S3 S4 S5 S6 d) MOVX (1-Byte, 2-Cycle) Access External Memory Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-5 Memory Organization C515 3 Memory Organization The C515 CPU manipulates operands in the following four address spaces: – – – – up to 64 Kbyte of program memory (8K on-chip program memory for C515-1R) up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C515. FFFF H FFFF H External External Indirect Address FF H Internal RAM 2000 H 1FFF H Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "Data Space" Internal RAM 80 H Direct Address Special Function Register 7F H 00 H FF H 80 H "Internal Data Space" MCD03202 Figure 3-1 C515 Memory Map Semiconductor Group 3-1 Memory Organization C515 3.1 Program Memory, "Code Space" The C515-1R has 8 Kbytes of read-only program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C515-1R executes program code out of the internal ROM unless the program counter address exceeds 1FFFH. Address locations 2000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C515 fetches all instructions from the external 64K byte program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 Memory Organization C515 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 43 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C515 are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C515. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group 3-3 Memory Organization C515 Table 3-1 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP SYSCON SYSCON4) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register System Control Register A/D Converter Control Register A/D Converter Data Register A/D Converter Program Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Timer Control Register Timer 2 Control Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H B1H D8H 1) D9H DAH A8H1) B8H 1) A9H B9H C0H 1) 88H 1) C8H 1) 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH 00H 00H 00H 00H 00H 07H XX1X XXXXB3) XXXX XXXXB3) 00X0 0000B 3) 00H 00H 00H 00H 00H X000 0000B 3) XX00 0000B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H A/DADCON 2) Converter ADDAT DAPR Interrupt System IEN0 2) IEN1 2) P0 2) IP1 IRCON TCON 2) T2CON 2) SCON 2) TCON 2) TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) For C515-LN/1RN only Semiconductor Group 3-4 Memory Organization C515 Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Symbol TL2 T2CON 2) P0 P1 P2 P3 P4 P5 P6 ADCON 2) PCON 2) SBUF SCON 2) Name Timer 2, Low Byte Timer 2 Control Register Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Analog/Digital Input A/D Converter Control Register Power Control Register Serial Channel Buffer Register Serial Channel Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Address Contents after Reset CCH C8H 1) 80H 1) 90H 1) A0H 1) B0H 1 E8H 1) F8H 1) DBH D8H 1 87H 99H 98H 1) A8H1) B8H 1) A9H 87H 00H 00H FFH FFH FFH FFH FFH FFH – 00X0 0000B 3) 00H XXH 3) 00H 00H 00H X000 0000B 3) 00H Ports Serial Channel Watchdog IEN0 2) IEN1 2) IP0 2) Power Saving Modes PCON 2) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group 3-5 Memory Organization C515 Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H SP 82H 83H 87H 87H DPL DPH PCON PCON 3) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 00H X0000000B FFH .7 .7 .7 .7 .6 .6 .6 .6 .5 .5 .5 .5 IDLS IDLS TF0 M1 .5 .5 .5 .5 T2EX SM2 .5 .5 ET2 .4 .4 .4 .4 SD _ TR0 M0 .4 .4 .4 .4 INT2 REN .4 .4 ES .4 T0 _ _ EX5 .4 .3 .3 .3 .3 GF1 GF1 IE1 GATE .3 .3 .3 .3 INT6 TB8 .3 .3 ET1 .3 INT1 _ _ EX4 .3 .2 .2 .2 .2 GF0 GF0 IT1 C/T .2 .2 .2 .2 INT5 RB8 .2 .2 EX1 .2 INT0 _ _ EX3 .2 .1 .1 .1 .1 PDE PDE IE0 M1 .1 .1 .1 .1 INT4 TI .1 .1 ET0 .1 TxD _ _ EX2 .1 .0 .0 .0 .0 IDLE IDLE IT0 M0 .0 .0 .0 .0 INT3 RI .0 .0 EX0 .0 RxD _ _ EADC .0 SMOD PDS SMOD PDS TF1 GATE .7 .7 .7 .7 T2 SM0 .7 .7 EAL – RD _ TR1 C/T .6 .6 .6 .6 CLKOUT SM1 .6 .6 WDT 88H 2) TCON 89H TMOD 8AH 8BH 8CH 8DH TL0 TL1 TH0 TH1 90H 2) P1 98H 2) SCON 99H SBUF A0H2) P2 A8H2) IEN0 A9H IP0 WDTS .5 WR _ _ T1 EALE _ B0H2) P3 B1H SYSCON X1XX XXXXB B1H SYSCON XXXX _ XXXXB4) 00H XX000000B – B8H2) IEN1 B9H IP1 EXEN2 SWDT EX6 – .5 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) For C515-LN/1RN only 4) This register is available without function in C515-LN/1RN Semiconductor Group 3-6 Memory Organization C515 Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content Bit 7 after Reset1) C0H2) IRCON C1H C2H C3H C4H C5H C6H C7H CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H – 00H FFH 00H FFH EXF2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC COCA COCAL COCA COCAL COCA COCAL COCA COCAL H3 3 H2 2 H1 1 H0 0 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY BD .7 .7 .7 .7 .7 .7 .7 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .6 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 I2FR .5 .5 .5 .5 F0 – .5 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .4 .4 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .3 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .2 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .1 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 .0 .0 .0 .0 .0 .0 .0 C8H2) T2CON CAH CRCL CBH CCH CRCH TL2 CDH TH2 D0H2) PSW D8H2) ADCON D9H DAH ADDAT DAPR DBH P6 E0H2) ACC E8H2) P4 F0H2) B F8H2) P5 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 3-7 External Bus Interface C515 4 External Bus Interface The C515 allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C515 is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emissions of the system. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 External Bus Interface C515 a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN MCT03220 RD P2 P0 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 External Bus Interface C515 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: - whenever signal EA is active (low); or - whenever the program counter (PC) content is greater than 1FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). Since the C515-L has no internal program memory, accesses to program memory are always external, and port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the C515-L can never be used as general-purpose I/O. This also applies to the C515-1R when it operates with only an external program memory. 4.2 PSEN, Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C515 the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-3 External Bus Interface C515 4.4 ALE, Address Latch Enable The C515 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 and PC £ 1FFFH) and ALE is switched off by EALE=0, then, ALE will only go active during external data memory accesses (MOVX instructions). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX1XXXXXB LSB 0 – SYSCON 6 – 5 EALE 4 – 3 – 2 – 1 – Bit EALE Function Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. Reserved bits for future use, read by CPU returns undefined values. – Note: The ALE swicth-off feature is available in C515-LM/1RM versions only. In case of the C515-LN/1RN versions, the SYSCON register is present without function. Semiconductor Group 4-4 External Bus Interface C515 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 4-5 External Bus Interface C515 4.6 ROM Protection for the C515 The C515-1R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C515-1R version has to define whether ROM protection has to be selected or not. The C515-1R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected as well as protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C515-1R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different : ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort. The behaviour of the move code instruction, when the code is executed from the external ROM, is in such a way that accessing a code byte from a protected on-chip ROM address is not possible. In this case the state of the EA pin is always latched with the rising edge of RESET and the byte accessed will be invalid. 4.6.1 Unprotected ROM Mode If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-3 is used to read out the contents of the ROM. The AC timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). P1.0 - P1.7 P2.0 - P2.4 Address 1 Address 2 Port 0 Inputs: PSEN = VSS ALE, EA = VIH / VIH2 RESET = VIL2 Data 1 Out Data 2 Out MCT03221 Figure 4-3 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. Then the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines. After a delay time, port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C515 must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. Semiconductor Group 4-6 External Bus Interface C515 4.6.2 Protected ROM Mode If the ROM is protected, the ROM verification mode 2 as shown in figure 4-4 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). ~ ~ RESET 1. ALE Pulse after Reset ~ ~ 12 t CLCL 6 t CLCL ~ ~ ALE Latch ~ ~ Latch ~ ~ ~ ~ Latch Data for Addr. X-16-1 Data for Addr. X-16 Latch Data for Addr. x-16+1 Port 0 ~ ~ ~ ~ Data for Addr. 0 Data for Addr. 1 ~ ~ ~ ~ P3.5 Inputs : ALE = VSS PSEN, EA = VIH RESET = Low : Error High : OK MCT03222 Figure 4-4 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C515 outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way : 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal ROM address 0000H content of internal ROM address 0001H content of internal ROM address 0002H content of internal ROM address 000FH The C515-1R does not output any address information during the ROM verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and is put onto the data bus with the first rising edge of ALE. With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the ROM content of the actual address. If an verify error is detected, the error Semiconductor Group 4-7 External Bus Interface C515 condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C515 must be provided with a system clock at the XTAL pins. Figure 4-5 shows an application example of an external circuitry which allows to verify a protected ROM inside the C515-1R in ROM verification mode 2. With RESET going inactive, the C515-1R starts the ROM verify sequence. Its ALE is clocking a 13-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the contents of the internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the verify operation. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal ROM has been handled, the C515-1R starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM verification. P3.5 Verify Detect Logic Carry CLK 13-Bit Address Counter S ALE 2 kW A0 - A12 C515-1R & RESET Compare Code ROM VCC & Port 0 EA D0 - D7 VCC PSEN CS OE MCS03223 Figure 4-5 ROM Verification Mode 2 - External Circuitry Example Semiconductor Group 4-8 Reset / System Clock C515 5 5.1 Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C515 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. Additional to the hardware reset, which is applied externally to the C515, there exists another internal reset source, the watchdog timer. This chapter deals only with the external hardware reset. The reset input is an active low input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes high again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the reset pin, a pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained when VCC is applied by connecting the reset pin to VSS via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. Semiconductor Group 5-1 Reset / System Clock C515 The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 mF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. a) b) & + RESET RESET C515 c) C515 + RESET C515 MCS03203 Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches are set to FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 to 5) output a one (1). Port 6 is an input-only port. It has no internal latch and therefore the contents of the special function registers P6 depend on the levels applied to port 6. The content of the internal RAM of the C515 is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-2 Reset / System Clock C515 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least one machine cycle; after this time the C515 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-2 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. PCL IN OUT PCH OUT P2 ALE MCT01879 Figure 5-2 CPU Timing after Reset Semiconductor Group 5-3 Reset / System Clock C515 5.3 Oscillator and Clock Circuit XTAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-3 shows the recommended oscillator circuit. C XTAL2 1 - 24 MHz C515 XTAL1 C C = 20 pF ± 10 pF for Crystal Operation MCS03225 Figure 5-3 Recommended Oscillator Circuitry In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-4). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Semiconductor Group 5-4 Reset / System Clock C515 To Internal Timing Circuitry C515 XTAL1 1) XTAL2 C1 C2 1) Crystal or Ceramic Resonator MCS03226 Figure 5-4 On-Chip Oscillator Circuitry To drive the C515 with an external clock source, the external clock signal has to be applied to XTAL2, as shown in figure 5-5. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2. VCC N.C. External Clock Signal C515 XTAL1 XTAL2 MCS03227 Figure 5-5 External Clock Source Semiconductor Group 5-5 Reset / System Clock C515 5.4 System Clock Output For peripheral devices requiring a system clock, the C515 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON), a clock signal with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset. Special Function Register ADCON (Address D8H) MSB DFH BD Reset Value : 00X000000B LSB D8H MX0 ADCON Bit No. D8H DEH CLK DDH – DCH BSY DBH ADM DAH MX2 D9H MX1 The shaded bits are not used for clock output control. Bit CLK Function Clockout enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/12 of the oscillator frequency. Reserved bit for future use. Read by CPU returns undefined value. – The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 5-6. Note : During slow-down operation the frequency of the CLKOUT signal is divided by 8. Semiconductor Group 5-6 Reset / System Clock C515 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-6 Timing Diagram - System Clock Output Semiconductor Group 5-7 On-Chip Peripheral Components C515 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C515 except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C515 has six 8-bit I/O ports and one 8-bit input port for analog/digital input. Port 0 is an opendrain bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET . 6.1.1 Port Structures The C515 generally allows digital I/O on 48 lines grouped into 6 bidirectional C501 compatible 8-bit ports and one 8-bit analog/digital input port. Each port bit (except port 6) consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 to P5 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. These alternate functions of the port pins are listed in table 6-1. When port 6 is used as analog input, an analog channel is switched to the A/D converter through a 3-bit multiplexer, which is controlled by three bits in SFR ADCON (see chapter 6.4). Port 6 lines may also be used as digital inputs. In this case they are addressed as an input port via SFR P6. Since port 6 has no internal latch, the contents of SFR P6 only depends on the levels applied to the input lines. It makes no sense to output a value to these input-only port by writing to the SFR P6. This will have no effect. Semiconductor Group 6-1 On-Chip Peripheral Components C515 Table 6-1 Alternate Functions of Port 1 and 3 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions INT3 / CC0 INT4 / CC1 INT5 / CC2 INT6 / CC3 INT2 T2EX CLKOUT T2 RxD TxD INT0 INT1 T0 T1 WR RD Description External Interrupt 3 input / Capture/compare 0 input/output External Interrupt 4 input / Capture/compare 1 input/output External Interrupt 5 input / Capture/compare 2 input/output External Interrupt 6 input / Capture/compare 3 input/output External Interrupt 2 input Timer 2 external reload/trigger input System clock output Timer 2 external count input Serial port’s receiver data input (asynchronous) or data input/output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external count input Timer 1 external count input External data memory write strobe External data memory read strobe Semiconductor Group 6-2 On-Chip Peripheral Components C515 6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the six I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P4) activate the "read-latch" signal, while others activate the "read-pin" signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-1 Basic Structure of a Port Circuitry Semiconductor Group 6-3 On-Chip Peripheral Components C515 The output drivers of port 1 to 5 have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1 to 5 the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are called "quasi-bidirectional". Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-2 Basic Output Driver Circuit of Ports 1 to 5 Semiconductor Group 6-4 On-Chip Peripheral Components C515 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1’s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Addr./Data Read Latch Control & VCC =1 Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q MUX Read Pin MCS02434 Figure 6-3 Port 0 Circuitry Semiconductor Group 6-5 On-Chip Peripheral Components C515 6.1.2.2 Port 1, Port 3 to Port 5 Circuitry The pins of ports 1, 3, 4, and 5 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-1. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Read Latch Alternate Output Function VCC Internal Pull Up Arrangement Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS01827 Read Pin Alternate Input Function Figure 6-4 Ports 1, 3, 4 and 5 Semiconductor Group 6-6 On-Chip Peripheral Components C515 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-3. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-6) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Addr. Read Latch Control VCC Internal Pull Up Arrangement Port Pin Int. Bus D Bit Latch CLK Q MUX Q =1 Write to Latch Read Pin MCS03228 Figure 6-5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. Semiconductor Group 6-7 On-Chip Peripheral Components C515 Addr. Control VCC Q _ VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 8) Not 100% tested, guaranteed by design characterization 9) The typical ICC values are periodically measured at TA = +25 ˚C and VCC = 5 V but not 100% tested. 10)The maximum ICC values are measured under worst case conditions (TA = 0 ˚C or -40 ˚C and VCC = 5.5 V) Semiconductor Group 10-3 Device Specifications C515 30 mA I CC 25 20 I CC max I CC typ Active Mode Active Mode 15 Idle Mode 10 5 Active Mode with Slow Down 0 0 4 8 12 16 20 MHz f OSC 24 Idle Mode Active mode Idle mode : I CC typ = 0.68 x f OSC + 2.8 : I CC max = 0.85 x f OSC + 4.6 : I CC typ = 0.28 x f OSC + 2.4 : I CC max = 0.39 x f OSC + 3.4 Active mode with slow-down : I CC typ = 0.18 x f OSC + 2.0 : I CC max = 0.23 x f OSC + 3.3 f OSC is the oscillator frequency in MHz. I CC values are given in mA. MCD03282 ICC Diagram Semiconductor Group 10-4 Device Specifications C515 10.3 A/D Converter Characteristics VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C for the SAB-C515 for the SAF-C515 for the SAH-C515 VCC – 0.25 V £ VAREF £ VCC + 0.1 V ; VSS – 0.1 V £ VAGND £ VSS + 0.2 V; VIntAREF - VIntAGND ³ 1 V; Parameter Analog input voltage A/D converter input clock Sample time Conversion cycle time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively. 2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS and the conversion time tCO. The values for the conversion clock tADC is always 4 x tIN. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Symbol Limit Values min. max. Unit V ns ns ns LSB kW kW pF Test Condition 1) VAIN t IN tS tADCC TUE VAGND 0.2 – – – – – – – VAREF + 0.2 2 x t CLCL 40 x tIN 72 x tIN ±1 4 x tIN /500 -1 2) 3) RAREF RASRC CAIN VIntAREF = VAREF = VCC VIntAGND = VAGND = VSS tIN in [ns] 5) 6) tS in [ns] 6) 2) 6) 4) tS / 500 - 1 45 Semiconductor Group 10-5 Device Specifications C515 10.4 AC Characteristics (16 MHz) VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C for the SAB-C515 for the SAF-C515 for the SAH-C515 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 16 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Limit Values Variable Clock 1/tCLCL = 1 MHz to 16 MHz min. 2tCLCL – 40 max. – – – 4tCLCL – 100 – – 3tCLCL – 100 – Unit max. – – – 150 – – 88 – 43 – 198 – tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 85 33 28 – 38 153 – 0 – 55 – 0 ns ns ns ns ns ns ns ns ns ns ns ns tCLCL – 30 tCLCL – 35 – tCLCL – 25 3tCLCL – 35 – 0 – tCLCL – 20 – 5tCLCL – 115 – tCLCL – 8 – 0 Interfacing the C515 to devices with float times up to 55 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. CLKOUT Timing Parameter Symbol 16 MHz Clock min. ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high max. – – – 103 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 16 MHz min. 7 tCLCL – 40 2 tCLCL – 40 10 tCLCL – 40 max. – – – ns ns ns ns Unit tLLSH tSHSL tSLSH tSLLH 398 85 585 23 tCLCL – 40 tCLCL + 40 Semiconductor Group 10-6 Device Specifications C515 AC Characteristics (16 MHz) (cont’d) External Data Memory Characteristics Parameter Symbol 16 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. – – – 148 – 55 350 398 238 – 103 – – – 0 Limit Values Variable Clock 1/tCLCL = 1 MHz to 16 MHz min. 6tCLCL – 100 6tCLCL – 100 max. – – – 5tCLCL – 165 – 2tCLCL – 70 8tCLCL – 150 9tCLCL – 165 3tCLCL + 50 – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 275 275 90 – 0 – – – 138 120 23 13 288 13 – 2tCLCL – 35 – 0 – – – 3tCLCL – 50 4tCLCL – 130 tCLCL – 40 tCLCL – 50 7tCLCL – 150 tCLCL + 40 – – – 0 tCLCL – 50 – External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 1 MHz to 16 MHz min. Oscillator period High time Low time Rise time Fall time max. 1000 ns ns ns ns ns Unit tCLCL tCHCX tCLCX tCLCH tCHCL 62.5 20 20 – – tCLCL – tCLCX tCLCL – tCHCX 20 20 Semiconductor Group 10-7 Device Specifications C515 10.5 AC Characteristics (24 MHz) VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C for the SAB-C515 for the SAF-C515 for the SAH-C515 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 24 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN max. – – – 80 – – 60 – 32 – 148 – Limit Values Variable Clock 1/tCLCL = 1 MHz to 24 MHz min. 2tCLCL – 40 max. – – – 4tCLCL – 87 – – 3tCLCL – 65 – ns ns ns ns ns ns ns ns ns ns ns ns Unit tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 43 17 17 – 22 95 – 0 – 37 – 0 tCLCL – 25 tCLCL – 25 – tCLCL – 20 3tCLCL – 30 – 0 – tCLCL – 10 – 5tCLCL – 60 – tCLCL – 5 – 0 *) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. CLKOUT Timing Parameter Symbol 24 MHz Clock min. ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high max. – – – 82 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 7 tCLCL – 40 2 tCLCL – 40 10 tCLCL – 40 max. – – – ns ns ns ns Unit tLLSH tSHSL tSLSH tSLLH 252 43 377 2 tCLCL – 40 tCLCL + 40 Semiconductor Group 10-8 Device Specifications C515 AC Characteristics (24 MHz) (cont’d) External Data Memory Characteristics Parameter Symbol 24 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. – – – 118 – 63 200 220 175 – 67 – – – 0 Limit Values Variable Clock 1/tCLCL = 1 MHz to 24 MHz min. 6tCLCL – 70 6tCLCL – 70 max. – – – 5tCLCL – 90 – 2tCLCL – 20 8tCLCL – 133 9tCLCL – 155 3tCLCL + 50 – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 180 180 48 – 0 – – – 75 67 17 5 170 15 – 2tCLCL – 35 – 0 – – – 3tCLCL – 50 4tCLCL – 97 tCLCL – 25 tCLCL – 37 7tCLCL – 122 tCLCL + 25 – – – 0 tCLCL – 27 – External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 1 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time max. 1000 ns ns ns ns ns Unit tCLCL tCHCX tCLCX tCLCH tCHCL 41.7 12 12 – – tCLCL – tCLCX tCLCL – tCHCX 12 12 Semiconductor Group 10-9 Device Specifications C515 t LHLL ALE t AVLL t LLPL t LLIV t PLIV PSEN t PLPH t AZPL t LLAX t PXAV t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Program Memory Read Cycle Semiconductor Group 10-10 Device Specifications C515 t WHLH ALE PSEN t LLDV t LLWL RD t RLRH t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL Data IN t RHDZ t RHDX A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Data Memory Read Cycle Semiconductor Group 10-11 Device Specifications C515 t WHLH ALE PSEN t LLWL WR t WLWH t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN Port 0 t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Data Memory Write Cycle Semiconductor Group 10-12 Device Specifications C515 t SLLH ALE t LLSH CLK OUT t SHSL t LLSH t SLSH PSEN RD,WR Program Memory Access Data Memory Access MCT00083 CLKOUT Timing t CLCL VCC- 0.5V 0.7 VCC 0.2 VCC- 0.1 0.45V t CHCL t CLCX t CLCH t CHCX MCT00033 External Clock Drive on XTAL2 Semiconductor Group 10-13 Device Specifications C515 10.6 ROM Verification Characteristics for the C515-1R ROM Verification Mode 1 Parameter Address to valid data Symbol min. Limit Values max. 10 tCLCL ns – Unit tAVQV P1.0 - P1.7 P2.0 - P2.4 Address New Address t AVQV Port 0 Data OUT New Data Out Inputs : PSEN = VSS ALE, EA = VIH RESET = VIL2 MCT03212 Address : P1.0 - P1.7 = A0 - A7 P2.0 - P2.4 = A8 - A12 Data : P0.0 - P0.7 = D0 - D7 ROM Verification Mode 1 Semiconductor Group 10-14 Device Specifications C515 ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL – – max. – – 4 tCLCL – – 24 ns ns ns ns ns MHz – – – 8 tCLCL – 1 Unit tAWD tACY tDVA tDSA tAS 1/ tCLCL tCLCL – t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.5 MCT02613 ROM Verification Mode 2 Semiconductor Group 10-15 Device Specifications C515 VCC -0.5 V 0.2 VCC+0.9 Test Points 0.2 VCC -0.1 MCT00039 0.45 V AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. AC Testing: Input, Output Waveforms VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points VOH -0.1 V VOL +0.1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ³ ± 20 mA AC Testing: Float Waveforms Crystal Oscillator Mode Driving from External Source C XTAL1 N.C. XTAL1 1-24 MHz C XTAL2 External Oscillator Signal XTAL2 Crystal Mode : C = 20 pF±10 pF (incl. stray capacitance) MCS03204 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 10-16 Device Specifications C515 10.7 Package Information (P-LCC-68) Plastic Package, P-LCC-68 (SMD) (Plastic Lead Chip-Carrier) 5.08 max 0.5 min 3.5 ±0.2 1.2 x 45˚ 1.27 0.43 ±0.1 0.81 max 0.18 M A-B D 68x 20.32 D 0.1 0.2 23.3 ±0.3 24.21 ±0.07 1) 25.28 -0.26 0.38 M A-B D 34x A B 0.5 x 45˚ 3x 68 1 1.1 x 45˚ Index Marking 24.21 ±0.07 1) 25.28 -0.26 1) Does not include plastic or metal protrusions of 0.15 max per side GPL05099 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 10-17 Dimensions in mm Device Specifications C515 10.8 Package Information (P-MQFP-80) Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.25 min 2 +0.1 -0.05 2.45 max 0.65 0.3 ±0.08 12.35 17.2 14 1) 0.88 C 0.12 0.1 M A-B D C 80x 0.2 A-B D 80x 0.2 A-B D H 4x D A B 14 1) 17.2 80 1 Index Marking 0.6x45˚ GPM05249 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 10-18 Dimensions in mm 7˚max H 0.15 +0.08 -0.02 Index C515 11 Index A/D converter . . . . . . . . . . . . . . . 6-57–6-68 Conversion timing . . . . . . . . . . 6-66–6-68 General operation . . . . . . . . . . . . . . 6-57 Programmable reference voltages . 6-62– 6-65 Registers . . . . . . . . . . . . . . . . . 6-59–6-61 A/D converter characteristics . . . . . . . 10-5 Absolute maximum ratings . . . . . . . . . 10-1 AC . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 AC characteristics . . . . . . . . . . . 10-6–10-16 16 MHz timing . . . . . . . . . . . . . 10-6–10-7 24 MHz timing . . . . . . . . . . . . . 10-8–10-9 CLKOUT timing . . . . . . . . . . . . . . . 10-13 Data memory read cycle . . . . . . . . 10-11 Data memory write cycle . . . . . . . . 10-12 External clock timing . . . . . . . . . . . 10-13 Program memory read cycle . . . . . 10-10 ROM verification mode 1 . . . . . . . . 10-14 ROM verification mode 2 . . . . . . . . 10-15 AC Testing Float waveforms . . . . . . . . . . . . . . 10-16 Input/output waveforms . . . . . . . . . 10-16 ACC . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-7 ADCON . . . . . 3-4, 3-5, 3-7, 5-6, 6-44, 6-59 ADDAT . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-60 ADM . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-59 ALE signal . . . . . . . . . . . . . . . . . . . . . . . 4-4 A COCAH0 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH1 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH2 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH3 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL0 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL1 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL2 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL3 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 CPU Accumulator . . . . . . . . . . . . . . . . . . . .2-2 B register . . . . . . . . . . . . . . . . . . . . . . .2-3 Basic timing . . . . . . . . . . . . . . . . . . . . .2-4 Fetch/execute diagram . . . . . . . . . . . .2-5 Functionality . . . . . . . . . . . . . . . . . . . .2-2 Program status word . . . . . . . . . . . . . .2-2 Stack pointer . . . . . . . . . . . . . . . . . . . .2-3 CPU timing . . . . . . . . . . . . . . . . . . . . . . .2-5 CRCH . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-26 CRCL . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-26 CY . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 D DAPR . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-62 DC characteristics . . . . . . . . . . . . 10-2–10-4 Device characteristics . . . . . . . . 10-1–10-18 DPH . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 DPL . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 E EADC . . . . . . . . . . . . . . . . . . 3-6, 6-61, 7-5 EAL . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Emulation concept . . . . . . . . . . . . . . . . .4-5 ES . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 ET0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 ET1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 ET2 . . . . . . . . . . . . . . . . . . . . 3-6, 6-27, 7-4 EX0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EX1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-4 EX2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 EX3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 EX4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 EX5 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 EX6 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-5 Execution of instructions . . . . . . . . . . . . .2-4 EXEN2 . . . . . . . . . . . . . . . . . 3-6, 6-27, 7-5 EXF2 . . . . . . . . . . . . . . . . . . . 3-7, 6-27, 7-8 External bus interface . . . . . . . . . . . 4-1–4-4 ALE signal . . . . . . . . . . . . . . . . . . . . . .4-4 B B . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-7 Basic CPU timing . . . . . . . . . . . . . . . . . 2-4 BD . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-44 Block diagram . . . . . . . . . . . . . . . . . . . . 2-1 BSY . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-59 C C/T . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17 CCEN . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-28 CCH1 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-31 CCH2 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-31 CCH3 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-31 CCL1 . . . . . . . . . . . . . . . . . . . . . . . 3-4, 6-31 CCL2 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-31 CCL3 . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-31 CLK . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 5-6 CLKOUT . . . . . . . . . . . . . . . . . . . . . 3-6, 5-6 Semiconductor Group 11-1 Index C515 Overlapping of data/program memory Program memory access . . . . . . . . . . Program/data memory timing . . . . . . PSEN signal . . . . . . . . . . . . . . . . . . . . Role of P0 and P2 . . . . . . . . . . . . . . . 4-3 4-3 4-2 4-3 4-1 F F0 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 F1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 Fail save mechanisms . . . . . . . . . . . 8-1–8-4 Features . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional units . . . . . . . . . . . . . . . . . . . 1-1 Fundamental structure . . . . . . . . . . . . . 2-1 External interrupts . . . . . . . . . . . . . . .7-15 Handling procedure . . . . . . . . . . . . . .7-13 Priority registers . . . . . . . . . . . . . . . .7-11 Priority within level structure . . . . . . .7-12 Request flags . . . . . . . . . . . . . . 7-6–7-10 Response time . . . . . . . . . . . . . . . . .7-17 Sources and vector addresses . . . . .7-14 IP0 . . . . . . . . . . . . . . . . . 3-5, 3-6, 7-11, 8-4 IP1 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 7-11 IRCON . . . . . . . . . 3-4, 3-7, 6-27, 6-61, 7-8 IT0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6 IT1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6 G GATE . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17 GF0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 GF1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 L Logic symbol . . . . . . . . . . . . . . . . . . . . . .1-3 M M0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17 M1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17 Memory organization . . . . . . . . . . . 3-1–3-2 Data memory . . . . . . . . . . . . . . . . . . . .3-2 General purpose registers . . . . . . . . . .3-2 Memory map . . . . . . . . . . . . . . . . . . . .3-1 Program memory . . . . . . . . . . . . . . . .3-2 MX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 MX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 MX2-0 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 H Hardware reset . . . . . . . . . . . . . . . . . . . 5-1 I I/O ports . . . . . . . . . . . . . . . . . . . . . 6-1–6-13 I2FR . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-7 I3FR . . . . . . . . . . . . . . . . . . . . 3-7, 6-25, 7-7 IADC . . . . . . . . . . . . . . . . . . . 3-7, 6-61, 7-8 IDLE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Idle mode . . . . . . . . . . . . . . . . . . . . . 9-3–9-4 IDLS . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 IE0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6 IE1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6 IEN0 . . . . . . . . 3-4, 3-5, 3-6, 6-27, 7-4, 8-4 IEN1 . . . . 3-4, 3-5, 3-6, 6-27, 6-61, 7-5, 8-4 IEX2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8 IEX3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8 IEX4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8 IEX5 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8 IEX6 . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8, 7-8 INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 INT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Interrupt system . . . . . . . . . . . . . . . 7-1–7-17 Interrupts Block diagram . . . . . . . . . . . . . . . 7-2–7-3 Enable registers . . . . . . . . . . . . . . 7-4–7-5 O Oscillator operation . . . . . . . . . . . . . 5-4–5-5 External clock source . . . . . . . . . . . . .5-5 On-chip oscillator circuitry . . . . . . . . . .5-5 Recommended oscillator circuit . . . . .5-4 OV . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 P P . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 P1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6 P2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6 P3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6 P4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7 P5 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7 P6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7 Package information (P-LCC-68) . . . .10-17 Package information (P-MQFP-80) . .10-18 Parallel I/O . . . . . . . . . . . . . . . . . . 6-1–6-13 PCON . . . . . . . . . . . . . . . 3-5, 3-6, 6-44, 9-2 PDE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Semiconductor Group 11-2 Index C515 PDS . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Pin configuration . . . . . . . . . . . . . . . . . . 1-4 P-MQFP-80 package . . . . . . . . . . 1-4, 1-5 Pin definitions and functions . . . . . 1-6–1-10 Ports . . . . . . . . . . . . . . . . . . . . . . . 6-1–6-13 Alternate functions . . . . . . . . . . . . . . . 6-2 Loading and interfacing . . . . . . . . . . 6-12 Output driver circuitry . . . . . . . . . 6-9–6-10 Output/input sample timing . . . . . . . 6-11 Read-modify-write operation . . . . . . 6-13 Types and structures . . . . . . . . . . . . . 6-1 Port 0 circuitry . . . . . . . . . . . . . . . . 6-5 Port 1/3/4/5 circuitry . . . . . . . . . . . . 6-6 Port 2 circuitry . . . . . . . . . . . . . . . . 6-7 Standard I/O port circuitry . . . . 6-3–6-4 Power down mode . . . . . . . . . . . . . . . . . 9-6 Entry procedure . . . . . . . . . . . . . . . . . 9-6 Exit procedure . . . . . . . . . . . . . . . . . . 9-6 Power saving modes . . . . . . . . . . . . 9-1–9-7 Control register . . . . . . . . . . . . . . . . . 9-2 Hardware enable . . . . . . . . . . . . . . . . 9-1 Idle mode . . . . . . . . . . . . . . . . . . . 9-3–9-4 Power down mode . . . . . . . . . . . . . . . 9-6 Slow down mode . . . . . . . . . . . . . . . . 9-5 State of pins . . . . . . . . . . . . . . . . . . . . 9-7 Power supply current . . . . . . . . . . 10-3–10-4 PSEN signal . . . . . . . . . . . . . . . . . . . . . 4-3 PSW . . . . . . . . . . . . . . . . . . . . 2-3, 3-4, 3-7 S SBUF . . . . . . . . . . . . . . . . . . 3-5, 3-6, 6-43 SCON . . . . . . . . . . 3-4, 3-5, 3-6, 6-43, 7-10 SD . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Serial interface (USART) . . . . . . 6-41–6-56 Baudrate generation . . . . . . . . . . . . .6-44 with internal baud rate generator . .6-46 with timer 1 . . . . . . . . . . . . . . . . . .6-46 Multiprocessor communication . . . . .6-42 Operating mode 0 . . . . . . . . . . 6-48–6-50 Operating mode 1 . . . . . . . . . . 6-51–6-53 Operating mode 2 and 3 . . . . . 6-54–6-56 Registers . . . . . . . . . . . . . . . . . 6-42–6-43 Slow down mode . . . . . . . . . . . . . . . . . .9-5 SM0 . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43 SM1 . . . . . . . . . . . . . . . . . . 3-6, 6-43, 6-43 SM2 . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43 SMOD . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-44 SP . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6 Special Function Registers . . . . . . . . . . .3-3 Table - address ordered . . . . . . . 3-6–3-7 Table - functional order . . . . . . . . 3-4–3-5 SWDT . . . . . . . . . . . . . . . . . . . . . . . 3-6, 8-4 SYSCON . . . . . . . . . . . . . . . . . 3-4, 3-6, 4-4 System clock output . . . . . . . . . . . . 5-6–5-7 T T0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 T2CM . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 T2CON . . . . . . . . . . 3-4, 3-5, 3-7, 6-25, 7-7 T2EX . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 T2I0 . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 T2I1 . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 T2PS . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 T2R0 . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 T2R1 . . . . . . . . . . . . . . . . . . . . . . . 3-7, 6-25 TB8 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43 TCON . . . . . . . . . . . . . . . 3-4, 3-6, 6-16, 7-6 TF0 . . . . . . . . . . . . . . . . . . . . 3-6, 6-16, 7-6 TF1 . . . . . . . . . . . . . . . . . . . . 3-6, 6-16, 7-6 TF2 . . . . . . . . . . . . . . . . . . . . 3-7, 6-27, 7-8 TH0 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-15 TH1 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-15 TH2 . . . . . . . . . . . . . . . . . . . . 3-4, 3-7, 6-26 TI . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43, 7-10 Timer/counter . . . . . . . . . . . . . . . 6-14–6-40 R RB8 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43 RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Recommended oscillator circuits . . . . 10-16 REN . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43 Reset . . . . . . . . . . . . . . . . . . . . . . . . 5-1–5-3 Hardware reset timing . . . . . . . . . . . . 5-3 Reset circuitries . . . . . . . . . . . . . . . . . 5-2 RI . . . . . . . . . . . . . . . . . . . . . 3-6, 6-43, 7-10 ROM protection . . . . . . . . . . . . . . . . 4-6–4-8 Protected ROM mode . . . . . . . . . . . . 4-7 Protected ROM verification example . 4-8 Protected ROM verify timing . . . . . . . 4-7 Unprotected ROM mode . . . . . . . . . . 4-6 Unprotected ROM verify timing . . . . . 4-6 RS0 . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 RS1 . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7 RxD . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-41 Semiconductor Group 11-3 Index C515 Timer/counter 0 and 1 . . . . . . . 6-14–6-21 Mode 0, 13-bit timer/counter . . . . 6-18 Mode 1, 16-bit timer/counter . . . . 6-19 Mode 2, 8-bit rel. timer/counter . . 6-20 Mode 3, two 8-bit timer/counter . . 6-21 Registers . . . . . . . . . . . . . . . 6-15–6-17 Timer/counter 2 . . . . . . . . . . . . 6-22–6-40 Alternate port functions . . . . . . . . 6-22 Block diagram . . . . . . . . . . . . . . . 6-23 Capture function . . . . . . . . . . 6-39–6-40 Compare function . . . . . . . . . 6-31–6-36 Compare mode 0 . . . . . . . . . 6-31–6-34 Compare mode 1 . . . . . . . . . 6-35–6-36 Compare mode interrupts . . . . . . 6-37 General operation . . . . . . . . . . . . 6-29 Registers . . . . . . . . . . . . . . . 6-24–6-28 Reload mode . . . . . . . . . . . . . . . . 6-30 Timings CLKOUT timing . . . . . . . . . . . . . . . 10-13 Data memory read cycle . . . . . . . . 10-11 Data memory write cycle . . . . . . . . 10-12 External clock timing . . . . . . . . . . . 10-13 Program memory read cycle . . . . . 10-10 ROM verification mode 1 . . . . . . . . 10-14 ROM verification mode 2 . . . . . . . . 10-15 TL0 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-15 TL1 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-15 TL2 . . . . . . . . . . . . . . . . . . . . 3-5, 3-7, 6-26 TMOD . . . . . . . . . . . . . . . . . . 3-4, 3-6, 6-17 TR0 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 TR1 . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-16 TxD . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-41 W Watchdog timer . . . . . . . . . . . . . . . . 8-1–8-4 Block diagram . . . . . . . . . . . . . . . . . . 8-3 Control and status flags . . . . . . . . . . . 8-4 General operation . . . . . . . . . . . . . . . 8-1 Refreshing of the WDT . . . . . . . . . . . 8-2 Reset operation . . . . . . . . . . . . . . . . . 8-2 Starting of the WDT . . . . . . . . . . . . . . 8-1 WDT . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 8-4 WDTS . . . . . . . . . . . . . . . . . . . . . . . 3-6, 8-4 WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Semiconductor Group 11-4