C515C

C515C 8-Bit CMOS Microcontroller User's Manual 11.97 ht tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ Edition 11.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. General Information C515C C515C User’s Manual Revision History : Previous Releases : Page (new version) general 1-1 1-9 Table 1-1 2-2 3-2 3-3, 3-11, 4-4, 6-4, Tab.3-2/3-3 Tab.3-2 / 3-3, pg.9-2 3-17 4-2, 4-5 4-3 4-10 - 4-12 4-11 4-12 6-6 6-10, 6-11 6-18 6-39, 6-43 6-67 6-72 6-105, 6-106 6-108 6-109 7-2 9-6, 9-7 9-7 9-8 9-15 Chapter 10 11-1 11-4 - 11-6 11-10 11-11 11-14 to 11-17 1-1 1-9 Table 1-1 2-2 3-2 3-3, 3-11, 4-4, 6-4, Tab.3-2/3-3 Tab.3-2 / 3-3, pg.9-2 3-17 4-2, 4-5 4-3 4-10 - 4-12 4-11 4-12 6-6 6-10, 6-11 6-18 6-39, 6-43 6-67 6-72 6-105, 6-106 6-108 7-2 9-6, 9-7 9-7 9-8 9-15 10-1 10-3 10-8 10-10 - 11.97 06.96 (Original Version) Page (prev. Subjects (changes since last revision) version) C515C-8E OTP version included (new chapter 10) C515C AC/DC characteristics are now in chapter 11 Description of the new features of the C515C-8E; figure 1-1 modified PSEN and ALE are activated every three (and not six) osc. periods Ports 1 to 5 and 7 descriptions are corrected to quasi-bidirectional Figure 2-1 modified for C515C-8E Section 3.1 : C515C-8E version included Description of SYSCON : bit CSWO and C515C-8E reset value added Description of PCON1 : bit WS and C515C-8E reset value added Reset value of P4 and table entry for bit P7.0 (INT7) corrected; Version registers for C515C-8E added Figure 4-1 and 4-2 corrected 3rd paragraph of chapter 4.1.3 removed Chapter 4.7 “ROM Protection...“ enhanced for OTP verification Figure 4-5 corrected Figure 4-5 : OTP version reference added Figure 6-4 and text : delay part corrected Figures 6-7 and 6-8 : delay part corrected Figure 6-14 corrected Figure 6-22 and 6-26 : figure content exchanged 6.4.3.: first paragraph, divider range corrected Baudrate selection bits corrected multiple formulas corrected last paragraph added Chapter 6.5.8 (CAN switch-off capability) added Figure 7-1 : bit address for bit RXIE added Adding P4.7/RXDC wake-up capability to the description Figure 9-1 corrected Additional text in last paragraph before 9.5 Note below figure 9-5 added New chapter : describes OTP programming of the C515C-8E Minimum value for ambient temperature under bias corrected to –40˚C Improved and extended Icc specification SSC timing parameter tSCLK (master mode) and tHI improved Wrong figure “External Clock Cycle“ exchanged with correct figure Programming interface characteristics added Semiconductor Group General Information C515C Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.7 4.7.1 4.7.2 5 5.1 5.2 5.3 5.4 5.5 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 XRAM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 XRAM/CAN Controller Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . 3-5 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode). . . . . . . . . 3-5 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Overlapping External Data and Program Memory Spaces. . . . . . . . . . . . . . . . . . . . 4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 How the eight Datapointers of the C515C are realized . . . . . . . . . . . . . . . . . . . . . . 4-6 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 ROM/OTP Protection for the C515C-8R / C515C-8E . . . . . . . . . . . . . . . . . . . . . . 4-10 Unprotected ROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Protected ROM/OTP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-3 5-4 5-6 5-8 Semiconductor Group I-1 1997-11-01 General Information C515C Table of Contents 6 6.1 6.1.1 6.1.1.1 6.1.1.2 6.1.1.2.1 6.1.1.2.2 6.1.1.2.3 6.1.1.2.4 6.1.1.3 6.1.1.3.1 6.1.1.3.2 6.1.1.3.3 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.3.1 6.2.2.3.2 6.2.2.3.3 6.2.2.4 6.2.2.5 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.3.1 6.3.3.3.2 6.3.4 6.3.5 Page On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structure Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Quasi-Bidirectional Port Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Basic Port Circuirty of Port 1 to 5 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 SSC Port Pins of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Bidirectional (CMOS) Port Structure of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Hardware Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Alternate Functions of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Port Loading and Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Read-Modify-Write Feature of Ports 1 to 5 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Timer/Counter 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . . . 6-29 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Timer 2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . . . . . . 6-38 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 Modulation Range in Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . . . 6-44 Capture Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Serial Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Baud Rate in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Using the Internal Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 Semiconductor Group I-2 1997-11-01 General Information C515C Table of Contents 6.3.6 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.6.1 6.4.6.2 6.4.7 6.5 6.5.1 6.5.2 6.5.2.1 6.5.2.2 6.5.3 6.5.4 6.5.5 6.5.5.1 6.5.5.2 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 Page Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 Write Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71 The On-Chip CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 Basic CAN Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77 CAN Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81 General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81 The Message Object Registers / Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91 Handling of Message Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 Configuration of the Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105 Hard Synchronization and Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106 Calculation of the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106 CAN Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107 CAN Controller in Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108 Switch-off Capability of the CAN Controller (C515C-8E only) . . . . . . . . . . . . . . . 6-109 Configuration Examples of a Transmission Object. . . . . . . . . . . . . . . . . . . . . . . . 6-110 Configuration Examples of a Reception Object . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111 The CAN Application Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113 A/D Converter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115 A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-119 A/D Conversion Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-120 A/D Converter Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-124 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 Semiconductor Group I-3 1997-11-01 General Information C515C Table of Contents 8 8.1 8.1.1 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.4 8.1.5 8.2 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.5 9.6 9.7 9.8 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.5 10.6 10.7 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 Page 8-1 8-1 8-2 8-3 8-4 8-4 8-4 8-5 8-5 8-6 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Control / Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The First Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . The Second Possibility of Starting the Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Power Saving Mode Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Slow Down Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Invoking Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Exit from Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . . . . . . . 9-8 Hardware Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Hardware Power Down Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 CPUR Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 OTP Memory Operation (C515C-8E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Basic Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 AC Characteristics for C515C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 OTP Memory Programming Mode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11-14 ROM/OTP Verification Characteristics for C515C-8R / C515C-8E . . . . . . . . . . 11-18 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Semiconductor Group I-4 1997-11-01 Introduction C515C 1 Introduction The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K byte of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 µs at 6 MHz). The C515C-8R contains a non-volatile 64k byte read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory The C515C-8E is the OTP version in the C515C microcontroller with a 64k byte one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 µsec). Also several levels of OTP memory protection can be selected. If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally provides two features : – the wake-up from software power down mode can, additionally to the external pin P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin P4.7/RXDC. – for power consumption reasons the on-chip CAN controller can be switched off The term C515C refers to all versions within this documentation unless otherwise noted. Figure 1-1 shows the different functional units of the C515C and figure 1-2 shows the simplified logic symbol of the C515C. On-Chip Emulation Support Module SSC (SPI) Interface Oscillator Watchdog Power Save Modes Idle/ Power down Slow down Port 7 Port 6 Full-CAN Controller 10 Bit ADC (8 inputs) Timer 2 Capture/Compare Unit Port 5 Port 4 T1 XRAM 2k x 8 RAM 256 x 8 Port 0 I/O T0 CPU 8 Datapointer 8 Bit USART Port 1 I/O Port 2 Program Memory C515C-8R : 64k x 8 ROM C515C-8E : 64k x 8 OTP I/O Port 3 I/O I/O Analog/ Digital Input I/O I/O MCA03646 Figure 1-1 C515C Functional Units Semiconductor Group 1-1 1997-11-01 Introduction C515C Listed below is a summary of the main features of the C515C: • • • • • • • • • • • • • • • • • • • • • • • Full upward compatibility with SAB 80C515A On-chip program memory (with optional memory protection) – C515C-8R : 64k byte on-chip ROM – C515C-8E : 64k byte on-chip OTP – alternatively up to 64k byte external program memory 256 byte on-chip RAM 2K byte on-chip XRAM Up to 64K byte external data memory Superset of the 8051 architecture with 8 datapointers Up to 10 MHz external operating frequency – without clock prescaler (1 µs instruction cycle time at 6 MHz external clock) On-chip emulation support logic (Enhanced Hooks Technology TM) Current optimized oscillator circuit Eight ports: 48 + 1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels) Three 16-bit timer/counters – Timer 2 can be used for compare/capture functions 10-bit A/D converter with multiplexed inputs and Built-in self calibration Full duplex serial interface with programmable baudrate generator (USART) SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 2.5 MHz transfer rate at 10 MHz operating frequency Full-CAN Module – 256 register/data bytes are located in external data memory area – max.1 MBaud at 10 MHz operating frequency Seventeen interrupt vectors, at four priority levels selectable Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog Power saving modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake-up capability through INT0 or RXDC pin – Hardware power-down mode CPU running condition output pin ALE can be switched off Multiple separate VCC/VSS pin pairs P-MQFP-80 package Temperature Ranges: SAB-C515C TA = 0 to 70 °C SAF-C515C TA = – 40 to 85 °C SAH-C515C TA = – 40 to 110 °C Semiconductor Group 1-2 1997-11-01 Introduction C515C VAGND VAREF Port 0 8 Bit Digital I/O XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD HWPD CPUR Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O C515C Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Inputs Port 7 1 Bit Digital I/O VSSE1 VCCE1 VSSE2 VCCE2 VSS1 VCC1 VSSCLK VCCCLK VSSEXT VCCEXT MCL02714 Figure 1-2 Logic Symbol Semiconductor Group 1-3 1997-11-01 Introduction C515C 1.1 Pin Configuration This section describes the pin configuration of the C515C in the P-MQFP-80 package. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VCCE2 HWPD VSSE2 N.C. P4.0/ADST P4.1/SCLK P4.2/SRI PE/SWD P4.3/STO P4.4/SLS P4.5/INT8 P4.6/TXDC P4.7/RXDC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 VSSE1 VSS1 VCC1 VCCE1 P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2 P1.5/T2EX P1.6/CLKOUT P1.7/T2 P7.0/INT7 P3.7/RD P3.6/WR RESET N.C. VAREF VAGND P6.7/AIN7 P6.6/AIN6 P6.5/AIN5 P6.4/AIN4 P6.3/AIN3 P6.2/AIN2 P6.1/AIN1 P6.0/AIN0 VSSCLK VCCCLK P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P5.7 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VSSEXT VCCEXT EA ALE PSEN CPUR P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 C515C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCP02715 Figure 1-3 Pin Configuration (top view) Semiconductor Group 1-4 1997-11-01 Introduction C515C 1.2 Pin Definitions and Functions This section describes all external signals of the C515C with its function. Table 1-1 Pin Definitions and Functions Symbol P4.0-P4.7 Pin Number P-MQFP-80 72-74, 76-80 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST External A/D converter start pin P4.1 SCLK SSC Master Clock Output / SSC Slave Clock Input P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS Slave Select Input P4.5 INT8 External interrupt 8 input P4.6 TXDC Transmitter output of the CAN controller P4.7 RXDC Receiver input of the CAN controller Power saving mode enable / Start watchdog timer A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . I/O*) Function 72 73 74 76 77 78 79 80 PE/SWD 75 I RESET 1 I *) I = Input O = Output Semiconductor Group 1-5 1997-11-01 Introduction C515C Table 1-1 Pin Definitions and Functions (cont’d) Symbol VAREF VAGND P6.7-P6.0 Pin Number P-MQFP-80 3 4 5-12 – – I Reference voltage for the A/D converter Reference ground for the A/D converter Port 6 is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs. Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 TXD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 INT0 External interrupt 0 input / timer 0 gate control input External interrupt 1 input / timer 1 P3.3 INT1 gate control input P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR WR control output; latches the data byte from port 0 into the external data memory P3.7 RD RD control output; enables the external data memory I/O*) Function P3.0-P3.7 15-22 I/O 15 16 17 18 19 20 21 22 *) I = Input O = Output Semiconductor Group 1-6 1997-11-01 Introduction C515C Table 1-1 Pin Definitions and Functions (cont’d) Symbol P7.0 Pin Number P-MQFP-80 23 I/O Port 7 is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7 Interrupt 7 input Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3 CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 INT4 CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 INT5 CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 INT6 CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger input P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input I/O*) Function P1.0 - P1.7 31-24 I/O 31 30 29 28 27 26 25 24 *) I = Input O = Output Semiconductor Group 1-7 1997-11-01 Introduction C515C Table 1-1 Pin Definitions and Functions (cont’d) Symbol XTAL2 Pin Number P-MQFP-80 36 – XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL1 Output of the inverting oscillator amplifier. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. CPU running condition This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET signal CPUR is set to high level. CPUR can be typically used for switching external memory devices into power saving modes. I/O*) Function XTAL1 P2.0-P2.7 37 38-45 – I/O CPUR 46 O *) I = Input O = Output Semiconductor Group 1-8 1997-11-01 Introduction C515C Table 1-1 Pin Definitions and Functions (cont’d) Symbol PSEN Pin Number P-MQFP-80 47 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every three oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally. External Access Enable When held high, the C515C executes instructions always from internal program memory. When EA is held low, all instructions are fetched from external program memory. EA should not be driven during reset operation Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C-8E. External pullup resistors are required during program. Port 5 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output. I/O*) Function ALE 48 O EA 49 I P0.0-P0.7 52-59 I/O P5.7-P5.0 60-67 I/O *) I = Input O = Output Semiconductor Group 1-9 1997-11-01 Introduction C515C Table 1-1 Pin Definitions and Functions (cont’d) Symbol HWPD Pin Number P-MQFP-80 69 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating. Supply voltage for internal logic This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode. Ground (0 V) for internal logic This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode. Supply voltage for I/O ports These pins are used for power supply of the I/O ports during normal, idle, and power-down mode. Ground (0 V) for I/O ports These pins are used for ground connections of the I/O ports during normal, idle, and power-down mode. Supply voltage for external access pins This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD). Ground (0 V) for external access pins This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD). Supply voltage for on-chip oscillator This pin is used for power supply of the on-chip oscillator circuit. Ground (0 V) for on-chip oscillator This pin is used for ground connection of the on-chip oscillator circuit. Not connected These pins should not be connected. I/O*) Function VCC1 33 – VSS1 34 – VCCE1 VCCE2 VSSE1 VSSE2 VCCEXT 32 68 35 70 50 – – – VSSEXT 51 – VCCCLK 14 – VSSCLK 13 – N.C. *) I = Input O = Output 2, 71 – Semiconductor Group 1-10 1997-11-01 Fundamental Structure C515C 2 Fundamental Structure The C515C is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C515C incorporates a CPU with 8 datapointers, a genuine 10-bit A/D converter, a capture/compare unit, a Full-CAN controller unit, a SSC synchronous serial interface, a USART serial interface, a XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C515C. Semiconductor Group 2-1 1997-11-01 Fundamental Structure C515C Oscillator Watchdog XTAL1 XTAL2 ALE PSEN EA CPUR PE/SWD HWPD RESET Timer 1 Port 1 Timer 2 Capture Compare Unit Port 2 Timer 0 Port 0 Programmable Watchdog Timer CPU 8 Datapointers Emulation Support Logic XRAM 2k x 8 OSC & Timing RAM 256 x 8 ROM/OTP 64k x 8 Multiple V CC /V SS Lines Port 0 8 Bit Digital I/O Port 1 8 Bit Digital I/O Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O Port 4 8 Bit Digital I/O Port 5 8 Bit Digital I/O Port 6 8 Bit Analog/ Digital Inputs Port 7 1 Bit Digital I/O USART Baud Rate Generator SSC (SPI) Interface 256 Byte Reg./Data Port 3 Port 4 Full-CAN Controller Port 5 Interrupt Unit V AREF V AGND S&H A/D Converter 10 Bit MUX Port 6 Port 7 C515C MCB03647 Figure 2-1 Block Diagram of the C515C Semiconductor Group 2-2 1997-11-01 Fundamental Structure C515C 2.1 CPU The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 6 MHz external clock, 58% of the instructions execute in 1.0 µs (10 MHz: 600 ns). The CPU (Central Processing Unit) of the C515C consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Additionally to the CPU functionality of the C501/8051 standard microcontroller, the C515C contains 8 datapointers. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-3 1997-11-01 Fundamental Structure C515C Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-4 1997-11-01 Fundamental Structure C515C 2.2 CPU Timing The C515C has no clock prescaler. Therefore, a machine cycle of the C515C consists of 6 states (6 oscillator periods). Each state is divided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Semiconductor Group 2-5 1997-11-01 Fundamental Structure C515C S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL1) ALE Read Opcode S1 S2 S3 S4 Read next Opcode (Discard) S5 S6 Read next Opcode again a) 1 Byte, 1-Cycle Instruction, e.g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 Read next Opcode b) 2 Byte, 1-Cycle Instruction, e.g. ADD A, # Data Read next Opcode again Read Opcode S1 S2 S3 S4 Read next Opcode (Discard) S5 S6 S1 S2 S3 S4 S5 S6 c) 1 Byte, 2-Cycle Instruction, e.g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read next Opcode (Discard) S5 ADDR S6 S1 Read next Opcode again No Fetch No ALE S2 DATA MCD02638 No Fetch S3 S4 S5 S6 d) MOVX (1 Byte, 2-Cycle) Access of External Memory Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-6 1997-11-01 Memory Organization C515C 3 Memory Organization The C515C CPU manipulates operands in the following four address spaces: – – – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 256 bytes CAN controller registers / data memory 2K bytes of internal XRAM data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C515C. Alternatively FFFF H Internal XRAM (2 KByte) F800 H Int. CAN Controller (256 Byte) F6FF H External (EA = 0) External F7FF H FFFF H External Data Memory Internal (EA = 1) F700 H Indirect Address FF H Internal RAM 80 H Internal RAM Direct Address Special Function Register 7F H FF H 80 H 0000 H "Code Space" "Data Space" 0000 H 00 H "Internal Data Space" MCD02717 Figure 3-1 C515C Memory Map Semiconductor Group 3-1 1997-11-01 Memory Organization C515C 3.1 Program Memory, "Code Space" The C515C-8R provides 64 Kbytes of read-only program memory while the C515C-L has no internal program memory. The C515C-8E provides 64 Kbytes of OTP program memory.. For internal ROM/OTP program execution the EA pin must be put to high level. The 64K bytes program memory can also be located completely external. If the EA pin is held low, the C515C fetches all instructions from an external program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal CAN controller and the internal XRAM are located in the external address memory area at addresses F700H to FFFFH. Using MOVX instruction with addresses pointing to this address area, alternatively XRAM and CAN controller registers or external XRAM are accessed. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 1997-11-01 Memory Organization C515C 3.4 XRAM Operation The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. 3.4.1 XRAM/CAN Controller Access Control Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM/CAN controller accesses. Special Function Register SYSCON (Address B1H) Reset Value C515C-8R : X010XX01B Reset Value C515C-8E : X010X001B LSB 0 SYSCON Bit No. MSB 7 B1H – 6 5 4 RMAP 3 – 2 1 PMOD EALE CSWO XMAP1 XMAP0 The function of the shaded bit is not described in this section. Bit – XMAP1 Function Not implemented. Reserved for future use. XRAM/CAN controller visible access control Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. Global XRAM/CAN controller access enable/disable control XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. XMAP0 When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and WR become active and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted. Semiconductor Group 3-3 1997-11-01 Memory Organization C515C After a reset operation, bit XMAP0 is reset. This means that the accesses to XRAM and CAN controller are generally disabled. In this case, all accesses using MOVX instructions within the address range of F700H to FFFFH generate external data memory bus cycles. When XMAP0 is set, the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with an address in the range of F700H to FFFFH will access internal XRAM or CAN controller. Bit XMAP0 is hardware protected. If it is reset once (XRAM and CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an unsymmetric latch at XMAP0 bit. A unintentional disabling of XRAM and CAN controller could be dangerous since indeterminate values could be read from the external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor is loaded. So the reset state is a disabled XRAM and CAN controller. Because of the load time of the capacitor, XMAP0 bit once written to '0' (that is, discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable status is XRAM and CAN controller enabled. The clear instruction for the XMAP0 bit should be integrated in the program initialization routine before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant clear instructions. Semiconductor Group 3-4 1997-11-01 Memory Organization C515C 3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM and CAN controller can be accessed by two read/write instructions, which use the 16bit DPTR for indirect addressing. These instructions are : – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of F800H to FFFFH. For accessing the CAN controller, the effective address stored in DPTR must be in the range of F700H to F7FFH. 3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX MOVX A, @ Ri @Ri, A (Read) (Write) As in the SAB 80C515A a special page register is implemented into the C515C to provide the possibility of accessing the XRAM or CAN controller also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM and CAN controller as Port 2 for external data memory. Special Function Register XPAGE (Address 91H) Bit No. MSB 7 91H .7 Reset Value : 00H LSB 0 .0 XPAGE 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 Bit XPAGE.7-0 Function XRAM/CAN controller high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM or CAN controller. Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differences in accessing XRAM/CAN controller, ext. RAM or what is to do when Port 2 is used as an I/O-port. Semiconductor Group 3-5 1997-11-01 Memory Organization C515C Port 0 Address/Data XPAGE Write to Port 2 Port 2 XRAM CAN-Controller Page Address MCS02761 Figure 3-2 Write Page Address to Port 2 “MOV P2,pageaddress“ will write the page address to Port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM/CAN controller address range (F700H FFFFH), the XRAM/CAN controller has to be disabled. When additional external RAM is to be addressed in an address range < F700H, the XRAM/CAN controller may remain enabled and there is no need to overwrite XPAGE by a second move. Semiconductor Group 3-6 1997-11-01 Memory Organization C515C Port 0 Address/Data XPAGE Write to XPAGE Port 2 XRAM CAN-Controller Address/ I/O Data MCS02762 Figure 3-3 Write Page Address to XPAGE The page address is only written to the XPAGE register. Port 2 is available for addresses or I/O data. Semiconductor Group 3-7 1997-11-01 Memory Organization C515C Port 0 Address/Data XPAGE Write I/O Data to Port 2 Port 2 XRAM CAN-Controller I/O Data MCS02763 Figure 3-4 Use of Port 2 as I/O Port At a write to port 2, the XRAM/CAN controller address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register. So, whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address. Example : I/O data at port 2 shall be AAH. A byte shall be fetched from XRAM at address F830H. MOV MOV MOV MOVX R0, #30H P2, #0AAH XPAGE, #0F8H A, @R0 ; ; P2 shows AAH and XPAGE contains AAH ; P2 still shows AAH but XRAM is addressed ; the contents of XRAM at F830H is moved to accumulator Semiconductor Group 3-8 1997-11-01 Memory Organization C515C The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM/CAN Controller address range, an external access is performed. For the C515C the content of XPAGE must be greater or equal F7H in order to use the XRAM/CAN Controller. The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used : a) Access to XRAM/CAN Contr. : The upper address byte must be written to XPAGE or P2; both writes select the XRAM/CAN controller address range. b) Access to external memory : The upper address byte must be written to P2; XPAGE will be loaded with the same address in order to deselect the XRAM. 3.4.4 Reset Operation of the XRAM The contents of the XRAM is not affected by a reset. After power-up the contents are undefined, while they remain unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value. 3.4.5 Behaviour of Port0 and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA. The table 3-1 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus: The pins work as external address/data bus. If (internal) XRAM is accessed, the data written to the XRAM can be seen on the bus in debug mode. I/0: The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal or external XDATA memory. The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM behaves. Semiconductor Group 3-9 1997-11-01 Semiconductor Group 3-10 1997-11-01 EA = 0 XMAP1, XMAP0 00 MOVX @DPTR DPTR < XRAM address range DPTR ≥ XRAM address range MOVX @ Ri XPAGE < XRAM addr.page range XPAGE ≥ XRAM addr.page range a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus (RD/WR-Data) b)RD/WR inactive c)XRAM is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus (RD/WR-Data) P2→I/O b)RD/WR inactive c)XRAM is used 10 a)P0/P2→Bus b)RD/WR active c)ext.memory is used X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used 00 a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→I/0 10 EA = 1 XMAP1, XMAP0 X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus (RD/WR-Data) b)RD/WR active b)RD/WR active c)XRAM is used c) ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus (RD/WR-Data) b)RD/WR b)RD/WR active b)RD/WR active inactive c)XRAM is used c) ext.memory c)XRAM is used is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P2→I/O P0/P2→I/O a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus a)P0→Bus (RD/WR-Data P2→I/O only) P2→I/O b)RD/WR active b)RD/WR active c)ext.memory c)XRAM is used is used b)RD/WR inactive c)XRAM is used c)XRAM is used c)ext.memory is used a)P0→Bus a)P0→Bus (RD/WR-Data) P2→I/O P2→I/O b)RD/WR active b)RD/WR active Memory Organization C515C modes compatible to 8051/C501 family Table 3-1 Behaviour of P0/P2 and RD/WR During MOVX Accesses Memory Organization C515C 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. Two special function registers of the C515C (PCON1 and DIR5) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH. Details about the access of these registers is described in section 3.4.1 of this chapter. Special Function Register SYSCON (Address B1H) Reset Value C515C-8R : X010XX01B Reset Value C515C-8E : X010X001B LSB 0 SYSCON Bit No. MSB 7 B1H – 6 5 4 RMAP 3 – 2 1 PMOD EALE CSWO XMAP1 XMAP0 The functions of the shaded bits are not described in this section. Bit – RMAP Function Reserved bits for future use. Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C515C are listed in table 3-2 and table 3-3. In table 3-2 they are organized in groups which refer to the functional blocks of the C515C. The CAN-SFRs are also included in table 3-2. Table 3-3 illustrates the contents of the SFRs in numeric order of their addresses. Table 3-4 list the CAN-SFRs in numeric order of their addresses. . Semiconductor Group 3-11 1997-11-01 Memory Organization C515C Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP SYSCON 2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Address Contents after Reset E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H C515C-8R B1H C515C-8E B1H D8H 1) DCH D9H DAH 4) A8H1) B8H 1) 9AH A9H B9H 88H 1) C8H 1) 98H 1) C0H 1) 00H 00H 00H 00H XXXXX000B 3) 00H 07H X010XX01B 3) X010X001B 3) 00H 0XXXX000B 3) 00H 00XXXXXXB 3) 00H 00H XX00X00XB 3) 00H 0X000000B 3) 00H 00H 00H 00H 00H X010XX01B 3) X010X001B 3) FFH FFH FFH FFH FFH FFH FFH – XXXXXXX1B 3) X010XX01B 3) X010X001B 3) A/DADCON0 2) Converter ADCON1 ADDATH ADDATL Interrupt System IEN0 2) IEN1 2) IEN2 IP0 2) IP1 TCON 2) T2CON 2) SCON 2) IRCON XPAGE SYSCON 2) Ports P0 P1 P2 P3 P4 P5 DIR5 P6 P7 SYSCON 2) A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register XRAM Page Address Register for Extended on-chip 91H XRAM and CAN Controller System Control Register C515C-8R B1H C515C-8E B1H Port 0 80H 1) 90H 1) Port 1 A0H 1) Port 2 B0H 1 Port 3 E8H 1) Port 4 F8H 1) Port 5 F8H 1) 4) Port 5 Direction Register DBH Port 6, Analog/Digital Input FAH Port 7 System Control Register C515C-8R B1H C515C-8E B1H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. Semiconductor Group 3-12 1997-11-01 Memory Organization C515C Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Serial Channel Symbol ADCON0 2) PCON 2) SBUF SCON SRELL SRELH Name A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers : Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 Address Contents after Reset D8H 1 87H 99H 98H 1) AAH BAH F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H 5) F7n1H 5) F7n2H 5) F7n3H 5) F7n4H 5) F7n5H 5) F7n6H 5) F7n7H 5) F7n8H 5) F7n9H 5) F7nAH 5) F7nBH 5) F7nCH 5) F7nDH 5) F7nEH 5) 00H 00H XXH 3) 00H D9H XXXXXX11B 3) 01H XXH 3) XXH 3) UUH 3) CAN CR Controller SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0UUUUUUUB 3) UUH 3) UUU11111B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUUUUU00B3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation “n“ in the message object address definition defines the number of the related message object. Semiconductor Group 3-13 1997-11-01 Memory Organization C515C Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block SSC Interface Symbol SSCCON STB SRB SCF SCIEN SSCMOD TCON TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON Name SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Address Contents after Reset 93H 1) 94H 95H ABH 1) ACH 96H 88H 1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 1) 86H A8H1) B8H 1) A9H 4) 4) 07H XXH 3) XXH 3) XXXXXX00B 3) XXXXXX00B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXXXXXXB 3) 0XX0XXXXB 3) Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 Watchdog WDTREL IEN0 2) IEN1 2) IP0 2) Power Save Modes PCON 2) PCON1 87H C515C-8R 88H C515C-8E 88H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-14 1997-11-01 Memory Organization C515C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H 82H 83H 86H 87H 88H 3) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 – – M1 .5 .5 .5 .5 T2EX .5 – MSTR .5 .5 0 SM2 .5 .4 .4 .4 .4 .4 SD TR0 – WS M0 .4 .4 .4 .4 INT2 .4 – CPOL .4 .4 0 REN .4 .3 .3 .3 .3 .3 GF1 IE1 – – GATE .3 .3 .3 .3 INT6 .3 – CPHA .3 .3 0 TB8 .3 .2 .2 .2 .2 .2 GF0 IT1 – – C/T .2 .2 .2 .2 INT5 .2 .2 BRS2 .2 .2 0 RB8 .2 .1 .1 .1 .1 .1 PDE IE0 – – M1 .1 .1 .1 .1 INT4 .1 .1 BRS1 .1 .1 0 TI .1 .0 .0 .0 .0 .0 IDLE IT0 – – M0 .0 .0 .0 .0 INT3 .0 .0 BRS0 .0 .0 LSBSM RI .0 SP DPL DPH WDTREL 00H PCON PCON1 4) 00H 00H 0XXXXXXXB SMOD PDS TR1 EWPD – EWPD – GATE .7 .7 .7 .7 T2 .7 – SCEN .7 .7 SM0 .7 C/T .6 .6 .6 .6 CLKOUT .6 – TEN .6 .6 SM1 .6 88H 2) TCON 88H 3) PCON1 5) 0XX0XXXXB 89H 8AH 8BH TMOD TL0 TL1 00H 00H 00H 00H 00H FFH 00H XXXXX000B XXH XXH 00H XXH 8CH TH0 8DH TH1 90H 2) P1 91H 92H 93H 94H 95H 96H 99H XPAGE DPSEL SSCCON 07H STB SRB SSCMOD 00H LOOPB TRIO 98H 2) SCON SBUF 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is available in the C515C-8R and C515C-L. 5) This SFR is available in the C515C-8E. Semiconductor Group 3-15 1997-11-01 Memory Organization C515C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) 9AH IEN2 X00XX00XB FFH 00H 00H D9H XXXXXX00B XXXXXX00B – .7 EAL .7 – – RD – – Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – .6 WDT .6 – – WR EX8 .5 ET2 .5 – – T1 EX7 .4 ES .4 .4 – – T0 RMAP RMAP EX5 .4 – IEX5 – .3 ET1 .3 .3 – – INT1 – – EX4 .3 – IEX4 ESSC .2 EX1 .2 .2 – – INT0 – ECAN .1 ET0 .1 .1 – .0 EX0 .0 .0 A0H2) P2 A8H2) IEN0 A9H IP0 AAH SRELL ABH SCF ACH SCIEN B0H2) P3 B1H B1H OWDS WDTS .5 WCOL TC WCEN TCEN TxD RxD FFH SYSCON X0103) XX01B PMOD EALE PMOD EALE XMAP1 XMAP0 SYSCON X0104) X001B 00H 0X000000B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H IP1 CSWO XMAP1 XMAP0 EX3 .2 – IEX3 EX2 .1 .1 IEX2 EADC .0 .0 IADC COCAL 0 .0 .0 .0 .0 .0 .0 T2I0 B8H2) IEN1 B9H EXEN2 SWDT EX6 PDIR – EXF2 COCA H3 .7 .7 .7 .7 .7 .7 T2PS – – TF2 .5 – IEX6 BAH SRELH C0H2) IRCON C1H CCEN C2H CCL1 C3H CCH1 C4H CCL2 C5H CCH2 C6H CCL3 C7H CCH3 C8H2) T2CON COCAL COCA 3 H2 .6 .6 .6 .6 .6 .6 I3FR .5 .5 .5 .5 .5 .5 I2FR COCAL COCA 2 H1 .4 .4 .4 .4 .4 .4 T2R1 .3 .3 .3 .3 .3 .3 T2R0 COCAL COCA 1 H0 .2 .2 .2 .2 .2 .2 T2CM .1 .1 .1 .1 .1 .1 T2I1 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) This SFR is available in the C515C-8R and C515C-L. 4) This SFR is available in the C515C-8E. Semiconductor Group 3-16 1997-11-01 Memory Organization C515C Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) CAH CRCL CBH CRCH CCH TL2 CDH TH2 D0H2) PSW 2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00H 00H 00H 00H 00H .7 .7 .7 .7 CY BD .9 .1 .7 ADCL .7 RXDC .7 .7 .7 – 1 1 .7 .6 .6 .6 .6 AC CLK .8 .0 .6 – .6 TXDC .6 .6 .6 – 1 0 .6 .5 .5 .5 .5 F0 ADEX .7 – .5 – .5 INT8 .5 .5 .5 – 0 0 .5 .4 .4 .4 .4 RS1 BSY .6 – .4 – .4 SLS .4 .4 .4 – 0 1 .4 .3 .3 .3 .3 RS0 ADM .5 – .3 0 .3 STO .3 .3 .3 – 0 0 .3 .2 .2 .2 .2 OV MX2 .4 – .2 MX2 .2 SRI .2 .2 .2 – 1 1 .2 .1 .1 .1 .1 F1 MX1 .3 – .1 MX1 .1 SCLK .1 .1 .1 – 0 0 .1 .0 .0 .0 .0 P MX0 .2 – .0 MX0 .0 ADST .0 .0 .0 INT7 1 1 .0 D8H ADCON0 00H D9H ADDATH 00H DAH ADDATL 00XXXXXXB DBH P6 – DCH ADCON1 0XXXX000B E0H2) ACC E8H2) P4 F0H2) B F8H2) P5 F8H2) DIR5 3) FAH P7 4) 5) 4) 5) 4) 5) 00H FFH 00H FFH FFH XXXXXXX1B C5H 95H 6) FCH VR0 FDH VR1 FEH VR2 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) These SFRs are read-only registers (C515C-8E only). 6) The content of this SFR varies with the actual step of the C515C-8E (see also chapter 10-7). Semiconductor Group 3-17 1997-11-01 Memory Organization C515C Table 3-4 Contents of the CAN Registers in numeric order of their addresses Addr. Register Content Bit 7 n=1-FH1) after Reset 2) F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG 01H XXH XXH UUH 0UUU. 0 UUUUB UUH UUU1. 1111B UUH UUH UUH UUUU. U000B UUH UUH UUH UUUU. U000B UUH UUH UUH UUH UUH UUUU. U000B UUUU. UU00B ID4-0 DLC DIR ID20-18 ID12-5 0 XTD 0 0 0 0 MSGVAL RMTPND ID4-0 TXIE TXRQ ID20-18 ID12-5 0 RXIE MSGLST CPUUPD ID28-21 ID17-13 0 0 INTPND NEWDAT ID4-0 ID28-21 ID17-13 ID20-18 1 TEST BOFF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCE 0 0 EIE INTID SIE LEC2 IE LEC1 INIT LEC0 EWRN – RXOK TXOK SJW TSEG2 ID28-21 1 ID28-21 ID20-13 ID12-5 BRP TSEG1 1 1 1 0 0 0 1) The notation “n“ in the address definition defines the number of the related message object. 2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation Semiconductor Group 3-18 1997-11-01 Memory Organization C515C Table 3-4 Contents of the CAN Registers in numeric order of their addresses (cont’d) Addr. Register Content Bit 7 n=1-FH1) after Reset 2) F7n7H F7n8H F7n9H F7nAH F7nBH F7nCH F7nDH F7nEH DB0n DB1n DB2n DB3n DB4n DB5n DB6n DB7n XXH XXH XXH XXH XXH XXH XXH XXH .7 .7 .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 .0 .0 .0 1) The notation “n“ in the address definition defines the number of the related message object. 2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation Semiconductor Group 3-19 1997-11-01 External Bus Interface C515C 4 External Bus Interface The C515C allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C515C is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emisions of the system. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 1997-11-01 External Bus Interface C515C a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST IN PCL OUT PCL OUT valid b) S1 ALE PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST IN RD P2 P0 MCD02575 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 1997-11-01 External Bus Interface C515C 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed whenever signal EA is active (low): Due to the 64K internal ROM, no mixed internal/external program memory execution is possible. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C515C the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-3 1997-11-01 External Bus Interface C515C 4.4 ALE, Address Latch Enable The C515C allows to switch off the ALE output signal. If the internal ROM is used (EA=1) and ALE is switched off by EALE=0, Then, ALE will only go active during external data memory accesses (MOVX instructions). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Reset Value C515C-8R : X010XX01B Reset Value C515C-8E : X010X001B LSB 0 SYSCON Bit No. MSB 7 B1H – 6 5 4 RMAP 3 – 2 1 PMOD EALE CSWO XMAP1 XMAP0 The function of the shaded bit is not described in this section. Bit – EALE Function Reserved bits for future use. Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. Semiconductor Group 4-4 1997-11-01 External Bus Interface C515C 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS03280 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. Semiconductor Group 4-5 1997-11-01 External Bus Interface C515C 4.6 Eight Datapointers for Faster External Bus Access 4.6.1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be handled bytewise. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. 4.6.2 How the eight Datapointers of the C515C are realized Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C515C contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C515C which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 4-3 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx. Special Function Register DPSEL (Address 92H) Bit No. MSB 7 92H – Reset Value : XXXXX000B LSB 0 .0 DPSEL 6 – 5 – 4 – 3 – 2 .2 1 .1 Bit DPSEL.2-0 Function Data pointer select bits DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7. Semiconductor Group 4-6 1997-11-01 External Bus Interface C515C ----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 .2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory MCD00779 DPTR0 DPH(83 H ) DPL(82 H) Figure 4-3 Accessing of External Data Memory via Multiple Datapointers 4.6.3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM. 4.6.4 Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H Semiconductor Group 4-7 1997-11-01 External Bus Interface C515C Example 1 : Using only One Datapointer (Code for an C501) Initialization Routine MOV MOV MOV MOV LOW(SRC_PTR), #0FFH HIGH(SRC_PTR), #1FH LOW(DES_PTR), #0A0H HIGH(DES_PTR), #2FH ;Initialize shadow_variables with source_pointer ;Initialize shadow_variables with destination_pointer Table Look-up Routine under Real Time Conditions PUSH PUSH MOV MOV ;INC ;CJNE MOVC MOV MOV MOV MOV INC MOVX MOV MOV POP POP ; DPL DPH DPL, LOW(SRC_PTR) DPH, HIGH(SRC_PTR) DPTR … A,@DPTR LOW(SRC_PTR), DPL HIGH(SRC_PTR), DPH DPL, LOW(DES_PTR) DPH, HIGH(DES_PTR) DPTR @DPTR, A LOW(DES_PTR), DPL HIGH(DES_PTR),DPH DPH DPL ; Number of cycles ;Save old datapointer 2 ; 2 ;Load Source Pointer 2 ; 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and 2 ;load destination_pointer 2 ; 2 ; 2 ;Increment destination_pointer ;(ex. time not relevant) – ;Transfer byte to destination address 2 ;Save destination_pointer 2 ; 2 ;Restore old datapointer 2 ; 2 Total execution time (machine cycles) : 28 Semiconductor Group 4-8 1997-11-01 External Bus Interface C515C Example 2 : Using Two Datapointers (Code for an C515C) Initialization Routine MOV MOV MOV MOV DPSEL, #06H DPTR, #1FFFH DPSEL, #07H DPTR, #2FA0H ;Initialize DPTR6 with source pointer ;Initialize DPTR7 with destination pointer Table Look-up Routine under Real Time Conditions PUSH MOV ;INC ;CJNE MOVC MOV MOVX POP DPSEL DPSEL, #06H DPTR … A,@DPTR DPSEL, #07H @DPTR, A DPSEL ; Number of cycles ;Save old source pointer 2 ;Load source pointer 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and ;load destination_pointer 2 ;Transfer byte to destination address 2 ;Save destination pointer and ;restore old datapointer 2 Total execution time (machine cycles) : 12 ; The above example shows that utilization of the C515C’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an C515C program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use. Semiconductor Group 4-9 1997-11-01 External Bus Interface C515C 4.7 ROM/OTP Protection for the C515C-8R / C515C-8E The C515C-8R ROM version allows to protect the contents of the internal ROM against read out by non authorized people. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C515C-8R ROM version has to define whether ROM protection has to be selected or not. The C515C-8E OTP version allows also program memory protection in several levels (see chapter 10.6). The program memory protection for the C515C-8E can be activated after programming of the device. The C515C-8R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected and also protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C515C-8R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM and OTP (in protection level 1) protected devices, operates different : ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort. 4.7.1 Unprotected ROM Mode If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-4 is used to read out the contents of the ROM. The AC timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 11). P1.0 - P1.7 P2.0 - P2.7 Address 1 Address 2 Port 0 Inputs: PSEN = VSS ALE, EA = VIH / VIH2 RESET = VIL2 Data 1 Out Data 2 Out MCT02718 Figure 4-4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. Then the 16-bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines. After a delay time, port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C515C-8R must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. Semiconductor Group 4-10 1997-11-01 External Bus Interface C515C 4.7.2 Protected ROM/OTP Mode If the C515C-8R ROM is protected by mask (or C515C-8E in protection level 1), the ROM/OTP verification mode 2 as shown in figure 4-5 is used to verify the content of the ROM/OTP. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 11). ~ ~ RESET 1. ALE Pulse after Reset ~ ~ 6 CLP 3 CLP ALE Latch ~ ~ Latch Data for Addr. 0 Latch ~ ~ ~ ~ ~ ~ Latch Data for Addr. X . 16 -1 Data for Addr. X . 16 Latch Data for Addr. X . 16 Port 0 ~ ~ ~ ~ Data for Addr. 1 ~ ~ ~ ~ P3.5 Inputs: ALE = VSS PSEN, EA = VIH RESET = Low: Verify Error High: Verify OK MCT03648 Figure 4-5 ROM/OTP Verification Mode 2 ROM/OTP verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM/OTP verification mode 2 sequence is started. The C515C outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way : 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal ROM/OTP address 0000H content of internal ROM/OTP address 0001H content of internal ROM/OTP address 0002H content of internal ROM/OTP address 000FH The C515C does not output any address information during the ROM/OTP verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the rising edge of RESET. With each following ALE pulse the ROM/OTP address pointer is internally incremented and the expected data byte for the next ROM/OTP address must be delivered externally. Semiconductor Group 4-11 1997-11-01 External Bus Interface C515C Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the ROM/OTP content of the actual address. If an verify error is detected, the error condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. If P3.5 has been set low (verify error detected), it will stay at low level even if the following ROM verification sequence does not detect further verify errors. In ROM/OTP verification mode 2, the C515C must be provided with a system clock at the XTAL pins. Figure 4-6 shows an application example of a external circuitry which allows to verify a protected ROM/OTP inside the C515C in ROM/OTP verification mode 2. With RESET going inactive, the C515C starts the ROM/OTP verify sequence. Its ALE is clocking an 16-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the contents of the internal (protected) ROM/OTP. The verify detect logic typically displays the pass/fail information of the verify operation. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal ROM/OTP has been handled, the C515C starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM/OTP verification. P3.5 Verify Detect Logic Carry CLK 16 Bit Address Counter R ALE 2 kΩ C515C-8R C515C-8E A0 - A15 & RESET Compare Code ROM VCC & Port 0 EA D0 - D7 VCC PSEN CS OE MCS02720 Figure 4-6 ROM Verification Mode 2 - External Circuitry Example Semiconductor Group 4-12 1997-11-01 Reset / System Clock C515C 5 5.1 Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C515C allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. Additionally to the hardware reset, which is applied externally to the C515C, there are two internal reset sources, the watchdog timer and the oscillator watchdog. The chapter at hand only deals with the external hardware reset. The reset input is an active low input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycle (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes high again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor (figure 5-1 a) and c)). After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. Semiconductor Group 5-1 1997-11-01 Reset / System Clock C515C The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. a) b) & + RESET RESET C515C c) C515C + RESET C515C MCS02721 Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches are set to FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 to 5 and 7) output a one (1). Port 6 is an input-only port. It has no internal latch and therefore the contents of the special function registers P6 depend on the levels applied to port 6. The content of the internal RAM and XRAM of the C515C is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-2 1997-11-01 Reset / System Clock C515C 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level) the internal reset procedure is started. It needs two machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins. The RESET signal must be active for at least one machine cycle. After this time the C515C remains in its reset state as long as the signal is active. When the reset signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-2 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT INST IN PCL OUT PCH OUT P2 ALE MCT01821 Figure 5-2 CPU Timing after Reset Semiconductor Group 5-3 1997-11-01 Reset / System Clock C515C 5.3 Fast Internal Reset after Power-On The C515C uses the oscillator watchdog unit (see also chapter 8) for a fast internal reset procedure after power-on. Figure 5-3 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (max. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C515C the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-3). Under worst case conditions (fast VCC rise time - e.g. 1 µs, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VCC below 4.25 V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-3, II). Subsequently, the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-3, III). However, an externally applied reset still remains active (figure 5-3, IV) and the device does not start program execution (figure 5-3, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – – – Termination of Hardware Power-Down Mode (a HWPD signal is overriden by reset) Termination of the Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal for clock generation, the external reset signal must be hold active at least until the on-chip oscillator has started (max.10 ms) and the internal watchdog reset phase is completed (after phase III in figure 5-3). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficient in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin. Semiconductor Group 5-4 1997-11-01 Semiconductor Group Reset II III IV V Clock from RC-Oscillator, Reset at Ports On-chip oscillator starts; final reset sequence by oscillator WD; max. 768 Cycles Port remains in reset because of ext. reset signal Start of program execution MCD02722 Ports Undef. Figure 5-3 Power-On Reset of the C515C On-Chip Oscillator RC Oscillator 5-5 VCC RESET Phase I Power On; undef. Port typ. 18 µs max. 34 µs Reset / System Clock C515C 1997-11-01 Reset / System Clock C515C 5.4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-4 shows the recommended oscillator circuit. C XTAL2 2-10 MHz C515C XTAL1 C C = 20 pF ± 10 pF for Crystal Operation MCS02723 Figure 5-4 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. lt a ceramic resonator is used, C1 and C2 are normally selected to be of somewhat higher values, typically 47 pF. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Semiconductor Group 5-6 1997-11-01 Reset / System Clock C515C To Internal Timing Circuitry C515C XTAL1 1) XTAL2 C1 C2 1) Crystal or Ceramic Resonator MCS02724 Figure 5-5 On-Chip Oscillator Circuitry To drive the C515C with an external clock source, the external clock signal has to be applied to XTAL2, as shown in figure 5-6. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2. VCC N.C. External Clock Signal C515C XTAL1 XTAL2 MCS02725 Figure 5-6 External Clock Source Semiconductor Group 5-7 1997-11-01 Reset / System Clock C515C 5.5 System Clock Output For peripheral devices requiring a system clock, the C515C provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON0), a clock signal with 1/6 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset. Special Function Register ADCON0 (Address D8H) MSB DFH BD Reset Value : 00H LSB D8H MX0 ADCON0 Bit No. D8H DEH CLK DDH ADEX DCH BSY DBH ADM DAH MX2 D9H MX1 The shaded bits are not used in controlling the clock output function. Bit CLK Function Clockout enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/6 of the oscillator frequency. The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 5-7. Note : During slow-down operation the frequency of the CLKOUT signal is divided by 32. Semiconductor Group 5-8 1997-11-01 Reset / System Clock C515C S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-7 Timing Diagram - System Clock Output Semiconductor Group 5-9 1997-11-01 On-Chip Peripheral Components C515C 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C515C except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O 6.1.1 Port Structures Digital I/O Ports The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P7 are performed via their corresponding special function registers P0 to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasibidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional port structure. This port operating mode can be selected by software (setting or clearing the bit PMOD in the SFR SYSCON). The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 6 is available as input port only and provides two functions. When used as digital inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have no effect. lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte instructions. Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked. In order to guarantee a high-quality A/D conversion, digital input lines of port 6 should not toggle while a neighbouring port pin is executing an A/D conversion. This could produce crosstalk to the analog signal. Semiconductor Group 6-1 1997-11-01 On-Chip Peripheral Components C515C Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 7 digital I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin self is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port activate the "read-port-latch" signal, while others activate the "read-port-pin" signal. Quasi Bidirectional : TTL Level Bidirectional : CMOS Level Read Port Latch Internal Bus Write to Latch & D Port Latch CLK Q Q Port Driver Circuitry Port Pin Read Port Pin Read Direction Latch D & D Write to IP1 R PDIR Q Q Direction Latch CLK Q PMOD Q Q = 0 : Output Q = 1 : Input Bidirectional Port Control Logic Delay = 2.5 Machine Cycles MCS02648 Figure 6-1 Basic Structure of a Port Circuitry The shaded area in figure 6-1 shows the control logic of the C515C port 5 circuitry, which has been added to the functionality of the standard 8051 digital I/O port structure. This control logic is used to provide the additional bidirectional port 5 structure with CMOS voltage levels. Semiconductor Group 6-2 1997-11-01 On-Chip Peripheral Components C515C 6.1.1.1 Port Structure Selection After a reset operation, the quasi-bidirectional 8051-compatible port structure is selected for all digital I/O ports of the C515C. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode, the direction register DIR5 of port 5 must be written . This direction register is mapped to the port 5 register. This means, the port register address is equal to its direction register address. Figure 6-2 illustrates the port- and direction register configuration of port 5. Write to Port Enable Internal Bus Int. Bus, Bit 7 Write to IP 1 D PDIR R Q Port Register Q Delay: 2.5 Machine Cycles Enable Direction Register Read Port Instruction sequence for the programming of the direction registers: ORL IP1, #80H ; Set bit PDIR MOV DIRx, #OYYH ; Write port x direction register with value YYH MCS02649 Figure 6-2 Port 5 Register, Direction Register For the access the direction register a double instruction sequence must be executed. The first instruction has to set bit PDIR in SFR IP1. Thereafter, a second instruction can read or write the direction registers. PDIR will automatically be cleared after the second machine cycle (S2P2) after having been set. For this time, the access to the direction register is enabled and the register can be read or written. Further, the double instruction sequence as shown in figure 6-2, cannot be interrupted by an interrupt, When the bidirectional port structure is activated (PMOD=1) after a reset, the ports are defined as inputs (direction registers default values after reset are set to FFH). With PMOD = 0 (quasi-bidirectional port structure selected), any access to the direction registers has no effect on the port driver circuitries. Semiconductor Group 6-3 1997-11-01 On-Chip Peripheral Components C515C Special Function Register SYSCON (Address B1H) Special Function Register IP1 (Address B9H) MSB 7 – 7 PDIR Reset Value C515C-8R : X010XX01B Reset Value C515C-8E : X010X001B Reset Value : 0X000000B LSB 0 SYSCON Bit No. B1H Bit No. B9H 6 5 4 RMAP 4 .4 3 – 3 .3 2 1 PMOD EALE 6 – 5 .5 CSWO XMAP1 XMAP0 2 .2 1 .1 0 .0 IP1 The shaded bits are not used for port selection. Bit PMOD Function Port 5 mode selection PMOD = 0 : Quasi-bidirectional port structure of port 5 is selected (reset value) PMOD = 1 : Bidirectional port structure of port 5 is selected. Direction register enable PDIR = 0 : Port 5 register access is enabled (reset value) PDIR = 1 : Direction register is enabled. PDIR will automatically be cleared after the second machine cycle (S2P2) after having been set. PDIR Direction Register DIR5 (Address F8H) Bit No. F8H MSB 7 .7 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 Reset Value : FFH LSB 0 .0 DIR5 Bit DIR5.7-0 Function Port driver circuitry, input/output selection Bit = 0 : Port line is in output mode Bit = 1 : Port line is in input mode (reset value). This register can only be read and written by software when bit PDIR (IP1) was set one instruction before. Semiconductor Group 6-4 1997-11-01 On-Chip Peripheral Components C515C 6.1.1.2 Quasi-Bidirectional Port Structure 6.1.1.2.1 Basic Port Circuirty of Port 1 to 5 and 7 The basic quasi-bidirectional port structure as shown in the upper part of the schematics of figure 6-3 provides a port driver circuit which is build up by an internal pullup FET as shown in figure 6-3. Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-3, Q=0), which turns off the output driver FET n1. Then, for ports 1 to 5 and 7, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional". Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-3 Basic Output Driver Circuit of Ports 1 to 5 and 7 Semiconductor Group 6-5 1997-11-01 On-Chip Peripheral Components C515C In fact, the pullups mentioned before and included in figure 6-3 are pullup arrangements as shown in figure 6-4. One n-channel pulldown FET and three pullup FETs are used: Delay = 1 State VCC =1 _