C517A

SAB-C501 C517A 8-Bit CMOS Microcontroller User’s Manual 01.99 d s. e n r/ m ie ct o . s du w w on wc :// mi ttp Se h C517A User’s Manual Revision History : Previous Releases : Page (previous version) All sections 1-2 1-2 1-4 1-5 1-5 to 1-10 1-8 6-24 9-1 9-2 9-3 9-5 9-7 9-7 9-9 Chapter 10 Page (new version) All sections 1-2 1-2 1-4 1-5 1-6 to 1-13 1-9 6-24 9-1 9-1 9-1 9-3 9-5 9-5 9-7 - 01.99 08.97 (Original Version) Subjects (changes since last revision) 9CC is changed to 9DD. "with wake-up capability through INT0 pin" is removed. P-LCC-84 package is added under the main feature list. P-LCC-84 package is added. Figure 1-4; added. Table 1-1; modified, column “P-LCC-84” is added. Description for pin EA is added with "For C517A-4R ...” Table 6-3; modified, column “Pin No. (P-LCC-84)” is added. The whole page is added to contain brief explanation of the power saving modes. Section 9.1 and 9.2 are added to give more explanation of pin PE/SWD usage. Last paragrapah; the sentence “Changing the logic level ...” in the note under the description of PCON is deleted. 1st paragraph; the sentence “If the idle mode ...” is added. 3rd paragraph; the paragraph is changed to contain an extra way to leave software power down mode. 4th paragraph; the sentece “If the software power down ...” is added. Paragraph "A low signal at the P3.2/INT0 ...." is removed. The whole chapter is moved to the C517A Data Sheet. Edition 01.99 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 01.99. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. General Information C517A Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.6 4.6.1 4.6.2 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.1.1 6.1.2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 XRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 XRAM Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . 3-5 Accesses to XRAM using the Registers R0/R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PSEN, Program Store Enable Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . . 4-3 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . . . . 4-5 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 How the eight Datapointers of the C517A are realized . . . . . . . . . . . . . . . . . . . . . . 4-5 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 ROM Protection for the C517A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Unprotected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Protected ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 Semiconductor Group I-1 General Information C517A Contents 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.1.2.1 6.3.1.2.2 6.3.1.2.3 6.3.2 6.3.2.1 6.3.2.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.4 6.3.4.1 6.3.4.2 6.3.4.3 6.3.4.4 6.3.4.4.1 6.3.4.4.2 6.3.4.5 6.3.5 6.3.6 6.3.6.1 6.3.6.2 6.3.6.3 6.4 6.4.1 6.4.2 6.4.3 Page Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Port 1, Port 3 to Port 6 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Read-Modify-Write Feature of Ports 0 to 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 The Compare/Capture Unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Timer 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 Timer 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-30 Gated Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Reload of Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-31 Operation of the Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Compare Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Operating Modes of the Compare Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 Compare Functions of the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-40 Timer- and Compare-Register Configurations of the CCU . . . . . . . . . . . . . . . . . . . 6-41 Timer 2 - Compare Function with Registers CRC, CC1 to CC4 . . . . . . . . . . . . 6-42 Timer 2 - Capture Function with Registers CRC, CC1 to CC4 . . . . . . . . . . . . . . . 6-45 Compare Function of Register CC4; "Concurrent Compare" . . . . . . . . . . . . . . . . 6-47 Compare Function of Registers CM0 to CM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 CMx Registers Assigned to the Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .6-52 CMx Registers Assigned to the Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55 Timer 2 Operating in Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-56 Modulation Range in Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . . . .6-59 Advantages in Using Compare Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59 Interrupt Enable Bits of the Compare/Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . .6-60 Interrupt Flags of the Compare/Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61 Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 MDU Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 Operation of the MDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64 Multiplication/Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-65 Semiconductor Group I-2 General Information C517A Contents 6.4.4 6.4.5 6.4.6 6.5 6.5.1 6.5.1.1 6.5.1.2 6.5.1.3 6.5.1.4 6.5.1.4.1 6.5.1.4.2 6.5.1.4.3 6.5.2 6.5.2.1 6.5.2.2 6.5.2.3 6.5.3 6.5.3.1 6.5.3.2 6.5.3.3 6.5.3.4 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.4 8.1.5 Page Normalize and Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-67 The Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-68 The Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-68 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-70 Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-70 Operating Modes of Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-70 Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-71 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-71 Baud Rates of Serial Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-73 Baud Rate in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75 Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 Operating Modes of Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-81 Baud Rates of Serial Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-81 Detailed Description of the Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83 Mode 0, Synchronous Mode (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83 Mode 1/Mode B, 8-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . . . . . . . .6-86 Mode 2, 9-Bit UART (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-89 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . . . . . . . .6-89 10-bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-93 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-93 A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-95 A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-99 A/D Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-100 A/D Converter Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-104 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 The First Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 The Second Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . .8-4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 I-3 Semiconductor Group General Information C517A Contents 8.2 8.2.1 8.2.2 9 9.1 9.2 9.3 9.4 9.5 9.6 9.6.1 9.6.2 9.7 9.8 9.9 10 Page Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 Description of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Hardware Enable for the Use of the Power Saving Modes . . . . . . . . . . . . . . . . . . . . .9-2 Application Example for Switching Pin PE/SWD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2 Power Saving Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Slow Down Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Invoking Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Exit from Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . . . . . . . .9-8 Hardware Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 Hardware Power Down Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Semiconductor Group I-4 Introduction C517A 1 Introduction The C517A is a high-end member of the Siemens C500 family of 8-bit microcontrollers. lt is functionally fully compatible with the SAB-80C517A/83C537A-5 microcontrollers. The C517A basically operates with internal and/or external program memory. The C517A-L is identical to the C517A-4R, except that it lacks the on-chip program memory. Therefore, in this documentation the term C517A refers to all versions within this specification unless otherwise noted. Figure 1-1 shows the different functional units of the C517A and figure 1-2 shows the simplified logic symbol of the C517A. On-Chip Emulation Support Module Oscillator Watchdog Watchdog Timer T0 T2 T1 10-Bit A/D Converter XRAM 2K x 8 RAM 256 x 8 Port 0 Port 1 I/O I/O I/O I/O I/O Power Saving Modes CCU Compare Timer CPU (8 Datapointer) MDU Port 2 ROM 32k x 8 Port 8 Port 7 Port 6 Port 5 Port 3 Port 4 8 Bit USART 8 Bit UART Analog/ Analog/ Digital Digital Input Input I/O I/O MCA03317 Figure 1-1 C517A Functional Units Semiconductor Group 1-1 Introduction C517A Listed below is a summary of the main features of the C517A: • Full upward compatibility with SAB 80C517A/83C517A-5 • Up to 24 MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation • Superset of the 8051 architecture with 8 datapointers • 32K byte on-chip ROM (with optional ROM protection) • • • • • • • – alternatively up to 64K byte external program memory Up to 64K byte external data memory 256 byte on-chip RAM 2K byte on-chip RAM (XRAM) Seven 8-bit parallel I/O ports Two input ports for analog/digital input Two full duplex serial interfaces (USART) – 4 operating modes, fixed or variabie baud rates – programmable baud rate generators Four 16-bit timer/counters – Timer 0 / 1 (C501 compatible) – Timer 2 for 16-bit reload, compare, or capture functions – Compare timer for compare/capture functions Powerful 16-bit compare/capture unt (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs 10-bit A/D converter – 12 multiplexed analog inputs – Built-in self calibration Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog Power saving modes – Slow down mode – Idle mode (can be combined with slow down mode) – Software power down mode – Hardware power down mode 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels On-chip emulation support logic (Enhanced Hooks Technology TM) P-MQFP-100 and P-LCC-84 packages Temperature Ranges : SAB-C517A TA = 0 to 70 °C SAF-C517A TA = -40 to 85 °C TA = -40 to 110 °C SAH-C517A • • • • • • • • Semiconductor Group 1-2 Introduction C517A VCC VDD VSS Port 7 8-bit Analog/ Digital Input Port 8 4-bit Analog/ Digital Input XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD OWE RO HWPD Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O C517A Port 3 8-Bit Digital I/O Port 4 8-Bit Digital I/O Port 5 8-Bit Digital I/O Port 6 8-Bit Digital I/O VAREF VAGND MCL03318 Figure 1-2 Logic Symbol Semiconductor Group 1-3 Introduction C517A 1.1 Pin Configuration This section describes the pin configration of the C517A in the P-MQFP-100 and P-LCC-84 packages. P1.5/T2EX P1.6/CLKOUT P1.7/T2 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 N.C. N.C. P7.0/AIN0 P7.1/AIN1 P7.2/AIN2 P7.3/AIN3 P7.4/AIN4 P7.5/AIN5 P7.6/AIN6 CC4/INT2/P1.4 N.C. N.C. N.C. N.C. CC3/INT6/P1.3 CC2/INT5/P1.2 CC1/INT4/P1.1 CC0/INT3/P1.0 V SS VCC V DD XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA N.C. P0.0/AD0 P0.1/AD1 N.C. N.C. P0.2/AD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C517A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P7.7/AIN7 VAGND VAREF N.C. N.C. N.C. N.C. RESET P4.7/CM7 P4.6/CM6 P4.5/CM5 P4.4/CM4 P4.3/CM3 PE/SWD P4.2/CM2 P4.1/CM1 P4.0/CM0 VCC VDD VSS RO P8.3/AIN11 P8.2/AIN10 P8.1/AIN9 P8.0/AIN8 P6.7 P6.6 P6.5 N.C. N.C. N.C. P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 HWPD CCM7/P5.7 CCM6/P5.6 CCM5/P5.5 CCM4/P5.4 CCM3/P5.3 CCM2/P5.2 CCM1/P5.1 CCM0/P5.0 OWE ADST/P6.0 RxD1/P6.1 TxD1/P6.2 P6.3 P6.4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MCP03319 Figure 1-3 Pin Configuration P-MQFP-100 Package (Top View) Semiconductor Group 1-4 Introduction C517A VAGND P7.7/AIN7 P7.6/AIN6 P7.5/AIN5 P7.4/AIN4 P7.3/AIN3 P7.2/AIN2 P7.1/AIN1 P7.0/AIN0 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P1.7/T2 P1.6/CLKOUT P1.5/T2EX P1.4/INT2/CC4 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 VAREF RESET P4.7/CM7 P4.6/CM6 P4.5/CM5 P4.4/CM4 P4.3/CM3 PE/SWD P4.2/CM2 P4.1/CM1 P4.0/CM0 VDD VSS RO P8.3/AIN11 P8.2/AIN10 P8.1/AIN9 P8.0/AIN8 P6.7 P6.6 P6.5 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 &$ P6.4 P6.3 P6.2/TxD1 P6.1/RxD1 P6.0/ADST OWE P5.0/CCM0 P5.1/CCM1 P5.2/CCM2 P5.3/CCM3 P5.4/CCM4 P5.5/CCM5 P5.6/CCM6 P5.7/CCM7 HWPD P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 Figure 1-4 Pin Configuration P-LCC-84 Package (Top View) Semiconductor Group P1.3/INT6/CC3 P1.2/INT5/CC2 P1.1/INT4/CC1 P1.0/INT3/CC0 VSS VDD XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.0/AD0 P0.1/AD1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1-5 Introduction C517A 1.2 Pin Definitions and Functions This section describes all external signals of the C517A with its function. Semiconductor Group 1-6 Introduction C517A Table 1-1 Pin Definitions and Functions 6\PERO P1.0 - P1.7 9 - 6, 1, 100 - 98 3LQ 1XPEHU 304)3 3/&& 36 - 29 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / INT3 / CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 / INT4 / CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 / INT5 / CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 / INT6 / CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 / INT2 / CC4 Interrupt 2 input / compare 4 output / capture 4 input P1.5 / T2EX Timer 2 external reload / trigger input P1.6 / CLKOUT System clock output P1.7 / T2 Counter 2 input ,2  )XQFWLRQ 9 36 8 35 7 34 6 33 1 32 100 99 98 *) I = Input, O = Output 31 30 29 Semiconductor Group 1-7 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO VSS 10, 62 3LQ 1XPEHU 304)3 3/&& 37, 83 – Ground (0V) during normal, idle, and power down operation. Supply voltage during normal, idle, and power down mode. XTAL2 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. XTAL1 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. ,2  )XQFWLRQ VDD XTAL2 11, 63 12 38, 84 39 – – XTAL1 13 40 – P2.0 - P2.7 14 - 21 41 - 48 I/O *) I = Input O = Output Semiconductor Group 1-8 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO PSEN 22 3LQ 1XPEHU 304)3 3/&& 49 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. External Access Enable When held high, the C517A executes instructions from the internal ROM as long as the PC is less than 8000H. When held low, the C517A fetches all instructions from external program memory. For the C517A-L this pin must be tied low. For the C517A-4R, if the device is protected (see section 4.6) then this pin is only latched during reset. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C517A4R. External pullup resistors are required during program verification. ,2  )XQFWLRQ ALE 23 50 O EA 24 51 I P0.0 - P0.7 26, 27, 30 - 35 52 - 59 I/O *) I = Input O = Output Semiconductor Group 1-9 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO HWPD 36 3LQ 1XPEHU 304)3 3/&& 60 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C517A. A low level for a longer period will force the part into hardware power down mode with the pins floating. There is no internal pullup resistor connected to this pin. Port 5 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 5 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. This port also serves the alternate function "Concurrent Compare" and "Set/Reset Compare". The secondary functions are assigned to the port 5 pins as follows: CCM0 to CCM7 P5.0 to P5.7 : concurrent compare or Set/Reset lines Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog. When left unconnected this pin is pulled high by a weak internal pull-up resisitor. The logic level at OWE should not be changed during normal operation. When held at low level the oscillator watchdog function is turned off. During hardware power down the pullup resistor is switched off. ,2  )XQFWLRQ P5.0 - P5.7 44 - 37 68 - 61 I/O OWE 45 69 I *) I = Input O = Output Semiconductor Group 1-10 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO P6.0 - P6.7 46 - 50, 54 - 56 3LQ 1XPEHU 304)3 3/&& 70 - 77 I/O Port 6 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 6 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 6 also contains the external A/D converter start control pin and the transmit and receive pins for the serial interface 1. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 6, as follows : external A/D converter P6.0 ADST start pin P6.1 RxD1 receiver data input of serial interface 1 P6.2 TxD1 transmitter data input of serial interface 1 Port 8 is a 4-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the higher 4-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P8.0 - P8.3 AIN8 - AIN11 analog input 8 - 11 Reset Output This pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watchdog reset. The RO output signal is active low. ,2  )XQFWLRQ 46 47 48 P8.0 - P8.3 57 - 60 70 71 72 78 - 81 I RO 61 82 O *) I = Input O = Output Semiconductor Group 1-11 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO P4.0 - P4.7 64 - 66, 68 - 72 3LQ 1XPEHU 304)3 3/&& 1 - 3, 5-9 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 4 also serves as alternate compare functions. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 4 as follows : P4.0 - P4.7 CM0 - CM7 Compare channel 0 - 7 Power saving mode enable / Start watchdog timer A low level at this pin allows the software to enter the power saving modes (idle mode, slow down mode, and power down mode). In case the low level is also seen during reset, the watchdog timer function is off on default. Usage of the software controlled power saving modes is blocked, when this pin is held at high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. During hardware power down the pullup resisitor is switched off. ,2  )XQFWLRQ PE/SWD 67 4 I *) I = Input O = Output Semiconductor Group 1-12 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO P3.0 - P3.7 90 - 97 3LQ 1XPEHU 304)3 3/&& 21 - 28 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / RxD0 Receiver data input (asynch.) or data input/output (synch.)of serial interface 0 P3.1 / TxD0 Transmitter data output (asynch.) or clock output (synch.) of serial interface 0 External interrupt 0 input / P3.2 / INT0 timer 0 gate control input External interrupt 1 input / P3.3 / INT1 timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input WR control output; latches P3.6 / WR the data byte from port 0 into the external data memory RD control output; enables P3.7 / RD the external data memory ,2  )XQFWLRQ 90 21 91 22 92 93 94 95 96 23 24 25 26 27 97 *) I = Input O = Output 28 Semiconductor Group 1-13 Introduction C517A Table 1-1 Pin Definitions and Functions (cont’d) 6\PERO RESET 73 3LQ 1XPEHU 304)3 3/&& 10 I RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C517A. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . Reference voltage for the A/D converter Reference ground for the A/D converter Port 7 is an 8-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the lower 8-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P7.0 - P7.7 AIN0 - AIN7 analog input 0 - 7 Not connected These pins of the P-MQFP-100 package must not be connected. ,2  )XQFWLRQ VAREF VAGND P7.0 - P7.7 78 79 87 - 80 11 12 20-13 – – I N.C. 2 - 5, 25, 28, 29, 51 - 53, 74 - 77 88, 89 – – *) I = Input O = Output Semiconductor Group 1-14 Fundamental Structure C517A 2 Fundamental Structure The C517A is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C517A incorporates a CPU with 8 datapointers, a genuine 10-bit A/D converter, a capture/compare unit, two USART serial interfaces, a XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C517A. Semiconductor Group 2-1 Fundamental Structure C517A Oscillator Watchdog XTAL1 XTAL2 ALE PSEN EA PE/SWD RESET HWPD RO OWE Timer 1 Timer 2 Capture Compare Unit Compare Timer Port 3 Serial Channel 0 Programmable Baud Rate Generator Serial Channel 1 Programmable Baud Rate Generator Interrupt Unit Port 5 Port 4 Port 4 8-Bit Digital I/O Port 5 8-Bit Digital I/O Port 6 8-Bit Digital I/O Port 7 8-Bit Analog/ Digital Input Port 8 4-Bit Analog/ Digital Input Port 2 Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O Port 1 Port 1 8-Bit Digital I/O Programmable Watchdog Timer Timer 0 CPU 8 Datapointer Emulation Support Logic Port 0 Port 0 8-Bit Digital I/O OSC & Timing RAM 256 x 8 XRAM 2k x 8 ROM 32k x 8 Port 6 VAREF VAGND S&H A/D Converter 10 Bit Analog MUX Port 7 Port 8 C517A MCB03320 Figure 2-1 Block Diagram of the C517A Semiconductor Group 2-2 Fundamental Structure C517A 2.1 CPU The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires six oscillator cycles (this number of oscillator cycles differs from other members of the C500 microcontroller family). The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set. The C517A uses five addressing modes: direct access, immediate, register, register indirect access, and for accessing the external data or program memory portions a base register plus index-register indirect addressing. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 24 MHz clock, 58% of the instructions execute in 500 ns. The CPU (Central Processing Unit) of the C517A consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-3 Fundamental Structure C517A Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-4 Fundamental Structure C517A 2.2 CPU Timing A machine cycle of the C517A consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-toregister transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Semiconductor Group 2-5 Fundamental Structure C517A S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL1) ALE Read Opcode S1 a) 1-Byte, S2 S3 S4 Read next Opcode (Discard) S5 S6 Read next Opcode again 1-Cycle Instruction, e.g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 # Data Read next Opcode again Read Opcode S1 S2 S3 S4 Read next Opcode (Discard) S5 S6 S1 S2 S3 S4 S5 S6 Read next Opcode b) 2-Byte, 1-Cycle Instruction, e.g. ADD A, c) 1-Byte, 2-Cycle Instruction, e.g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read next Opcode (Discard) S5 ADDR S6 S1 Read next Opcode again No Fetch No ALE S2 DATA MCD03218 No Fetch S3 S4 S5 S6 d) MOVX (1-Byte, 2-Cycle) Access External Memory Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-6 0HPRU\ 2UJDQL]DWLRQ C517A 3 Memory Organization The C517A CPU manipulates operands in the following four address spaces: – – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 2K bytes of internal XRAM data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C517A. FFFF H int. (XMAP0 = 0) ext. ext. (XMAP0 = 1) FFFF H F800 H 8000 H 7FFF H int. (EA = 1) ext. (EA = 0) 0000 H "Code Space" ext. F7FF H Indirect Address FF H Internal RAM 80 H Internal RAM Direct Address Special Function Regs. 7F H FF H 80 H 0000 H "Data Space" 00 H "Internal Data Space" MCB03321 Figure 3-1 C517A Memory Map Semiconductor Group 3-1 0HPRU\ 2UJDQL]DWLRQ C517A 3.1 Program Memory, "Code Space" The C517A-4R has 32 Kbytes of read-only program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C517A-4R executes program code out of the internal ROM unless the program counter address exceeds 7FFFH. Address locations 8000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C517A fetches all instructions from the external 64K byte program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal XRAM is located in the external address memory area at addresses F800H to FFFFH. Using MOVX instruction with addresses pointing to this address area, alternatively internal XRAM or external data RAM are accessed. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07 H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 0HPRU\ 2UJDQL]DWLRQ C517A 3.4 XRAM Operation The XRAM in the C517A is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. 3.4.1 XRAM Access Control Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM accesses. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XXXXXX01B LSB 0 SYSCON 6 – 5 – 4 – 3 – 2 – 1 XMAP1 XMAP0 The functions of the shaded bits are not described in this section. Bit – XMAP1 Function Reserved bits for future use. XRAM visible access control Control bit for RD/WR signals during XRAMaccesses. If addresses are outside the XRAM address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to the XRAM XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM. In this mode, address and data information during XRAM accesses are visible externally. Global XRAM access enable/disable control XMAP0 = 0 : The access to XRAM is enabled. XMAP0 = 1 : The access to XRAM is disabled (default after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. XMAP0 When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM RD and WR become active and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM. This feature allows to check externally the internal data transfers to the XRAM. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted. Semiconductor Group 3-3 0HPRU\ 2UJDQL]DWLRQ C517A After a reset operation, bit XMAP0 is reset. This means that the accesses to the XRAM are generally disabled. In this case, all accesses using MOVX instructions within the address range of F800H to FFFFH generate external data memory bus cycles. When XMAP0 is set, the access to the XRAM is enabled and all accesses using MOVX instructions with an address in the range of F800H to FFFFH will access internally the XRAM. Bit XMAP0 is hardware protected. If it is reset once (XRAM access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an unsymmetric latch at the XMAP0 bit. A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from teh external bus. To avoid this the XMAP0 bit is forced to ’1’ only by a reset operation. Additionally, during reset an internal capacitor is loaded. So the reset state is a disabled XRAM. Because of the load time of the capacitor, XMAP0 bit once written to ’0’ (that is, discharging the capacitor) cannot be set to ’1’ again by software. On the other hand, any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable status is XRAM enabled. The clear instruction for the XMAP0 bit should be integrated in the program initialization routine before the XRAM is used. In extremely noisy systems the user may have redundant clear instructions. Semiconductor Group 3-4 0HPRU\ 2UJDQL]DWLRQ C517A 3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are : – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of F800 H to FFFFH. 3.4.3 Accesses to XRAM using the Registers R0/R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX MOVX A, @ Ri @Ri, A (Read) (Write) In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as page register which selects pages of 256-Byte. However, the distinction, whether Port 2 is used as general purpose I/0 or as "page address" is made by the external system design. From the device's point of view it cannot be decided whether the Port 2 data is used externally as address or as I/0 data. Hence, a special page register is implemented into the C517A to provide the possibility of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM as Port 2 for external data memory. Special Function Register XPAGE $GGUHVV + Bit No. MSB 7 91H .7 5HVHW 9DOXH  + LSB 0 .0 XPAGE 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 Bit XPAGE.7-0 Function XRAM high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access the internal XRAM. Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differences in accessing XRAM, ext. RAM or what is to do when Port 2 is used as an I/O-port. Semiconductor Group 3-5 0HPRU\ 2UJDQL]DWLRQ C517A Port 0 Address/Data XRAM XPAGE Write to Port 2 Port 2 Page Address MCB02112 Figure 3-2 Write Page Address to Port 2 “MOV P2,pageaddress“ will write the page address to Port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM address range (F800 H - FFFFH), XRAM has to be disabled. When additional external RAM is to be addressed in an address range < F800H, XRAM may remain enabled and there is no need to overwrite XPAGE by a second move. Semiconductor Group 3-6 0HPRU\ 2UJDQL]DWLRQ C517A Port 0 Address/Data XRAM XPAGE Write to XPAGE Port 2 Address/ I/O-Data MCB02113 Figure 3-3 Write Page Address to XPAGE “MOV XPAGE,pageaddress“ will write the page address only to the XPAGE register. Port 2 is available for addresses or I/O data. Semiconductor Group 3-7 0HPRU\ 2UJDQL]DWLRQ C517A Port 0 Address/Data XRAM XPAGE Write I/O Data to Port 2 Port 2 I/O-Data MCB02114 Figure 3-4 Usage of Port 2 as I/O Port At a write to port 2, the XRAM address in the XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register. So, whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address. Example : I/O data at port 2 shall be AAH. A byte shall be fetched from XRAM at address F830H. MOV MOV MOV MOVX R0, #30H P2, #0AAH XPAGE, #0F8H A, @R0 ; ; P2 shows AAH ; P2 still shows AAH but XRAM is addressed ; the contents of XRAM at F830H is moved to accumulator Semiconductor Group 3-8 0HPRU\ 2UJDQL]DWLRQ C517A The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM address range, an external access is performed. For the C517A the content of XPAGE must be F8H - FFH in order to use the XRAM. The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used : a) Access to XRAM : The upper address byte must be written to XPAGE or P2; both writes select the XRAM address range. b) Access to external memory : The upper address byte must be written to P2; XPAGE will be loaded with the same address in order to deselect the XRAM. 3.4.4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset. After power-up the contents are undefined, while they remain unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value. 3.4.5 Behaviour of Port0 and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA. The table 3-7 lists the various operating conditions. It shows the following characteristics : a) Use of P0 and P2 pins during the MOVX access. Bus: The pins work as external address/data bus. If (internal) XRAM is accessed, the data written to the XRAM can be seen on the bus in debug mode. I/0: The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal or external XDATA memory. The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM behaves. Semiconductor Group 3-9 Semiconductor Group 3-10 EA = 0 XMAP1, XMAP0 00 MOVX @DPTR DPTR < XRAM address range DPTR ≥ XRAM address range MOVX @ Ri XPAGE < XRAM addr.page range XPAGE ≥ XRAM addr.page range a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus (RD/WR-Data) b)RD/WR inactive c)XRAM is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus (RD/WR-Data) P2→I/O b)RD/WR inactive c)XRAM is used 10 a)P0/P2→Bus b)RD/WR active c)ext.memory is used X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used 00 a)P0/P2→Bus b)RD/WR active c)ext.memory is used 10 EA = 1 XMAP1, XMAP0 X1 a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus a)P0/P2→I/O (RD/WR-Data) b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM is used c) ext.memory c)XRAM is used is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0/P2→Bus a)P0/P2→Bus (RD/WR-Data) b)RD/WR active b)RD/WR active c)XRAM is used c) ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0/P2→I/O a)P0→Bus a)P0→Bus (RD/WR-Data) P2→I/O P2→I/O b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM is used c)ext.memory is c)XRAM is used used a)P0→Bus a)P0→Bus (RD/WR-Data) P2→I/O P2→I/O b)RD/WR active b)RD/WR active c)XRAM is used c)ext.memory is used 0HPRU\ 2UJDQL]DWLRQ C517A modes compatible to 8051/C501 family Table 3-7 Behaviour of P0/P2 and RD/WR During MOVX Accesses 0HPRU\ 2UJDQL]DWLRQ C517A 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80 H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 93 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C517A are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C517A. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses.. Semiconductor Group 3-11 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-1 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register, High Byte A/D Converter Data Register, Low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register 0 Interrupt Request Control Register 1 Timer 0/1 Control Register Timer 2 Control Register Serial Channel 0 Control Register Serial Channel ! Control Register Compare Timer Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Address E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H D8H 1) DCH D9H DAH A8H 1) B8H 1) 9AH A9H B9H C0H 1) D1H 88H 1) C8H 1) 98H 1) 9BH E1H EFH E9H EAH EBH ECH EDH EEH 88H 1) 8CH 8DH 8AH 8BH 89H Contents after Reset 00H 00H 00H 00H XXXX X000B 3) 00H 07H 00H 0XXX 0000B 3) 00H 00XX XXXXB 3 00H 00H XX00 00X0B 3) 00H XX00 0000B 3) 00H 00H 00H 00H 00H 0X00 0000B 3) 0X00 0000B 3) 0XXXXXXXB 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) 00H 00H 00H 00H 00H 00H A/DADCON0 2) Converter ADCON1 ADDATH ADDATL Interrupt System IEN0 2) IEN1 2) IEN2 IP0 2) IP1 IRCON0 2) IRCON1 TCON 2) T2CON 2) S0CON 2) S1CON 2) CTCON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 TCON TH0 TH1 TL0 TL1 TMOD 2) MUL/DIV Unit Timer 0 / Timer 1 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group 3-12 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Compare/ Capture Unit (CCU) Timer 2 Symbol CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL Name Address C1H C9H C3H C5H C7H CFH C2H C4H C6H CEH F6H D3H D5H D7H E3H E5H E7H F3H F5H D2H D4H D6H E2H E4H E6H F2H F4H F7H CBH CAH A1H A2H A3H A4H A5H A6H E1H DFH DEH CDH CCH C8H 1) C0H 1) Contents after Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0X00 0000B 3) 00H 00H 00H 00H 00H 00H Compare/Capture Enable Register Compare/Capture 4 Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 4, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Comp./Rel./Capt. Register High Byte Comp./Rel./Capt. Register Low Byte COMSETL Compare Set Register Low Byte COMSETH Compare Set Register, High Byte COMCLRL Compare Clear Register, Low Byte COMCLRH Compare Clear Register, High Byte Compare Set Mask Register SETMSK CLRMSK Compare Clear Mask Register CTCON 2) Compare Timer Control Register Compare Timer Rel. Register, High Byte CTRELH Compare Timer Rel. Register, Low Byte CTRELL Timer 2, High Byte TH2 Timer 2, Low Byte TL2 T2CON 2) Timer 2 Control Register IRCON0 2) Interrupt Request Control Register 0 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group 3-13 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 XPAGE SYSCON 2) Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit Page Address Register for Extended On-Chip RAM System/XRAM Control Register A/D Converter Control Register Power Control Register Serial Channel 0 Buffer Register Serial Channel 0 Control Register Serial Channel 0 Reload Reg., Low Byte Serial Channel 0 Reload Reg., High Byte Serial Channel 1 Buffer Register Serial Channel 1 Control Register Serial Channel 1 Reload Reg., Low Byte Serial Channel 1 Reload Reg., High Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Watchdog Timer Reload Register Power Control Register Address 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) F8H 1) FAH DBH DDH 91H B1H D8H 1) 87H 99H 98H 1) AAH BAH 9CH 9BH 9DH BBH A8H1) B8H 1) A9H 86H 87H Contents after Reset FFH FFH FFH FFH FFH FFH FFH – – 00H XXXX XX01B 3) 00H 00H XXH 3) 00H D9H XXXX XX11B 3) XXH 3) 0X00 0000B 3) 00H XXXX XX11B 3) 00H 00H 00H 00H 00H XRAM Serial Channels ADCON0 2) PCON 2) S0BUF S0CON 2) S0RELL S0RELH S1BUF S1CON 2) S1RELL S1RELH Watchdog IEN0 2) IEN1 2) IP0 2) WDTREL Pow. Sav. PCON 2) Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved. Semiconductor Group 3-14 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H SP 82H 83H 83H DPL DPH FFH 07H 00H 00H .7 .7 .7 .7 WDTPSEL TF1 GATE .7 .7 .7 .7 T2 .7 – SM0 .7 – SM .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 M1 .5 .5 .5 .5 T2EX .5 – SM20 .5 ECR SM21 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 SD TR0 M0 .4 .4 .4 .4 INT2 .4 – REN0 .4 ECS REN1 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 INT6 .3 – TB80 .3 ECT TB81 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 INT5 .2 .2 RB80 .2 ECMP RB81 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 INT4 .1 .1 TI0 .1 – TI1 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 INT3 .0 .0 RI0 .0 ES1 RI1 .0 .0 .0 .0 .0 .0 WDTREL 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H XXXXX000B 00H XXH XX0000X0B 0X000000B XXH 00H FFH 87H PCON 88H 2) TCON 89H 8AH 8BH 8CH 8DH TMOD TL0 TL1 TH0 TH1 SMOD PDS TR1 C/T .6 .6 .6 .6 CLKOUT .6 – SM1 .6 – – .6 .6 .6 .6 .6 90H 2) P1 91H 92H XPAGE DPSEL 98H 2) S0CON 99H S0BUF 9AH 9BH 9CH 9DH IEN2 S1CON S1BUF S1RELL A0H2) P2 A1H COMSETL 00H A2H COMSETH 00H A3H COMCLRL 00H .7 .6 .5 .4 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group 3-15 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) A4H A5H COMCLRH 00H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .7 .7 .7 EAL .7 RD – .6 .6 .6 WDT .6 WR – .5 .5 .5 ET2 .5 T1 – .4 .4 .4 ES0 .4 .4 T0 – EX5 .4 – – IEX5 COCA L2 .4 .4 .4 .4 .4 .4 T2R1 .3 .3 .3 ET1 .3 .3 INT1 – EX4 .3 – – IEX4 COCA H1 .3 .3 .3 .3 .3 .3 T2R0 .2 .2 .2 EX1 .2 .2 INT0 – EX3 .2 – – IEX3 COCA L1 .2 .2 .2 .2 .2 .2 T2CM .1 .1 .1 ET0 .1 .1 TxD0 .0 .0 .0 EX0 .0 .0 RxD0 SETMSK 00H A6H CLRMSK 00H A8H2) IEN0 00H A9H IP0 00H AAH S0RELL B0H2) P3 B1H D9H FFH OWDS WDTS .5 SYSCON XXXXXX01B 00H XX000000B XXXXXX11B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XMAP1 XMAP0 B8H2) IEN1 B9H IP1 BAH S0RELH BBH S1RELH C0H 2) EXEN2 SWDT EX6 – – – EXF2 COCA H3 .7 .7 .7 .7 .7 .7 T2PS – – – TF2 COCA L3 .6 .6 .6 .6 .6 .6 I3FR .5 – – IEX6 COCA H2 .5 .5 .5 .5 .5 .5 I2FR EX2 .1 .1 .1 IEX2 COCA H0 .1 .1 .1 .1 .1 .1 T2I1 EADC .0 .0 .0 IADC COCA L0 .0 .0 .0 .0 .0 .0 T2I0 IRCON0 CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON CC4EN C1H C2H C3H C4H C5H C6H C7H C8H 2) C9H COCO COCO COCO COCO COCO COCA EN1 N2 N1 N0 EN0 H4 COCA COMO L4 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group 3-16 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) CAH CRCL CBH CRCH CCH TL2 CDH TH2 CEH CCL4 CFH CCH4 D0H 2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H .7 .7 .7 .7 .7 .7 CY .6 .6 .6 .6 .6 .6 AC .5 .5 .5 .5 .5 .5 F0 .4 .4 .4 .4 .4 .4 RS1 .3 .3 .3 .3 .3 .3 RS0 .2 .2 .2 .2 .2 .2 OV .1 .1 .1 .1 .1 .1 F1 .0 .0 .0 .0 .0 .0 P PSW IRCON1 CML0 CMH0 CML1 CMH1 CML2 CMH2 D1H D2H D3H D4H D5H D6H D7H D8H 2) ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0 .7 .7 .7 .7 .7 .7 BD .9 .1 .7 ADCL – .7 .7 .7 .6 .6 .6 .6 .6 .6 CLK .8 .0 .6 – – .6 .6 .6 .5 .5 .5 .5 .5 .5 ADEX .7 – .5 – – .5 .5 .5 ICR .5 .4 .4 .4 .4 .4 .4 BSY .6 – .4 – – .4 .4 .4 ICS .4 .3 .3 .3 .3 .3 .3 ADM .5 – .3 MX3 .3 .3 .3 .3 CTF .3 .2 .2 .2 .2 .2 .2 MX2 .4 – .2 MX2 .2 .2 .2 .2 CLK2 .2 .1 .1 .1 .1 .1 .1 MX1 .3 – .1 MX1 .1 .1 .1 .1 CLK1 .1 .0 .0 .0 .0 .0 .0 MX0 .2 – .0 MX0 .0 .0 .0 .0 CLK0 .0 ADCON0 00H D9H ADDATH 00H DAH ADDATL 00XXXXXXB DBH P7 – DCH ADCON1 0XXX0000B 00H DFH CTRELH 00H E0H2) ACC 00H E1H E2H CTCON CML3 0X00. 0000B 00H DDH P8 DEH CTRELL – T2PS1 – .7 .6 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group 3-17 0HPRU\ 2UJDQL]DWLRQ C517A Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) E3H E4H E5H E6H E7H CMH3 CML4 CMH4 CML5 CMH5 00H 00H 00H 00H 00H FFH XXH XXH XXH XXH XXH XXH 0XXX. XXXXB 00H 00H 00H 00H 00H 00H 00H FFH FFH .7 .7 .7 .7 .7 CM7 .7 .7 .7 .7 .7 .7 MDEF .7 .7 .7 .7 .7 .7 .7 CCM7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .6 CM6 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 CM5 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 CM4 .4 .4 .4 .4 .4 .4 SC.4 .4 .4 .4 .4 .4 .4 .4 CCM4 .4 .3 .3 .3 .3 .3 CM3 .3 .3 .3 .3 .3 .3 SC.3 .3 .3 .3 .3 .3 .3 .3 CCM3 .3 .2 .2 .2 .2 .2 CM2 .2 .2 .2 .2 .2 .2 SC.2 .2 .2 .2 .2 .2 .2 .2 CCM2 TxD1 .1 .1 .1 .1 .1 CM1 .1 .1 .1 .1 .1 .1 SC.1 .1 .1 .1 .1 .1 .1 .1 CCM1 RxD1 .0 .0 .0 .0 .0 CM0 .0 .0 .0 .0 .0 .0 SC.0 .0 .0 .0 .0 .0 .0 .0 CCM0 ADST E8H2) P4 E9H MD0 EAH MD1 EBH MD2 ECH MD3 EDH MD4 EEH MD5 EFH ARCON F0H2) B F2H CML6 F3H F4H F5H F6H CMH6 CML7 CMH7 CMEN MDOV SLR .6 .6 .6 .6 .6 .6 .6 CCM6 .6 .5 .5 .5 .5 .5 .5 .5 CCM5 .5 F7H CMSEL F8H2) P5 FAH P6 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group 3-18 External Bus Interface C517A 4 External Bus Interface The C517A allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FF H to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 External Bus Interface C517A a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN MCT03220 RD P2 P0 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 External Bus Interface C517A 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: – - whenever signal EA is active (low); or – - whenever the program counter (PC) content is greater than 7FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN, Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C517A the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-3 External Bus Interface C517A 4.4 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensures that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System interface to emulation hardware SYSCON PCON TCON C500 MCU opt. I/O Ports RESET EA ALE PSEN Port 0 Port 2 Port 3 Port 1 RSYSCON RPCON RTCON Enhanced Hooks Interface Circuit RPORT RPORT 2 0 TEA TALE TPSEN EH-IC Target System Interface MCS03254 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 4-4 External Bus Interface C517A 4.5 Eight Datapointers for Faster External Bus Access 4.5.1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be handled bytewise. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. 4.5.2 How the eight Datapointers of the C517A are realized Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051/C501 instruction set. This instruction set, however, allows the handling of only one single 16-bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C517A contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C517A which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 4-3 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx. Special Function Register DPSEL $GGUHVV + Bit No. MSB 7 92H – 5HVHW 9DOXH  XXXXX000B LSB 0 .0 DPSEL 6 – 5 – 4 – 3 – 2 .2 1 .1 Bit – DPSEL.2-0 Function Reserved bits for future use. Data pointer select bits DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7. Semiconductor Group 4-5 External Bus Interface C517A ----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 .2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory MCD00779 DPTR0 DPH(83 H ) DPL(82 H) Figure 4-3 Accessing of External Data Memory via Multiple Datapointers 4.5.3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM. 4.5.4 Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H Semiconductor Group 4-6 External Bus Interface C517A Example 1 : Using only One Datapointer (Code for a C501) Initialization Routine MOV MOV MOV MOV LOW(SRC_PTR), #0FFH HIGH(SRC_PTR), #1FH LOW(DES_PTR), #0A0H HIGH(DES_PTR), #2FH ;Initialize shadow_variables with source_pointer ;Initialize shadow_variables with destination_pointer Table Look-up Routine under Real Time Conditions PUSH PUSH MOV MOV ;INC ;CJNE MOVC MOV MOV MOV MOV INC MOVX MOV MOV POP POP ; DPL DPH DPL, LOW(SRC_PTR) DPH, HIGH(SRC_PTR) DPTR … A,@DPTR LOW(SRC_PTR), DPL HIGH(SRC_PTR), DPH DPL, LOW(DES_PTR) DPH, HIGH(DES_PTR) DPTR @DPTR, A LOW(DES_PTR), DPL HIGH(DES_PTR),DPH DPH DPL ; Number of cycles ;Save old datapointer 2 ; 2 ;Load Source Pointer 2 ; 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and 2 ;load destination_pointer 2 ; 2 ; 2 ;Increment destination_pointer ;(ex. time not relevant) – ;Transfer byte to destination address 2 ;Save destination_pointer 2 ; 2 ;Restore old datapointer 2 ; 2 Total execution time (machine cycles) : 28 Semiconductor Group 4-7 External Bus Interface C517A Example 2 : Using Two Datapointers (Code for an C517A) Initialization Routine MOV MOV MOV MOV DPSEL, #06H DPTR, #1FFFH DPSEL, #07H DPTR, #2FA0H ;Initialize DPTR6 with source pointer ;Initialize DPTR7 with destination pointer Table Look-up Routine under Real Time Conditions PUSH MOV ;INC ;CJNE MOVC MOV MOVX POP DPSEL DPSEL, #06H DPTR … A,@DPTR DPSEL, #07H @DPTR, A DPSEL ; Number of cycles ;Save old source pointer 2 ;Load source pointer 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and ;load destination_pointer 2 ;Transfer byte to destination address 2 ;Save destination pointer and ;restore old datapointer 2 Total execution time (machine cycles) : 12 ; The above example shows that utilization of the C517A’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an C517A program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use. Semiconductor Group 4-8 External Bus Interface C517A 4.6 ROM Protection for the C517A The C517A-4R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C517A-4R version has to define whether ROM protection has to be selected or not. The C517A-4R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected as well as protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C517A-4R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different : ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort. The behaviour of the move code instruction, when the code is executed from the external ROM, is in such a way that accessing a code byte from a protected on-chip ROM address is not possible. In this case the byte accessed will be invalid. 4.6.1 Unprotected ROM Mode If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-4 is used to read out the contents of the ROM. The AC timing characteristics of the ROM verification mode is shown in the AC specifications in the C517A Data Sheet. P1.0-P1.7 P2.0-P2.6 Address 1 Address 2 Inputs: PSEN = V SS ALE, EA = V IH / V IH2 RESET = V IL2 Port 0 Data 1 Out Data 2 Out MCT03255 Figure 4-4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. Then the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines. After a delay time, port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C517A must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. Semiconductor Group 4-9 External Bus Interface C517A 4.6.2 Protected ROM Mode If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications in the C517A Data Sheet. RESET 1. ALE Pulse after Reset ~ ~ 12 t CLCL 6 t CLCL ~ ~ ALE Latch ~ ~ Latch ~ ~ ~ ~ ~ ~ Latch Data for Addr. X-16-1 Data for Addr. X-16 Latch Data for Addr. x-16+1 Port 0 ~ ~ ~ ~ Data for Addr. 0 Data for Addr. 1 ~ ~ ~ ~ P3.5 Inputs : ALE = VSS PSEN, EA = VIH RESET = Low : Error High : OK MCT03222 Figure 4-5 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C517A outputs an ALE signal with a period of 12 tCLCL and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way : 1. Data Byte = 2. Data Byte = 3. Data Byte = : 16. Data Byte = : content of internal ROM address 0000H content of internal ROM address 0001H content of internal ROM address 0002H content of internal ROM address 000FH The C517A-4R does not output any address information during the ROM verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000 H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the ROM content of the actual address. If an verify error is detected, the error Semiconductor Group 4-10 External Bus Interface C517A condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C517A must be provided with a system clock at the XTAL pins. Figure 4-6 shows an application example of an external circuitry which allows to verify a protected ROM inside the C517A-4R in ROM verification mode 2. With RESET going inactive, the C517A-4R starts the ROM verify sequence. Its ALE is clocking a 16-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the contents of the internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the verify operation. P3.5 can be latched with the falling edge of ALE. When the last byte of the internal ROM has been handled, the C517A-4R starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM verification. P3.5 Verify Detect Logic Carry CLK 15-Bit Address Counter S ALE 2 kΩ A0-A14 C517A-4R & RESET Compare Code ROM VCC VDD & Port 0 EA D0-D7 VDD VCC PSEN CS OE MCS03322 Figure 4-6 ROM Verification Mode 2 - External Circuitry Example Semiconductor Group 4-11 External Bus Interface C517A Semiconductor Group 4-12 Reset / System Clock C517A 5 5.1 Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C517A allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power down mode is to be terminated. Additional to the hardware reset, which is applied externally to the C517A, there are two internal reset sources, the watchdog timer and the oscillator watchdog. This chapter deals only with the external hardware reset. The reset input is an active low input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes high again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the RESET pin, a pullup resistor is internally connected to VDD to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained when VDD is applied by connecting the reset pin to VSS via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. Semiconductor Group 5-1 Reset / System Clock C517A The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. a) b) & + RESET RESET C517A c) C517A + RESET C517A MCS03323 Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0 to 6 are set to FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/ O port lines (ports 1,3 to 6) output a one (1). Port 2 lines output a zero (or one) after reset, if EA is held low (or high). Port 7 and 8 are input-only ports. They have no internal latch and therefore the contents of the special function registers P7 and P8 depend on the levels applied to port 7 or 8. The content of the internal RAM of the C517A is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. Semiconductor Group 5-2 Reset / System Clock C517A 5.2 Fast Internal Reset after Power-On The C517A uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C517A the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator’s output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-2). Under worst case conditions (fast VDD rise time - e.g. 1µs, measured from VDD = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VDD below 4.25V (lower specification limit). Therefore, at slower VDD rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-2, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-2, III). However, an externally applied reset still remains active ( figure 5-2, IV) and the device does not start program execution ( figure 5-2, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – – Termination of software power down mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficent in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin. Semiconductor Group 5-3 Semiconductor Group Reset II III IV V Clock from RC-Oscillator, Reset at Ports On-chip oscillator starts; final reset sequence by oscillator WD; max. 768 Cycles Port remains in reset because of ext. reset signal Start of program execution MCD02722 Ports Undef. Figure 5-2 Power-On Reset of the C517A On-Chip Oscillator RC Oscillator 5-4 VDD VCC RESET Phase I Reset / System Clock C517A Power On; undef. Port typ. 18 µs max. 34 µs Reset / System Clock C517A 5.3 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1’s etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this time the C517A remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. PCL IN OUT PCH OUT P2 ALE MCT01879 Figure 5-3 CPU Timing after Reset Semiconductor Group 5-5 Reset / System Clock C517A 5.4 Oscillator and Clock Circuit X TAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-4 shows the recommended oscillator circuit. C XTAL2 3.5-24 MHz C517A XTAL1 C C = 20 pF ± 10 pF for Crystal Operation MCS03324 Figure 5-4 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. Semiconductor Group 5-6 Reset / System Clock C517A To Internal Timing Circuitry C517A XTAL1 *) XTAL2 C1 C2 *) Crystal or ceramic resonator MCS03325 Figure 5-5 On-Chip Oscillator Circuiry To drive the C517A with an external clock source, the external clock signal has to be applied to XTAL2, as shown in figure 5-6. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2. VCC V DD N.C. External Clock Signal C517A XTAL1 XTAL2 MCS03326 Figure 5-6 External Clock Source Semiconductor Group 5-7 Reset / System Clock C517A 5.5 System Clock Output For peripheral devices requiring a system clock, the C517A provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON0), a clock signal with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset. Special Function Register ADCON0 (Address D8H) MSB DFH BD Reset Value : 00H LSB D8H MX0 ADCON0 Bit No. D8H DEH CLK DDH ADEX DCH BSY DBH ADM DAH MX2 D9H MX1 The shaded bits are not used for clock output control. Bit CLK Function Clock output enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/12 of the oscillator frequency. The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 5-7. Note : During slow-down operation the frequency of the CLKOUT signal is divided by 8. Semiconductor Group 5-8 Reset / System Clock C517A S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-7 Timing Diagram - System Clock Output Semiconductor Group 5-9 Reset / System Clock C517A Semiconductor Group 5-10 On-Chip Peripheral Components C517A 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C517A except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C517A has seven 8-bit digital I/O ports and one 8-bit and one 4-bit input port for analog/digital input. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 6 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 6 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET . 6.1.1 Port Structures The C517A generally allows digital I/O on 56 lines grouped into 7 bidirectional C501 compatible 8bit ports and one 8-bit and one 4-bit analog/digital input port. Each port bit (except port 7, 8) consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 to P6 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. These alternate functions of the port pins are listed in table 6-1. When port 7 or 8 is used as analog input, an analog channel is switched to the A/D converter through a 4-bit multiplexer, which is controlled by three bits in SFR ADCON1. Port 6 lines may also be used as digital inputs. In this case they are addressed as an input port via SFR P7 or P8. Since ports 7 and 8 have no internal latch, the contents of SFR P7 or P8 only depends on the levels applied to the input lines. It makes no sense to output a value to these input-only port by writing to the SFR P7 or P8. This will have no effect. Semiconductor Group 6-1 On-Chip Peripheral Components C517A Table 6-1 Alternate Functions of Port 1, 3, 4, 5, and 6 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 Alternate Functions INT3 / CC0 INT4 / CC1 INT5 / CC2 INT6 / CC3 INT2 / CC4 T2EX CLKOUT T2 RxD0 TxD0 INT0 INT1 T0 T1 WR RD CM0 CM1 CM2 CM3 CM4 CM5 CM6 CM7 CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 ADST RxD1 TxD1 Description External Interrupt 3 input / Capture/compare 0 input/output External Interrupt 4 input / Capture/compare 1 input/output External Interrupt 5 input / Capture/compare 2 input/output External Interrupt 6 input / Capture/compare 3 input/output External Interrupt 2 input / Capture/compare 4 input/output Timer 2 external reload/trigger input System clock output Timer 2 external count input Serial port 0 receiver data input (asynchronous) or data input/output (synchronous) Serial port 0 transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external count input Timer 1 external count input External data memory write strobe External data memory read strobe Compare output for the CM0 register Compare output for the CM1 register Compare output for the CM2 register Compare output for the CM3 register Compare output for the CM4 register Compare output for the CM5 register Compare output for the CM6 register Compare output for the CM7 register Concurrent compare 0 output Concurrent compare 1 output Concurrent compare 2 output Concurrent compare 3 output Concurrent compare 4 output Concurrent compare 5 output Concurrent compare 6 output Concurrent compare 7 output External A/D converter start Serial port 1 receiver data input Serial port 1 transmitter data output Semiconductor Group 6-2 On-Chip Peripheral Components C517A 6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the seven I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P6) activate the "read-latch" signal, while others activate the "read-pin" signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-1 Basic Structure of a Port Circuitry Semiconductor Group 6-3 On-Chip Peripheral Components C517A The output drivers of port 1 to 6 have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1 to 6 the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current ( IIL or ITL). For this reason these ports are called "quasi-bidirectional". Read Latch V VCC DD Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-2 Basic Output Driver Circuit of Ports 1 to 6 Semiconductor Group 6-4 On-Chip Peripheral Components C517A 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1’s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Addr./Data Read Latch Control & VVCC DD =1 Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q MUX Read Pin MCS02434 Figure 6-3 Port 0 Circuitry Semiconductor Group 6-5 On-Chip Peripheral Components C517A 6.1.2.2 Port 1, Port 3 to Port 6 Circuitry The pins of ports 1, 3, 4, 5, and 6 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-1. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Read Latch Alternate Output Function VCC VDD Internal Pull Up Arrangement Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS01827 Read Pin Alternate Input Function Figure 6-4 Ports 1, 3, 4, 5, and 6 Semiconductor Group 6-6 On-Chip Peripheral Components C517A 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-3. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-6) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Addr. Read Latch Control VVCC DD Internal Pull Up Arrangement Port Pin Int. Bus D Bit Latch CLK Q MUX Q =1 Write to Latch Read Pin MCS03228 Figure 6-5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. Semiconductor Group 6-7 On-Chip Peripheral Components C517A Addr. Control VDD VCC Q _