PC100-323-620

3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module 168 pin unbuffered DIMM Modules HYS 64/72V8200GU HYS 64/72V16220GU • 168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications 1 bank 8M × 64, 8M × 72 and 2 bank 16M × 64, 16M × 72 organization Optimized for byte-write non-parity or ECC applications JEDEC standard Synchronous DRAMs (SDRAM) Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification SDRAM Performance -8 -8B 100 6 -10 66 8 Units MHz ns • • • • • fCK tAC • Clock frequency (max.) Clock access time 100 6 Programmed Latencies Product Speed -8 -8B -10 PC100 PC100 PC66 CL 2 3 2 tRCD 2 2 2 tRP 2 3 2 • • Single + 3.3 V (± 0.3 V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E2PROM Utilizes 8M × 8 SDRAMs in TSOPII-54 packages 4096 refresh cycles every 64 ms 133.35 mm × 31.75 mm × 4.00 mm card size with gold contact pads • • • • • • • Semiconductor Group 1 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules The HYS 64(72)8200 and HYS 64(72)16220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 8M × 64, 8M × 72 in 1 bank and 16M × 64 and 16M × 72 in two banks high speed memory arrays designed with 64M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort 8M 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ ( 31.75 mm) height. Ordering Information Type HYS 64V8200GU-8 HYS 72V8200GU-8 HYS 64V16220GU-8 HYS 72V16220GU-8 HYS 64V8200GU-8B Ordering Code Package Descriptions Module Height 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ 1.25“ PC100-222-620 L-DIM-168-30 100 MHz 8M × 64 1 bank SDRAM module PC100-222-620 L-DIM-168-30 100 MHz 8M × 72 1 bank SDRAM module PC100-222-620 L-DIM-168-30 100 MHz 16M × 64 2 bank SDRAM module PC100-222-620 L-DIM-168-30 100 MHz 16M × 72 2 bank SDRAM module PC100-323-620 L-DIM-168-30 100 MHz 8M × 64 1 bank SDRAM module HYS 64V16220GU-8B PC100-323-620 L-DIM-168-30 100 MHz 16M × 64 2 bank SDRAM module HYS 64V8200GU-10 HYS 72V8200GU-10 PC66-222-920 PC66-222-920 L-DIM-168-30 66 MHz 8M × 64 1 bank SDRAM module L-DIM-168-30 66 MHz 8M × 72 1 bank SDRAM module L-DIM-168-30 66 MHz 16M × 64 2 bank SDRAM module L-DIM-168-30 66 MHz 16M × 72 2 bank SDRAM module HYS 64V16220GU-10 PC66-222-920 HYS 72V16220GU-10 PC66-222-920 Semiconductor Group 2 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules Pin Names A0 - A11 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0, CKE1 Address Inputs Bank Selects Data Input/Output Check Bits (× 72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable CLK0 - CLK3 DQMB0 DQMB7 CS0 - CS3 Clock Input Data Mask Chip Select Power (+ 3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection VCC VSS SCL SDA N.C. Address Format Part Number 8M × 64 8M × 72 HYS 64V8200GU HYS 72V8200GU Rows 12 12 12 12 Columns Bank Select 9 9 9 9 2 2 2 2 Refresh 4k 4k 4k 4k Period 64 ms 64 ms 64 ms 64 ms Interval 15.6 µs 15.6 µs 15.6 µs 15.6 µs 16M × 64 HYS 64V16220GU 16M × 72 HYS 72V16220GU Semiconductor Group 3 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS DQ0 DQ1 DQ2 DQ3 VSS DU CS2 DQMB2 DQMB3 DU VSS DQ32 DQ33 DQ34 DQ35 VSS CKE0 CS3 DQMB6 DQMB7 NC VCC DQ4 DQ5 DQ6 DQ7 DQ8 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VCC NC NC NC (CB2) NC (CB3) VCC NC NC CB6 CB7 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VSS DQ16 DQ17 DQ18 DQ19 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ20 NC DU CKE1 VCC DQ52 NC DU NC VCC DQ14 DQ15 NC (CB0) NC (CB1) VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS DQ21 DQ22 DQ23 VSS DQ53 DQ54 DQ55 VSS NC NC VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS DQ24 DQ25 DQ26 DQ27 VCC CAS DQMB4 DQMB5 CS1 RAS VSS DQ56 DQ57 DQ58 DQ59 VCC DQ28 DQ29 DQ30 DQ31 VCC DQ60 DQ61 DQ62 DQ63 VSS A0 A2 A4 A6 A8 A10 BA1 VSS A1 A3 A5 A7 A9 BA0 A11 VSS CLK2 NC WP SDA SCL VSS CLK3 NC SA0 SA1 SA2 VCC VCC CLK0 VCC CLK1 NC VCC VCC Note: Pinnames in brackets are for the x72 ECC versions Semiconductor Group 4 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules WE CS0 DQMB0 DQ(7:0) CS WE DQM DQ0-DQ7 D0 CS WE DQM DQ0-DQ7 D1 CS WE DQM DQ0-DQ7 D8 DQMB4 DQ(39:32) CS WE DQM DQ0-DQ7 D4 CS WE DQM DQ0-DQ7 D5 DQMB1 DQ(15:8) DQMB5 DQ(47:40) CB(7:0) CS2 DQMB2 DQ(23:16) CS WE DQM DQ0-DQ7 D2 CS WE DQM DQ0-DQ7 D3 D0-D7, (D8) D0-D7, (D8) C0-C15, (C16, C17) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) DQMB6 DQ(55:48) CS WE DQM DQ0-DQ7 D6 CS WE DQM DQ0-DQ7 D7 E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47 k Ω DQMB3 DQ(31:24) DQMB7 DQ(63:56) A0-A11, BA0, BA1 VCC VSS RAS CAS CKE0 Clock Wiring 16 M x 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM + 3.3 pF Termination 4 SDRAM + 3.3 pF Termination 16 M x 72 5 SDRAM Termination 4 SDRAM + 3.3 pF Termination SPB03958 Note: D8 is only used in the x72 ECC version. Block Diagram for 8M × 64/72 SDRAM DIMM Modules (HYS 64/72V8200GU) Semiconductor Group 5 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules CS1 CS0 DQMB0 DQ(7:0) CS DQM DQ0-DQ7 D0 CS DQM DQ0-DQ7 D1 CS DQM DQ0-DQ7 D16 CS3 CS2 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 D3 A0-A11, BA0, BA1 D0-D15, (D16, D17) D0-D15, (D16, D17) C0-C31, (C32...C35) D0-D7, (D8) D0-D15, (D16, D17) D0-D7, (D16) Clock Wiring 16 M x 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 16 M x 72 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF SPB03769 CS DQM DQ0-DQ7 D8 CS DQM DQ0-DQ7 D9 CS DQM DQ0-DQ7 D17 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 D5 CS DQM DQ0-DQ7 D12 CS DQM DQ0-DQ7 D13 DQMB1 DQ(15:8) DQMB5 DQ(47:40) CB(7:0) CS DQM DQ0-DQ7 D10 CS DQM DQ0-DQ7 D11 DQMB6 DQ(55:48) CS DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D7 CS DQM DQ0-DQ7 D14 CS DQM DQ0-DQ7 D15 DQMB3 DQ(31:24) DQMB7 DQ(63:56) E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47 k Ω VDD VSS RAS, CAS, WE CKE0 VDD 10 k Ω CKE1 D9-D15, (D17) Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted. Block Diagram for 16M × 64/72 SDRAM DIMM Modules (HYS 64/72V1620GU) Semiconductor Group 6 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = – 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol min. Limit Values max. 2.0 – 0.5 2.4 – – 40 – 40 Unit V V V V µA µA VIH VIL VOH VOL II(L) IO(L) VCC + 0.3 0.8 – 0.4 40 40 Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol max. 8M×64 Input capacitance CI1 (A0 to A11, BA0, BA1, RAS, CAS, WE) Input capacitance (CS0 - CS3) Input capacitance (CLK0 - CLK3) Input capacitance (CKE0, CKE1) Input capacitance (DQMB0 - DQMB7) Input/Output capacitance (DQ0 - DQ63, CB0 - CB7) Input Capacitance (SCL, SA0 - 2) Input/Output capacitance 45 25 35 35 13 10 8 10 Limit Values max. 8M×72 55 25 38 38 13 10 8 10 max. 16M×64 70 25 35 35 20 15 8 10 max. 16M×72 80 30 38 38 20 15 8 10 pF pF pF pF pF pF pF pF Unit CI2 CICL CI3 CI4 CIO CSC CSD Semiconductor Group 7 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules Operating Currents TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V 1 Recommended Operating Conditions unless otherwise noted Parameter & Test Condition Symb. -8/-8B -10 max. Operating Current ICC1 tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open Burst length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharged Standby Current in Power Down Mode CS = VIH(MIN.), CKE ≤ VIL(MAX.) Precharged Standby Current in Non-power Down Mode CS = VIH(MIN.), CKE ≥ VIH(MIN.) No operating current 110 75 mA 1 Unit Note tCK = min. tCK = infinity tCK = min. tCK = infinity CKE ≥ ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P ICC4 2 1 35 5 45 8 70 2 1 30 5 40 8 50 mA mA mA 1 1 1 1 VIH(MIN.) mA mA mA 1 tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Burst operating current tCK = min., Read command cycling Auto refresh current tCK = min., Auto Refresh command cycling Self refresh current Self Refresh Mode, CKE = 0.2 V CKE ≤ VIL(MAX.) 1 – 1, 2 – ICC5 130 90 mA 1 standard version ICC6 1 1 mA 1 Semiconductor Group 8 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules AC Characteristics 3, 4 TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol -8 PC100-222 min. Clock and Clock Enable Clock Cycle Time tCK CAS Latency = 3 CAS Latency = 2 System Frequency fCK CAS Latency = 3 CAS Latency = 2 Clock Access Time tAC CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition Time (rise and fall) Common Parameters RAS to CAS delay Precharge Time Active Command Period Cycle Time Bank to Bank Delay Time CAS to CAS Delay Time (same bank) 10 10 – – – – 3 3 2 1 2.5 8 1 – – 100 100 6 6 – – – – – – – 10 12 – – – – 3 3 2 1 2.5 10 1 – – 100 83 6 7 – – – – – – – 10 15 – – – – 3.5 3.5 3 1 3 8 1 – – 100 66 8 9 – – – – – – – ns ns MHz MHz ns ns ns ns ns ns ns ns ns 4, 5 Limit Values -8B PC100-323 min. max. -10 PC66 min. max. Unit Note max. tCH tCL tCS tCH tCKSP tCKSR tT 6 6 7 7 8 9 tRCD tRP tRAS tRC tRRD tCCD 20 20 50 70 16 1 – – 100k – – – 20 30 60 80 20 1 – – 100k – – – 30 30 70 80 20 1 – – 100k – – – ns ns ns ns ns CLK Semiconductor Group 9 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules AC Characteristics (cont’d)3, 4 TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol -8 PC100-222 min. Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time max. Limit Values -8B PC100-323 min. max. -10 PC66 min. max. Unit Note tREF tSREX – 10 64 – – 10 64 – – 10 64 – ms ns 8 9 tOH 3 0 3 – – – 8 2 3 0 3 – – – 10 2 3 0 3 – – – 10 2 ns ns ns CLK 4 Data Out to Low Impedance tLZ Data Out to High Impedance tHZ DQM Data Out Disable Latency Write Cycle Data input to Precharge (write recovery) Data In to Active/Refresh DQM Write Mask Latency 10 tDQZ tDPL tDAL tDQW 2 5 0 – – – 2 5 0 – – – 2 5 0 – – – CLK CLK CLK Semiconductor Group 10 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules Notes 1. The specified values are valid when addresses are changed no more than once during tCK(MIN.) and when No Operation commands are registered on every rising clock edge during tRC(MIN.). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate between 0.8 V and 2.0 V. . t CH CLOCK 2.4 V 0.4 V t CL t SETUP INPUT tT t HOLD 1.4 V t AC t LZ OUTPUT t AC t OH 1.4 V I/O 50 pF Measurement conditions for tAC and tOH t HZ SPT03404 If clock rising time is longer than 1ns, a time (tT/2 – 0.5) ns has to be added to this parameter. Rated at 1.5 V If tT is longen than 1 ns, a time (tT – 1) ns has to be added to this parameter. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“ the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 5. 6. 7. 8. Semiconductor Group 11 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). SPD-Table for PC100 Modules Byte# Description SPD Entry Value 128 256 SDRAM 12 Hex 8M×64 8M×64 8M×72 16M×64 16M×64 16M×72 -8 -8B -8 -8 -8B -8 80 08 04 0C 80 08 04 0C 80 08 04 0C 80 08 04 0C 80 08 04 0C 80 08 04 0C 0 1 2 3 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for 8M × 8 SDRAMs) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels 4 9 09 09 09 09 09 09 5 6 7 8 9 10 1/2 64/72 0 LVTTL 01 40 00 01 A0 60 01 40 00 01 A0 60 01 48 00 01 A0 60 02 40 00 01 A0 60 02 40 00 01 A0 60 02 48 00 01 A0 60 SDRAM Cycle Time 10.0 ns at CL= 3 SDRAM Access time from Clock at CL = 3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 6.0 ns 11 12 none/ECC 00 00 80 02 80 00 80 00 80 02 80 Self 80 Refresh15. 6 µs ×8 n/a /× 8 08 00 13 14 SDRAM width, Primary Error Checking SDRAM data width 08 00 08 08 08 00 08 00 08 08 Semiconductor Group 12 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules SPD-Table for PC100 Modules (cont’d) Byte# Description SPD Entry Value Hex 8M×64 8M×64 8M×72 16M×64 16M×64 16M×72 -8 -8B -8 -8 -8B -8 01 01 01 01 01 01 15 Minimum clock delay for back-toback random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD tCCD = 1 CLK 16 17 18 1, 2, 4, 8 & full page 4 CAS latency = 2&3 8F 04 06 8F 04 06 8F 04 06 8F 04 06 8F 04 06 8F 04 06 19 20 21 CS 01 latency = 0 Write 01 latency = 0 non buffered/ non reg. 00 01 01 00 01 01 00 01 01 00 01 01 00 01 01 00 22 23 VCC tol ± 10% 10.0/12.0 ns 6.0/7.0 ns 06 A0 06 C0 06 A0 06 A0 06 C0 06 A0 24 60 70 60 60 60 60 25 not supported not supported 20/30 ns 16/20 ns FF FF FF FF FF FF 26 FF FF FF FF FF FF 27 28 14 10 1E 14 14 10 14 10 1E 14 14 10 Semiconductor Group 13 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules SPD-Table for PC100 Modules (cont’d) Byte# Description SPD Entry Value 20 ns 45 ns 64 MByte Hex 8M×64 8M×64 8M×72 16M×64 16M×64 16M×72 -8 -8B -8 -8 -8B -8 14 2D 10 20 10 20 10 FF 14 2D 10 20 10 20 10 FF 14 2D 10 20 10 20 10 FF 14 2D 10 20 10 20 10 FF 14 2D 10 20 10 20 10 FF 14 2D 10 20 10 20 10 FF 29 30 31 32 33 34 35 Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup 2 ns time SDRAM input hold time SDRAM data input hold time SDRAM data input setup time 1 ns 2 ns 1 ns – 62-61 Superset information (may be used in future) 62 63 64125 SPD Revision Checksum for bytes 0 - 62 Manufacturers information (optional) (FFH if not used) Frequency Specification 100 MHz support details Unused storage locations Revision 1.2 – – 12 D8 XX 12 16 XX 12 EA XX 12 D9 XX 12 17 XX 12 EB XX 126 127 128+ 100 MHz – – 64 AF FF 64 AD FF 64 AF FF 64 FF FF 64 FD FF 64 FF FF Semiconductor Group 14 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules SPD-Table for PC66 Modules Byte# Description SPD Entry Value Hex 8M×64 8M×72 16M×64 16M×72 -10 -10 -10 -10 0 1 2 3 4 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access time from Clock at C L= 3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes 128 256 SDRAM 12 9 80 08 04 0C 09 80 08 04 0C 09 80 08 04 0C 09 80 08 04 0C 09 5 6 7 8 9 10 11 12 13 14 15 1/2 64/72 0 LVTTL 10.0 ns 8.0 ns none/ECC Self Refresh 15.6 µs ×8 n/a/×8 01 40 00 01 A0 80 00 80 08 00 01 01 48 00 01 A0 80 02 80 08 08 01 02 40 00 01 A0 80 00 80 08 00 01 02 48 00 01 A0 80 02 80 08 08 01 tCCD = 1 CLK 16 17 18 19 20 21 1, 2, 4, 8 & full page 4 CAS latency = 2 & 3 CS latency = 0 Write latency = 0 non buffered/ non reg. 8F 04 06 01 01 00 8F 04 06 01 01 00 8F 04 06 01 01 00 8F 04 06 01 01 00 Semiconductor Group 15 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules SPD-Table for PC66 Modules (cont’d) Byte# Description SPD Entry Value Hex 8M×64 8M×72 16M×64 16M×72 -10 -10 -10 -10 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL= 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD Minimum RAS to CAS delay VCC tol ± 10% 15.0 ns 9.0 ns not supported not supported 30 ns 20 ns 30 ns 45 ns 64 MByte 3 ns 1 ns 1 ns 06 F0 90 FF FF 1E 14 1E 2D 10 30 10 30 10 FF 06 F0 90 FF FF 1E 14 1E 2D 10 30 10 30 10 FF 12 C2 XX 06 F0 90 FF FF 1E 14 1E 2D 10 30 10 30 10 FF 12 B1 XX 06 F0 90 FF FF 1E 14 1E 2D 10 30 10 30 10 FF 12 C3 XX tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time 3 ns 62-61 Superset information (may be used in future) 62 63 64125 126 127 128+ SPD Revision Checksum for bytes 0 - 62 Manufacturers information (optional) (FFH if not used) Frequency Specification Details Unused storage locations 66 MHz Revision 1.2 12 B0 XX 66 AF FF 66 AF FF 66 FF FF 66 FF FF Semiconductor Group 16 1998-08-01 HYS 64(72)V8200/16220GU-8/-10 SDRAM Modules Package Outlines L-DIM-168-30 SDRAM DIMM Module Package 133.35 127.35 4 ± 0.1 4 31.75 *) 3 1 3 10 1.27 11 6.35 42.18 40 41 6.35 84 1.27± 0.1 91 x 1.27 = 115.57 3.125 85 94 2 95 124 125 168 17.78 *) R1.27 +0.1 3 min. Detail of Contacts 0.2 ± 0.15 2.54 min. 2.26 *) on ECC modules only 1 ± 0.05 1.27 GLD09159 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 17 Dimensions in mm 1998-08-01 4.45 8.25