PSB2115

ICs for Communications ISDN PC Adapter Circuit IPAC PSB 2115 Version 1.1 Data Sheet 11.97 DS 1 PSB 2115 Revision History: Current Version: 11.97 Previous Version: Preliminary Data Sheet 03.97 Page Page (in previous (in new Version) Version) Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http://www.siemens.de/Semiconductor/address/address.htm. Edition 11.97 Published by Siemens AG, HL TS, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PSB 2115 PSF 2115 Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.7.1 2.1.7.2 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.4.1 2.3.4.2 2.3.4.3 2.3.4.4 2.3.4.5 2.3.5 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 B-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Non-Auto Mode (MODEB: MDS1, MDS0 = 01) . . . . . . . . . . . . . . . . . . . . . . .32 Transparent Mode 1 (MODEB: MDS1, MDS0, ADM = 101) . . . . . . . . . . . . .33 Transparent Mode 0 (MODEB: MDS1, MDS0, ADM = 100) . . . . . . . . . . . . .33 Extended Transparent Modes 0, 1 (MODEB: MDS1, MDS0 = 11) . . . . . . . .33 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Clock Mode 5 (Time-Slots) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Fully Transparent Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . .39 Cyclic Transmission (Fully Transparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Continuous Transmission (DMA Mode only) . . . . . . . . . . . . . . . . . . . . . . . . .40 Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Data Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 D-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Layer-2 Functions for HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Reception of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Transmission of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Activation Initiated by Exchange (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Activation Initiated by Terminal (TE/LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 TIC Bus D-Channel Control in TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .56 S-Bus D-channel Control in TEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 D-Channel Control in the Intelligent NT (TIC- and S-Bus) . . . . . . . . . . . . . . .59 IOM-2 Interface Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3 11.97 Semiconductor Group PSB 2115 PSF 2115 Table of Contents 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.5 2.5.1 2.5.2 2.5.2.1 2.5.2.2 2.5.3 2.5.3.1 2.5.3.2 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.5.9 2.5.9.1 2.5.9.2 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.7 2.7.1 2.7.2 2.7.3 Page S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 S/T Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 MON-8 Commands (Internal Register Access) . . . . . . . . . . . . . . . . . . . . . . .72 MON-8 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 MON-8 Loop-Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 MON-8 IOM-2 Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 MON-8 SM/CI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Layer-1 Functions for the S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 S/T Interface Pre-Filter Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Receiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Level Detection Power Down (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 S/T Transmitter Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Terminal Specific Functions (TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . .94 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 B-Channel Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 D-Channel and S/T Interface Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 FIFO Structure for B-Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 IOM-2 Frame Structure / Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 IOM-2 Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Microprocessor Access to B and IC Channels . . . . . . . . . . . . . . . . . . . . . . .125 4 11.97 Semiconductor Group PSB 2115 PSF 2115 Table of Contents 2.7.4 2.7.4.1 2.7.4.2 2.7.4.3 2.7.4.4 2.7.5 2.7.6 2.8 2.8.1 2.8.2 2.8.2.1 2.8.2.2 2.8.2.3 2.9 Page MONITOR Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Monitor Procedure Timeout (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 MON-1, MON-2 Commands (S/Q Channel Access) . . . . . . . . . . . . . . . . . .137 MON-8 Commands (Register Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 C/I-Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 TIC Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Mode Dependent Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 PCM Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Switching of Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.6.3.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 B-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 D-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 B-Channel Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 D-Channel Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 HDLC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 HDLC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . .188 Activation/Deactivation of S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 State Machine TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 TE/LT-T Modes State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 5 11.97 Semiconductor Group PSB 2115 PSF 2115 Table of Contents 3.6.3.2 3.6.4 3.6.4.1 3.6.4.2 3.6.4.3 3.6.4.4 3.6.5 3.6.5.1 3.6.5.2 3.6.5.3 3.6.5.4 3.6.6 3.6.7 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 4.2.19 4.2.20 4.2.21 4.2.22 4.2.23 Page TE/LT-T Modes Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 LT-S Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 LT-S Mode Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Transmitted Signals and Indications in LT-S Mode . . . . . . . . . . . . . . . . . . .204 States LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 State Machine Intelligent NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Intelligent NT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Intelligent NT Mode Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Transmitted Signals and Indications in Intelligent NT Mode . . . . . . . . . . . .208 States Intelligent NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Command/Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 B-Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 RFIFOB - Receive FIFO B-Channel (Read)) . . . . . . . . . . . . . . . . . . . . . . . .218 XFIFOB - Transmit FIFO B-Channel (WRITE)) . . . . . . . . . . . . . . . . . . . . . .219 ISTAB - Interrupt Status Register for B-Channel (READ) . . . . . . . . . . . . . .220 MASKB - Mask Register for B-Channel (WRITE) . . . . . . . . . . . . . . . . . . . .220 STARB - Status Register for B-Channel (READ) . . . . . . . . . . . . . . . . . . . . .221 CMDRB - Command Register for B-Channel (WRITE) . . . . . . . . . . . . . . . .222 MODEB - Mode Register for B-Channel (READ/WRITE) . . . . . . . . . . . . . .223 EXIRB - Extended Interrupt Register for B-Channel (READ) . . . . . . . . . . . .225 RBCLB - Receive Byte Count Low for B-Channel (READ) . . . . . . . . . . . . .226 RAH1 - Receive Address Byte High Register 1 (WRITE) . . . . . . . . . . . . . .226 RAH2 - Receive Address Byte High Register 2 (WRITE) . . . . . . . . . . . . . .226 RSTAB - Receive Status Register for B-Channel (READ) . . . . . . . . . . . . . .227 RAL1 - Receive Address Byte Low Register 1 (READ/WRITE) . . . . . . . . . .229 RAL2 - Receive Address Byte Low Register 2 (WRITE) . . . . . . . . . . . . . . .229 RHCRB - Receive HDLC Control Register for B-Channel (READ) . . . . . . .230 XBCL - Transmit Byte Count Low (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . .230 CCR2 - Channel Configuration Register 2 (READ/WRITE) . . . . . . . . . . . . .231 RBCHB - Received Byte Count High for B-Channel (READ) . . . . . . . . . . . .232 XBCH - Transmit Byte Count High (WRITE) . . . . . . . . . . . . . . . . . . . . . . . .232 RLCR - Receive Length Check Register (WRITE) . . . . . . . . . . . . . . . . . . . .233 CCR1 - Channel Configuration Register 1 (READ/WRITE) . . . . . . . . . . . . .234 TSAX - Time-Slot Assignment Register Transmit (WRITE) . . . . . . . . . . . . .234 TSAR - Time-Slot Assignment Register Receive (WRITE) . . . . . . . . . . . . .235 6 11.97 Semiconductor Group PSB 2115 PSF 2115 Table of Contents Page 4.2.24 XCCR - Transmit Channel Capacity Register (WRITE) . . . . . . . . . . . . . . . .235 4.2.25 RCCR - Receive Channel Capacity Register (WRITE) . . . . . . . . . . . . . . . .235 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 4.3.16 4.3.17 4.3.18 4.3.19 4.3.20 4.3.21 4.3.22 4.3.23 4.3.24 4.3.25 4.3.26 4.3.27 4.3.28 4.3.29 4.3.30 4.3.31 4.3.32 4.3.33 4.3.34 4.3.35 4.3.36 4.3.37 4.3.38 D-Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 RFIFOD - Receive FIFO D-Channel (Read) . . . . . . . . . . . . . . . . . . . . . . . .236 XFIFOD - Transmit FIFO D-Channel (Write) . . . . . . . . . . . . . . . . . . . . . . . .236 ISTAD - Interrupt Status Register D-Channel (Read) . . . . . . . . . . . . . . . . .237 MASKD - Mask Register D-Channel (Write) . . . . . . . . . . . . . . . . . . . . . . . .238 STARD - Status Register D-Channel (Read) . . . . . . . . . . . . . . . . . . . . . . . .239 CMDRD - Command Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 MODED - Mode Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 TIMR1 - Timer 1 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 EXIRD - Extended Interrupt Register (Read) . . . . . . . . . . . . . . . . . . . . . . . .245 XAD1 - Transmit Address 1 (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 XAD2 - Transmit Address 1 (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 RBCLD - Receive Frame Byte Count Low for D-Channel (Read) . . . . . . . .248 SAPR - Received SAPI Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . .249 SAP1 - SAPI1 Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 SAP2 - SAPI2 Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 RSTAD - Receive Status Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . .250 TEI1 - TEI1 Register 1 (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 TEI2 - TEI2 Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 RHCRD - Receive HDLC Control Register for D-Channel (Read) . . . . . . . .253 RBCHD - Receive Frame Byte Count High for D-Channel (Read) . . . . . . .254 STAR2 - Status Register 2 (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 SPCR - Serial Port Control Register (Read/Write) . . . . . . . . . . . . . . . . . . . .256 CIR0 - Command/Indication Receive 0 (Read) . . . . . . . . . . . . . . . . . . . . . .258 CIX0 - Command/Indication Transmit 0 (Write) . . . . . . . . . . . . . . . . . . . . . .259 MOR0 - MONITOR Receive Channel 0 (Read) . . . . . . . . . . . . . . . . . . . . . .260 MOX0 - MONITOR Transmit Channel 0 (Write) . . . . . . . . . . . . . . . . . . . . . .260 CIR1 - Command/Indication Receive 1 (Read) . . . . . . . . . . . . . . . . . . . . . .260 CIX1 - Command/Indication Transmit 1 (Write) . . . . . . . . . . . . . . . . . . . . . .261 MOR1 - MONITOR Receive Channel 1 (Read) . . . . . . . . . . . . . . . . . . . . . .261 MOX1 - MONITOR Transmit Channel 1 (Write) . . . . . . . . . . . . . . . . . . . . . .261 C1R - Channel Register 1 (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 C2R - Channel Register 2 (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 STCR - Synchronous Transfer Control Register (Write) . . . . . . . . . . . . . . .263 B1CR - B1 Channel Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 B2CR - B2 Channel Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 ADF1 - Additional Feature Register 1 (Write) . . . . . . . . . . . . . . . . . . . . . . .265 MOSR - MONITOR Status Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . .266 MOCR - MONITOR Control Register (Write) . . . . . . . . . . . . . . . . . . . . . . . .267 7 11.97 Semiconductor Group PSB 2115 PSF 2115 Table of Contents 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.4.12 4.4.13 5 6 7 7.1 7.2 7.3 7.4 Page General IPAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 CONF - IPAC Configuration Register (Read/Write) . . . . . . . . . . . . . . . . . . .268 ISTA - IPAC Interrupt Status Register (Read) . . . . . . . . . . . . . . . . . . . . . . .270 MASK - IPAC Mask Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 ID - Identification Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 ACFG - Auxiliary Interface Configuration (Read/Write) . . . . . . . . . . . . . . . .272 AOE - Auxiliary Output Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . .273 ARX - Auxiliary Interface Receive Register (Read) . . . . . . . . . . . . . . . . . . .273 ATX - Auxiliary Interface Transmit Register (Write) . . . . . . . . . . . . . . . . . . .274 PITA1/2 - PCM Input Time Slot Assignment B1/B2 (Read/Write) . . . . . . . .274 POTA1/2 - PCM Output Time Slot Assignment B1/B2 (Read/Write) . . . . . .275 PCFG - PCM Configuration Register (Read/Write) . . . . . . . . . . . . . . . . . . .276 SCFG - SDS Configuration Register (Read/Write) . . . . . . . . . . . . . . . . . . .277 TIMR2 - Timer 2 Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 MON-8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI® , ARCOFI®-BA, ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®, SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Siemens AG. MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, ASM™, ASP™, DigiTape™ are trademarks of Siemens AG. Semiconductor Group 8 11.97 PSB 2115 PSF 2115 List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Page Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ISDN PC Adapter Card for S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ISDN PC Adapter Card for U or S interface . . . . . . . . . . . . . . . . . . . . . . . 28 ISDN Voice/Data Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ISDN Stand-Alone Terminal with POTS interface . . . . . . . . . . . . . . . . . . 30 Multiline PC-Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Receive Data Flow of IPAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Transmit Data Flow of IPAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Location of Time-Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 NRZ Encoding/NRZI Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Contents of RFIFOD (short message) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Contents of RFIFOD (long message) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 D-Channel Access Control on TIC Bus and S Bus. . . . . . . . . . . . . . . . . . 54 Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . . . . 63 Intelligent NT-Configuration for IOM-2 Channel Switching. . . . . . . . . . . . 65 Data Path Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 S/T -Interface Line Code (without code violation). . . . . . . . . . . . . . . . . . . 69 Frame Structure at Reference Points S and T (ITU I.430) . . . . . . . . . . . . 70 Wiring Configurations in User Premises. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Connection of the Line Transformers and Power Supply to the IPAC . . . 82 Equivalent Internal Circuits of Receiver and Transmitter Stages . . . . . . . 83 External Circuitry for Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 External Circuitry for Symmetrical Receivers . . . . . . . . . . . . . . . . . . . . . . 86 Receiver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Receiver Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Clock System of the IPAC in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90 Clock System of the IPAC in TE and LT-T Modes . . . . . . . . . . . . . . . . . . 91 ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Layer 2 Test Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 High and Low Active Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 IPAC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Timing Diagram for DMA-Transfers (fast) Transmit (n < 64, remainder of a long message or n = k × 64) 104 Semiconductor Group 9 11.97 PSB 2115 PSF 2115 List of Figures Page 105 105 106 106 106 108 109 110 111 112 113 114 115 116 118 120 121 123 124 126 126 129 131 134 136 140 141 142 144 147 148 149 150 150 151 152 154 11.97 Figure 41: Timing Diagram for DMA-Transfers (slow) Transmit (n < 64, remainder of a long message or n = k × 64) Figure 42: Timing Diagram for DMA-Transfer (fast) Receive (n = k × 64) . . . . . . . . Figure 43: Timing Diagram for DMA-Transfers (slow) Receive (n = k × 64) . . . . . . Figure 44: Timing Diagram for DMA-Transfers (slow or fast) Receive (n = 4, 8, 16 or 32) Figure 45: DMA-Transfers with Pulsed DACK (read or write) . . . . . . . . . . . . . . . . . Figure 46: Configuration of RFIFOB (Long Frames) . . . . . . . . . . . . . . . . . . . . . . . . Figure 47: Configuration of RFIFOB (Short Frames). . . . . . . . . . . . . . . . . . . . . . . . Figure 48: Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 49: Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 50: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 51: Channel Structure of IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 52: Multiplexed Frame Structure of the IOM-2 Interface in Non-TE Timing Mode Figure 53: Definition of IOM-2 Channels in Terminal Timing Mode . . . . . . . . . . . . . Figure 54: Data Strobe Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 55: IOM-2 Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 56: IOM-2 Data Ports DU/DD in Terminal Mode (MODE0=0) . . . . . . . . . . . Figure 57: IOM-2 Data Ports DU/DD in LT-T Mode (MODE0=1, MODE1=1) . . . . . Figure 58: IOM-2 Data Ports DU/DD in LT-S Mode (MODE0=1, MODE1=0) with Normal Layer 2 Direction (SPCR:SDL=1) Figure 59: IOM-2 Data Ports DU/DD in LT-S Mode (MODE0=1, MODE1=0) with Inversed Layer 2 Direction (SPCR:SDL=0) Figure 60: Principle of B/IC Channel Access in IOM-2 Terminal Mode . . . . . . . . . . Figure 61: Access to B and IC Channels in IOM-2 Terminal Mode . . . . . . . . . . . . . Figure 62: Examples of MONITOR Channel Applications in IOM-2 TE Mode. . . . . Figure 63: MONITOR Channel Protocol (IOM-2). . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 64: Handshake Protocol with a 2-Byte Monitor Message/Response . . . . . . Figure 65: Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . . Figure 66: Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . . . Figure 67: Structure of Last Octet of Ch2 on DU. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 68: Structure of Last Octet of Ch2 on DD. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 69: Input/Output Characteristic of AUX Pins . . . . . . . . . . . . . . . . . . . . . . . . Figure 70: PCM Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 71: PCM Bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 72: Switching Data between PCM and IOM-2 . . . . . . . . . . . . . . . . . . . . . . . Figure 73: Data Path Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 74: Generation of FSC and BCL in LT-T mode . . . . . . . . . . . . . . . . . . . . . . Figure 75: Multiline Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 76: Switching of PCM Timeslots on IOM-2 Channel B1 . . . . . . . . . . . . . . . . Figure 77: Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Group 10 PSB 2115 PSF 2115 List of Figures Page 163 172 175 176 177 178 179 181 182 183 185 186 189 190 192 194 195 202 206 212 213 279 280 284 285 286 286 286 287 287 287 288 289 290 291 292 293 294 295 297 298 Figure 78: IPAC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 79: a) CIC Interrupt Structure b) MOS Interrupt Structure Figure 80: Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . . . Figure 81: Interrupt Driven Transmission Sequence Example . . . . . . . . . . . . . . . . Figure 82: Continuous Frames Transmission (Flow Diagram) . . . . . . . . . . . . . . . . Figure 83: Continuous Frames Transmission Sequence Example . . . . . . . . . . . . . Figure 84: DMA Driven Transmission Sequence Example . . . . . . . . . . . . . . . . . . . Figure 85: Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . . . Figure 86: DMA Driven Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . Figure 87: Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 88: Transmission of an I Frame in the D Channel (Subscriber to Exchange) Figure 89: Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 90: Deactivation of the IOM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 91: Activation of the IOM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 92: State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 93: State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . Figure 94: State Diagram of the TE/LT-T Modes, Unconditional Transitions . . . . . Figure 95: State Transition Diagram in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . Figure 96: NT Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 97: Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 98: Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 99: Test Condition for Maximum Input Current. . . . . . . . . . . . . . . . . . . . . . . Figure 100:Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 101:Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 102:Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 103:Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 104:Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 105:Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 106:Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 107:Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 108:Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 109:Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 110:IOM Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 111:IOM Timing (LT-S, LT-T mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 112:PCM Interface Timing (LT-S, LT-T mode) . . . . . . . . . . . . . . . . . . . . . . . Figure 113:BCL, FSC Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 114:AUX Interface I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 115:Phase Relationships of IPAC Clock Signals. . . . . . . . . . . . . . . . . . . . . . Figure 116:Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 117:Block Diagram of XPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 118:Reset Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Group 11 11.97 PSB 2115 PSF 2115 List of Figures Page 311 312 313 314 Figure 119:State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . Figure 120:State Diagram of the TE/LT-T Modes, Unconditional Transitions . . . . . Figure 121:State Transition Diagram in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . Figure 122:NT Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Group 12 11.97 PSB 2115 PSF 2115 List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Page Programming of Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 IPAC Configuration Settings in Intelligent NT Applications . . . . . . . . . . . .60 Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Multiframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 MON-8 “Write to Register” Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 MON-8 “Read Register Request” Structure . . . . . . . . . . . . . . . . . . . . . . . .73 MON-8 “Read Response” Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DU/DD Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Bus Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Auxiliary Interface Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 D-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 B-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 mP Access to B/IC Channels (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AUX Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 IOM-2 Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 RESET Values for B-Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .155 RESET Values for D-Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .156 RESET Values for General IPAC Registers . . . . . . . . . . . . . . . . . . . . . . .157 Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 User Demand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Receive Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Transmit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Interrupts from D-Channel HDLC Controller. . . . . . . . . . . . . . . . . . . . . . .168 Auxiliary Interface Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Status Information after RME Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . .180 IOM-2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 Reset Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 DU/DD Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 Semiconductor Group 13 11.97 PSB 2115 PSF 2115 Overview 1 Overview The ISDN PC Adapter Circuit IPAC integrates all necessary functions for a host based ISDN access solution on a single chip. It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two protocol controllers for each B-channel. They can be used for HDLC protocol or transparent access. The system integration is simplified by several host interface configurations selected via pin strapping. They include multiplexed and demultiplexed interface options as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The IPAC combines the functions of the ISDN Subscriber Access Controller (ISAC-S PEB 2086) and the High-Level Serial Communications Controller Extended for Terminals (HSCX-TE PSB 21525) providing additional features and enhanced functionality. The FIFO size of the B-channel buffers is 2x64 bytes per channel and per direction. The S-transceiver supports other terminal relevant operation modes like line termination subscriber side (LT-S) and line termination trunk side (LT-T). A multi-line ISDN solution to support both S and U (2B1Q) line coding is simplified as well as multi-line solution with up to 3 S-interfaces. An auxiliary I/O port has been added with interrupt capabilities on two input lines. These programmable I/O lines may be used to connect a DTMF receiver or other peripheral components to the IPAC which need software control or have to forward status information to the host. Peripheral data controllers can transfer data on a PCM interface which is mapped into the B-channels on the IOM-2 interface. Three programmable LED outputs can be used to indicate certain status information, one of them is capable to indicate the activation status of the S-interface automatically. The IPAC is produced in advanced CMOS technology. Semiconductor Group 14 11.97 ISDN PC Adapter Circuit IPAC PSB 2115 PSF 2115 Version 1.1 1.1 Features CMOS • Single chip host based ISDN solution • Integrates S-transceiver, D-channel, B-channel protocol controller • Replaces solutions based on ISAC-S TE PSB 2186 and HSCX-TE PSB 21525 • Easy adjustment of software using ISAC-S and HSCX-TE P-MQFP-64 • Various types of protocol support depending on operating mode (Non-auto mode, transparent mode) • Efficient transfer of data blocks from/to system memory by DMA or interrupt request • Enlarged FIFO buffers (2x64 byte) per B-channel and per direction • S-transceiver with TE, LT-S and LT-T modes • D-channel FIFO buffers with 2x32byte P-TQFP-64 • D-channel access mechanism in all modes • D-channel priority handler on IOM-2 for intelligent NT applications • Software reset (required for Windows95) • Programmable I/O interface with 2 interrupt inputs • PCM interface for non IOM-2 compatible peripheral data controllers • Programmable timer (1 ... 63 ms) for continuous or single interrupts • Reduced register address space due to indirect address mode option • 3 programmable LED outputs, one can indicate S bus activation status automatically • 8-bit multiplexed or demultiplexed bus interface • Siemens/Intel or Motorola µP interface Semiconductor Group 15 11.97 PSB 2115 PSF 2115 Overview 1.2 Logic Symbol The logic symbol shows all functions of the IPAC. It must be noted, that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are multiplexed and not available in all modes. Figure 1 Logic Symbol Semiconductor Group 16 11.97 PSB 2115 PSF 2115 Overview 1.3 Pin Configuration Figure 2 shows the pin configuration for P-MQFP-64 and for P-TQFP-64 packages. XTAL1 XTAL2 AMOD VDDA VSSA VDD BCL / SCLK DU DD FSC DCL VSS MODE0 MODE1 / EAW ACL SDS AUX7 AUX6 AUX5 AUX4 AUX3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 50 51 52 53 54 55 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 VDD AUX2 C768 RES VSS SR1 SR2 SX2 SX1 TP TP TP AUX1 AUX0 DACKB DACKA DRQRB DRQTB VDD A7 A6 A5 A4 A3 A2 A1 A0 VSS 56 57 58 59 60 61 62 63 64 2 INT 3 ALE 4 CS 5 WR / R/W 67 RD / DS VSS 8 9 10 11 12 13 14 15 16 VDD 17 AD0 / D0 AD1 / D1 AD2 / D2 AD3 / D3 AD4 / D4 AD5 / D5 AD6 / D6 Figure 2 Pin Configuration Semiconductor Group 17 AD7 / D7 11.97 PSB 2115 PSF 2115 Overview 1.4 Pin Definitions and Functions Pin No. Symbol Input (I) Function Output (O) Microprocessor Interface 8 9 10 11 13 14 15 16 18 19 20 21 22 23 24 25 6 AD0-7 I/O Multiplexed Bus Mode: Address/data bus Transfers addresses from the host system to the IPAC and data between the host system and the IPAC. Non-Multiplexed Bus Mode: Data bus. Transfers data between the host system and the IPAC. Non-Multiplexed Bus Mode: Address bus transfers addresses from the host system to the IPAC. For indirect address mode only A0 is valid. Multiplexed Bus Mode Not used in multiplexed bus mode. In this case A0-A7 should directly be connected to VDD. D0...7 I/O A0-A7 I RD I DS I Read Indicates a read access to the registers (Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). Write Indicates a write access to the registers (Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). Chip Select A LOW on this line selects the IPAC for a read/write operation. 5 WR I R/W I 4 CS I Semiconductor Group 18 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 3 ALE I Address Latch Enable A HIGH on this line indicates an address on the external address/data bus (multiplexed bus type only). ALE also selects the microprocessor interface type (multiplexed or non multiplexed). Interrupt Request This low active signal is activated when the IPAC requests an interrupt. It is an open drain output. DMA Request Transmitter (channel B) The transmitter of the IPAC requests DMA data transfer by activating this line. The DRQTB remains HIGH as long as the transmit FIFO requires data transfer. The amount of data bytes to be transferred from system memory to the IPAC (= byte count) must be written first to the XBCH, XBCL register. Always blocks of data (n x 64 bytes + REST, n=0, 1, ..) are transferred till the byte count is reached. DRQTB is deactivated immediately following the falling edge of the last WR cycle. Note: To support DMA for channel A, the DRQTA line is available in TE mode only (see pin AUX0). DMA Request Receiver (channel B) The receiver of the IPAC requests DMA data transfer by activating this line. The DRQRB remains HIGH as long as the receive FIFO requires data transfer, thus always blocks of data (64, 32, 16, 8 or 4 bytes) are transferred. DRQRB is deactivated immediately following the falling edge of the last read cycle. Note: To support DMA for channel A, the DRQRA line is available in TE mode only (see pin AUX1). 2 INT OD 27 DRQTB O 28 DRQRB O Semiconductor Group 19 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 29 30 DACKA I DACKB DMA Acknowledge (channel A/B) When LOW, this input signal from the DMA controller indicates to the IPAC, that the requested DMA cycle controlled via DRQTA/B and DRQRA/B is in progress, i.e. the DMA controller has achieved bus mastership from the CPU and will start data transfer cycles (either read or write). Together with RD, if DMA has been requested from the receiver, or with WR, if DMA has been requested from the transmitter, this input works like CS to enable a data byte to be read from or written to the top of the receive or transmit FIFO of the specified channel. If DACKA/B is active, the input on pins A0-7 is ignored and the FIFO’s are implicitly selected. If the DACKA/B signals are not used, these pins must be connected to VDD. Auxiliary Interface 31 AUX0 I/O Auxiliary Port 0 TE-Mode: DRQTA (output) DMA Request Transmitter (channel A) The transmitter of the IPAC requests DMA data transfer by activating this line. The DRQTA remains HIGH as long as the transmit FIFO requires data transfer. The amount of data bytes to be transferred from system memory to the IPAC (= byte count) must be written first to the XBCH, XBCL register. Always blocks of data (n x 64 bytes + REST, n=0, 1, ..) are transferred till the byte count is reached. DRQTA is deactivated immediately following the falling edge of the last WR cycle. LT-T/LT-S Mode: CH0 (input) IOM-2 Channel Select 0 Together with CH1 (pin AUX1) and CH2 (pin AUX2), this pin selects one of eight channels on the IOM-2 interface. Semiconductor Group 20 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 32 AUX1 I/O Auxiliary Port 1 TE-Mode: DRQRA (output) DMA Request Receiver (channel A) The receiver of the IPAC requests DMA data transfer by activating this line. The DRQRA remains HIGH as long as the receive FIFO requires data transfer, thus always blocks of data (64, 32, 16, 8 or 4 bytes) are transferred. DRQRA is deactivated immediately following the falling edge of the last read cycle. LT-T/LT-S Mode: CH1 (input) IOM-2 Channel Select 1 Together with CH0 (pin AUX0) and CH2 (pin AUX2), this pin selects one of eight channels on the IOM-2 interface. Auxiliary Port 2 TE-Mode: AUX2 (input) This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. TE-Mode: INT (output) This high active signal is activated when the IPAC requests an interrupt (invers polarity of INT line). LT-T/LT-S Mode: CH2 (input) IOM-2 Channel Select 2 Together with CH0 (pin AUX0) and CH1 (pin AUX1), this pin selects one of eight channels on the IOM-2 interface. 33 AUX2 I/O Semiconductor Group 21 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 64 AUX3 I/O Auxiliary Port 3 TE-Mode: AUX3 (input/output) This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. LT-T/LT-S Mode: FBOUT (output) FSC/BCL Output This pin is programmable to output either an FSC clock which is derived from the DCL input divided by 192 (in LT-T: SCLK output provides 1.536 MHz) or a single bit clock from the IOM-2 interface, especially to serve non IOM-2 compatible peripheral devices on the PCM interface. Auxiliary Port 4 TE-Mode: AUX4 (input/output) This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. LT-T/LT-S Mode: PCMIN (input) PCM Data Input On this line the IPAC receives 8-bit data, which is transmitted from a peripheral device. This data is mapped to a B-Channel timeslot on IOM-2. Auxiliary Port 5 TE-Mode: AUX5 (input/output) This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. LT-T/LT-S Mode: PCMOUT (output) PCM Data Output On this line the IPAC transmits 8-bit data, which is received by a peripheral device. This data is taken from a B-Channel timeslot on IOM-2. 63 AUX4 I/O 62 AUX5 I/O Semiconductor Group 22 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 61 60 AUX6 AUX7 I/O Auxiliary Port 6/7 All Modes: INT0/1 This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. Additionally, as input they can generate a maskable interrupt to the host, which is either edge or level triggered. An internal pull up resistor is connected to these pins. As outputs an LED can directly be connected to these pins. LT-T mode: AUX7 can also be programmed to output the S/G bit signal from the IOM-2 DD line (LT-T mode only). IOM-2 Interface 53 FSC I/O Frame Sync Synchronisation signal. The rising edge indicates the beginning of the IOM frame (HIGH during channel 0 in TE mode). Data Clock IOM clock signal of twice the IOM data rate. The first rising edge is used to transmit data, the second falling edge is used to sample data. Data Upstream IOM data signal in upstream direction. Data Downstream IOM data signal in downstream direction. Bit Clock/S-clock TE-Mode: Bit clock output, identical to IOM data rate. LT-T Mode: 1.536 MHz output synchronous to S-interface. LT-S Mode: Bit clock output derived from the DCL input clock divided by 2. 54 DCL I/O 51 52 50 DU DD BCL/ SCLK I/O(OD) I/O (OD) O Semiconductor Group 23 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 59 SDS O Serial Data Strobe Programmable strobe signal, selecting either one or two channels (8 or 16 bit strobe length) on the IOM-2 or PCM interface. Miscellaneous 34 RES I/O Reset A HIGH on this input forces the IPAC into a reset state. The minimum pulse length is four DCL-clock periods or four ms (see table 29). If the terminal specific functions are enabled, the IPAC may also supply a reset signal. Address Mode Selects between direct and indirect register access. A HIGH selects indirect address mode and a LOW selects the direct register access. Mode 0 Select A LOW selects TE-mode and a HIGH selects LT-T and LT-S mode (see MODE1/EAW). Mode 1 Select / External Awake The pin function depends on the setting of MODE0. If MODE0=1: Mode 1 Select A LOW selects LT-S mode and a HIGH selects LT-T mode. If MODE0=0: External Awake If a falling edge on this input is detected, the IPAC generates an interrupt and, if enabled, a reset pulse. Activation LED This pin can either function as a programmable output or automatically indicate the activated state of the S interface by a logic ’0’. An LED with pre-resistance may directly be connected to ACL. S-Bus Transmitter Output Differential output for the S-transmitter. positive negative 35 AMODE I 56 MODE0 I 57 MODE1 I EAW I 58 ACL O 47 48 SX1 SX2 O O Semiconductor Group 24 11.97 PSB 2115 PSF 2115 Overview Pin No. Symbol Input (I) Function Output (O) 45 44 41 SR1 SR2 XTAL1 I I I S-Bus Receiver Input Differential inputs for the S-receiver. Oscillator Input Input pin of oscillator or input from external clock source. 7.68 MHz crystal or clock required. Oscillator Output Output pin of oscillator. Not connected if external clock source is used. Clock Output A 7.68 MHz clock is output to support other devices, e.g. further IPACs in a multiline application. This clock is not synchronous to the S interface. Test Pins. These pins are not used for normal operation. They must be connected to GND. 42 XTAL2 O 40 C768 O 36 37 38 TP I Power Supply 1 12 26 49 43 7 17 39 55 46 VDD I Digital Supply Voltage +5V (+/- 5%) VDDA VSS I I Analog Supply voltage +5V (+/- 5%) Digital GND VSSA I Analog GND Semiconductor Group 25 11.97 PSB 2115 PSF 2115 Overview 1.5 Functional Block Diagram Figure 3 Block Diagram Semiconductor Group 26 11.97 PSB 2115 PSF 2115 Overview 1.6 System Integration The IPAC is suited for all host based applications. ISDN PC Adapter Card for S Interface An ISDN adapter card for a PC is built around the IPAC using a USB, PCI or PnP interface device depending on the PC interface (figure 4). The IPAC can be connected to any bus interface logic and since it provides the possibility of a one-device terminal architecture, interfacing directly to the printer port applications is rather easy. IPAC PSB 2115 S Interface Interface Logic (USB, PCI, Plug and Play, ISA Bus, Parallel Printer Port) Host Interface 2115_12 Figure 4 ISDN PC Adapter Card for S Interface Semiconductor Group 27 11.97 PSB 2115 PSF 2115 Overview ISDN PC Adapter Card for U or S Interface An ISDN adapter card which supports both U and S interface may be realized using the IPAC together with the PSB 21910 IEC-Q TE ( figure 5). The S interface may be configured for TE or LT-S mode supporting intelligent NT configurations. IOM-2 S Interface * IPAC PSB 2115 IEC-Q TE PSB 20911 U Interface Interface Logic (USB, PCI, Plug and Play, ISA Bus) Host Interface * optional for NT applications 2115_13 Figure 5 ISDN PC Adapter Card for U or S interface Semiconductor Group 28 11.97 PSB 2115 PSF 2115 Overview ISDN Voice/Data Terminal Figure 6 shows a voice data terminal developed on a PC card, where the IPAC provides its functionality as data controller + S interface within a two chip solution. During ISDN calls the ARCOFI-SP PSB 2163 provides for speakerphone functions and includes a DTMF generator. Additionally, a DTMF receiver or keypad may be connected to the auxiliary interface of the IPAC (LT-T mode). ARCOFI-SP PSB 2163 IOM-2 DTMF Receiver or Keypad AUX IPAC PSB 2115 S Interface Interface Logic (USB, PCI, Plug and Play, ISA Bus) Host Interface 2115_14 Figure 6 ISDN Voice/Data Terminal Semiconductor Group 29 11.97 PSB 2115 PSF 2115 Overview ISDN Stand-alone Terminal with POTS interface The IPAC (LT-T mode) can be integrated in a microcontroller based stand-alone terminal (figure 7) that is connected to the communications interface of a PC. The SICOFI2-TE PSB 2132 enables connection of analog terminals (e.g. telephones or fax) to the dual channel POTS interface. POTS SICOFI2-TE PSB 2132 SLIC SLIC IOM-2 DTMF Receiver or Keypad AUX IPAC PSB 2115 S Interface Microcontroller V.24 Interface PC Interface Figure 7 ISDN Stand-Alone Terminal with POTS interface Semiconductor Group 30 11.97 PSB 2115 PSF 2115 Overview Multiline PC-Adapter Up to three S-interfaces can be combined using one IOM interface (figure 8). All three IPACs are configured for LT-T mode in different channels. The SCLK output is used for DCL clock and the FSC clock is generated by one device. Only one 7.68 MHz crystal is required for the three IPACs as they provide a buffered output clock derived from the XTAL1 clock input. PCM IOM-2 IPAC PSB 2115 Data Controller IPAC PSB 2115 3xS Interface IPAC PSB 2115 Interface Logic (USB, PCI, Plug and Play, ISA Bus) Host Interface 2115_15 Figure 8 Multiline PC-Adapter Semiconductor Group 31 11.97 PSB 2115 PSF 2115 Functional Description 2 Functional Description The ISDN PC Adapter Circuit IPAC replaces solutions which are based on ISAC-S TE PSB 2186 and HSCX-TE PSB 21525. Most of the functions of both devices are integrated on the IPAC with further modifications and improvements on certain features. Therefore the functional and operational description is quite similar to these devices. 2.1 B-Channel Operation The HDLC controller of each channel can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be effected in a very flexible way, which satisfies most requirements. There are 4 different operating modes which can be set via the MODEB register. • • • • Non-Auto Mode Transparent Mode 1 Transparent Mode 0 Extended Transparent Modes 0; 1 (MODEB: MDS1, MDS0 = 01) (MODEB: MDS1, MDS0, ADM = 101) (MODEB: MDS1, MDS0, ADM = 100) (MODEB: MDS1, MDS0 = 11) 2.1.1 Non-Auto Mode (MODEB: MDS1, MDS0 = 01) Characteristics: address recognition, arbitrary window size. All frames with valid addresses are forwarded directly to the system memory. According to the selected address mode, the IPAC can perform a 2-byte or 1-byte address recognition. If a 2-byte address field is selected, the high address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values in RAH1 and RAH2 registers. Similarly, two compare values can be programmed in special registers (RAL1, RAL2) for the low address byte. A valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. Thus, the IPAC can be called (addressed) with 6 different address combinations. HDLC frames with address fields that do not match with any of the address combinations, are ignored by the IPAC. The HDLC control field, data in the I-field and an additional status byte are temporarily stored in the RFIFOB. The HDLC control field and additional information can also be read from special registers (RHCRB, RSTAB), however, the register contents are only valid for the last received frame and values of previous frames are overwritten. If several frames are stored in the RFIFOB the information should be read from the FIFO contents. In non-auto mode, all frames are treated similarly. Semiconductor Group 32 11.97 PSB 2115 PSF 2115 Functional Description 2.1.2 Transparent Mode 1 (MODEB: MDS1, MDS0, ADM = 101) Characteristics: address recognition high byte Only the high byte of a 2-byte address field will be compared. The whole frame except the first address byte will be stored in RFIFOB. RAL1 contains the second and RHCRB the third byte following the opening flag. 2.1.3 Transparent Mode 0 (MODEB: MDS1, MDS0, ADM = 100) Characteristics: no address recognition No address recognition is performed and each frame will be stored in the RFIFOB. RAL1 contains the first and RHCRB the second byte following the opening flag. 2.1.4 Extended Transparent Modes 0, 1 (MODEB: MDS1, MDS0 = 11) Characteristics: fully transparent In extended transparent modes, fully transparent data transmission/reception without HDLC framing is performed, i.e. without FLAG generation/recognition, CRC generation/ check, bit-stuffing mechanism. This allows user specific protocol variations or the usage of Character Oriented Protocols (such as IBM BISYNC). Data transmission is always performed out of the XFIFOB. In extended transparent mode 0 (ADM = 0), data reception is done via the RAL1 register, which always contains the actual data byte assembled at the DD pin. In extended transparent mode 1 (ADM = 1), the receive data are additionally shifted into the RFIFOB. Also refer to chapter 2.1.8 and 2.1.9. Semiconductor Group 33 11.97 PSB 2115 PSF 2115 Functional Description 2.1.5 Receive Data Flow The following figure gives an overview of the management of the received HDLC frames as affected by different operating modes. FLAG MDS1 MDS0 ADM MODE ADDR ADDRESS RAH1,2 RAL1,2 CTRL CONTROL Ι DATA RFIFOB CRC STATUS FLAG 0 1 1 Non Auto/16 RHCRB RAL1,2 RSTAB X RFIFOB RHCRB RSTAB 0 1 0 Non Auto/8 RAH1,2 RFIFOB 1 0 1 Transparent 1 RAL1 RHCRB RSTAB RFIFOB 1 0 0 Transparent 0 RAL1 RHCRB RSTAB Description of Symbols: Compared with (register) Stored (FIFO, register) Note: In case of on 8 Bit Address, the Control Field starts here! ITD09619 Figure 9 Receive Data Flow of IPAC Semiconductor Group 34 11.97 PSB 2115 PSF 2115 Functional Description 2.1.6 Transmit Data Flow Transparent frames can be transmitted as shown below. FLAG ADDR ADDRESS CTRL CONTROL XFIFOB Ι DATA CRC CHECKRAM FLAG Transmit Transparent Frame (XTF) ITD09620 Figure 10 Transmit Data Flow of IPAC For transparent frames (command XTF via CMDRB register), the address and the control fields have to be entered in the XFIFOB. This is possible in all operating modes. Semiconductor Group 35 11.97 PSB 2115 PSF 2115 Functional Description 2.1.7 Serial Interface The two serial interfaces of the IPAC provide two fully independent channels for Bchannel communication. 2.1.7.1 Clock Mode 5 (Time-Slots) This operating mode has been designed for application in time-slot oriented PCM systems. It is well known as “Clock Mode 5“ from the HSCX-TE PSB 21525. The receive and transmit clock is identical for both channels and is generated from the double rate bit clock at the DCL pin, i.e. the bit clock frequency is DCL/2. The IPAC receives and transmits only during certain time-slots of programmable width (1 … 256 bit, via RCCR and XCCR registers) and location with respect to a frame synchronization signal, which is determined via the FSC pin. One of up to 64 time-slots can be programmed independently for receive and transmit direction via TSAR and TSAX registers, and an additional clock shift of 0 … 7 bits via TSAR, TSAX, and CCR2 registers. Together with bits XCS0 and RCS0 (LSB of clock shift), located in the CCR2 register, there are 9 bits to determine the location of a time-slot. According to the value programmed via those bits, the receive/transmit window (time-slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame synchronization signal and is active during the number of clock periods programmed via RCCR, XCCR (number of bits to be received/transmitted within a timeslot) as shown in figure 11. Within one frame the B1-channel occupies bit 0...7 and the B2-channel bit 8...15. Considering the minimum delay of 1 bit, the host programs the previous channel with 7 bits clock shift in order to access a certain channel. Table 1 Timeslot 0 (B1-channel) 1 (B2-channel) Programming of Timeslots TSAR/TSAX No. of previous channel (see note) 0 RCS0...2 7 7 Note: The previous channel of the B1-channel is the last of the IOM-2 frame, e.g. in TE mode (DCL=1.536 MHz) the channel number is 11 (12th timelsot). Semiconductor Group 36 11.97 PSB 2115 PSF 2115 Functional Description Register: TSAR TSAX TSNR TSNX Time-Slot Number TSN (6 Bits ) 9 Bits RCS 2 RCS 1 RCS 0 CCR 2 XCS 2 XCS 1 XCS 0 Clock Shift CS (3 Bits ) FSC BCL TIME-SLOT ~ ~ N ~ ~ SDS DELAY SCFG : TSLT (0, 7, 15, ... 255 Clocks) WIDTH SCFG : TLEN (8 or 16 Bit) ITD09621 Figure 11 Location of Time-Slots Note: In extended transparent mode the width of the time-slots has to be n × 8 bit. The active time-slot can additionally be indicated by a programmable strobe signal SDS of which the output is set to log 1 during the active window. Semiconductor Group 37 11.97 PSB 2115 PSF 2115 Functional Description 2.1.7.2 Data Encoding In the point-to-point configuration, the IPAC supports both NRZ and NRZI data encoding (selectable via CCR1 register). Figure 12 NRZ Encoding/NRZI Encoding During NRZI encoding, level changes are interpreted as log 0, and no changes in level as log 1. Data output on the IOM interface is performed with the rising edge of DCL, data input with the second falling DCL clock edge. Semiconductor Group 38 11.97 PSB 2115 PSF 2115 Functional Description 2.1.8 Fully Transparent Transmission and Reception When programmed to the extended transparent mode via the MODEB register (MDS1, MDS0 = 11), each channel of the IPAC supports fully transparent data transmission and reception without HDLC framing overhead, i.e. without • FLAG insertion and deletion • CRC generation and checking • Bit-stuffing mechanism. In order to enable fully transparent data transfer, RAC bit in MODEB has to be reset and FFH has to be written to XAD1, XAD2 and RAH2. Data transmission is always performed out of the transmit FIFO by directly shifting the contents of the XFIFOB via the serial transmit data pin (DU). Transmission is initiated by setting CMDRB : XTF (08H); end of transmission is indicated by EXIRB : EXE (40H). In receive direction, the character currently assembled via the receive data line (DD) is available in the RAL1 register. Additionally, in extended transparent mode 1 (MODEB: MDS1, MDS0, ADM = 111), the received data is shifted into the RFIFOB. This feature can be profitably used e.g. for: • user specific protocol variations • the application of character oriented protocols (e.g. BISYNC) • test purposes, line intentionally violation of HDLC protocol rules (e.g. wrong CRC) The valid timeslot for data access on IOM-2 can be selected by setting timeslot position and timeslot length. For a timeslot length greater than 8-bit (e.g. 16-bit) the access to the selected timeslots on IOM-2 is not synchronized to the frame sync signal FSC. For example if the valid 16-bit timeslot is programmed to B1 and B2, the IPAC does not ensure that transmission is started in B1 of the very first IOM-2 frame, it may also start with B2 and then continue with B1 and B2 in the next frame. It should be noted that in extended transparent mode 1 an invalid octett is output on IOM-2 before the first valid octett from the XFIFOB is transmitted. In receive direction the first 3 ocetetts of each 64-byte RFIFOB block are invalid and should be discarded. 2.1.9 Cyclic Transmission (Fully Transparent) If the extended transparent mode is selected, the IPAC supports the continuous transmission of the transmit FIFO’s contents. After having written 1 to 64 bytes to the XFIFOB, the command XREP.XTF.XME via the CMDR register (bit 7 … 0 = ‘00101010’ = 2AH) forces the IPAC to repeatedly transmit the data stored in the XFIFOB via DU pin. The cyclic transmission continues until a reset command (CMDRB : XRES) is issued, after which continuous ‘1’-s are transmitted. Semiconductor Group 39 11.97 PSB 2115 PSF 2115 Functional Description Note: In DMA-mode the command XREP, XTF has to be written to CMDRB. 2.1.10 Continuous Transmission (DMA Mode only) If data transfer from system memory to the IPAC is done by DMA (DMA bit in XBCH set), the number of bytes to be transmitted is usually defined via the Transmit Byte Count registers (XBCH, XBCL : bits XBC11 ... XBC0). Setting the „Transmit Continuously“ (XC) bit in XBCH, however, the byte count value is ignored and the DMA interface of the IPAC will continuously request for transmit data any time 64 bytes can be stored in the XFIFOB. This feature can be used e.g. to • continuously transmit voice or data onto a PCM highway, or to • transmit frames exceeding the byte count programmable via XBCH, XBCL (frames with more than 4095 bytes). Note: If the XC bit is reset during continuous transmission, the transmit byte count becomes valid again, and the IPAC will request the amount of DMA transfers programmed via XBC11 ... XBC0. Otherwise the continuous transmission is stopped when a data underrun condition occurs in the XFIFOB, i.e. the DMA controller does not transfer further data to the IPAC. In this case continuous ’1’-s (idle), without appending a CRC, are transmitted. 2.1.11 Receive Length Check Feature The IPAC offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. This feature is controlled via the special Receive Length Check Register (RLCR). The function is enabled by setting the RC (Receive Check) bit in RLCR and programming the maximum frame length via bits RL5 … RL01) . According to the value written to RL5 … RL0, the maximum receive length can be adjusted in multiples of 64-byte blocks as follows: MAX. LENGTH = (RL + 1) × 64. All frames exceeding this length are treated as if they have been aborted from the opposite station, i.e. the CPU is informed via a 1) The frame length includes all bytes which are stored in the RFIFOB. Semiconductor Group 40 11.97 PSB 2115 PSF 2115 Functional Description – RME interrupt, and the – RAB bit in RSTA register is set! To distinguish between frames really aborted from the opposite station, the receive byte count (readable from RBCHB, RBCLB registers) exceeds the maximum receive length (via RL5 … RL0) by one or two bytes in this case. The check includes all data that is copied into the RFIFOB. It does not include the address byte(s) if address recognition is selected. It includes the RSTAB value in all operating modes. 2.1.12 Data Inversion When NRZ data encoding has been selected, the IPAC may transmit and receive data inverted, i.e. a ‘one’ bit is transmitted as phys. zero (0 V) and a ‘zero’ bit as phys. one (+ 5 V) via the DU line. Figure 13 Data Inversion This feature is selected by setting the DIV bit in the CCR2 register. Semiconductor Group 41 11.97 PSB 2115 PSF 2115 Functional Description 2.2 2.2.1 D-Channel Operation Layer-2 Functions for HDLC The D-Channel HDLC controller in the IPAC is responsible for the data link layer using HDLC/SDLC based protocols. The IPAC can be configured to support data link layer to a degree that best suits system requirements. Multiple links may be handled simultaneously due to the address recognition capabilities, as explained in section 2.2.1.1. The IPAC supports point-to-point protocols such as LAPB (Link Access Procedure Balanced) used in X.25 networking. For ISDN, one particularly important protocol is the Link Access Procedure for the D channel (LAPD). LAPD, layer 2 of the ISDN D-channel protocol (CCITT I.441) includes functions for: – Provision of one or more data link connections on a D channel (multiple LAP). Discrimination between the data link connections is performed by means of a data link connection identifier (DLCI = SAPI + TEI) – HDLC-framing – Application of a balanced class of procedure in point-multipoint configuration. The HDLC transceiver in the IPAC performs the framing functions used in HDLC/SDLC based communication: flag generation/recognition, bit stuffing, CRC check and address recognition. The FIFO structure with two 64-byte pools for transmit and receive directions and an intelligent FIFO controller permit flexible transfer of protocol data units to and from the µC system. 2.2.1.1 Message Transfer Modes The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be programmed in a flexible way, to satisfy different system requirements. For the address recognition the IPAC contains four programmable registers for individual SAPI and TEI values SAP1-2 and TEI1-2, plus two fixed values for “group” SAPI and TEI, SAPG and TEIG. Semiconductor Group 42 11.97 PSB 2115 PSF 2115 Functional Description There are 5 different operating modes which can be set via the MODED register: Auto Mode (MDS2, MDS1 = 00) Characteristics: – Full address recognition (1 or 2 bytes). – Normal (mod 8) or extended (mod 128) control field format – Automatic processing of numbered frames of an HDLC procedure. If a 2-byte address field is selected, the high address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values in SAP1 and SAP2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as COMMAND/RESPONSE bit (C/R) dependent on the setting of the CRI bit in SAP1, and will be excluded from the address comparison. Similarly, the low address byte is compared with the fixed value FFH (group TEI) and two compare values programmed in special registers (TEI1, TEI2). A valid address will be recognized in case the high and low byte of the address field match one of the compare values. The IPAC can be called (addressed) with the following address combinations: – – – – – – – SAP1/TEI1 SAP1/FFH SAP2/TEI2 SAP2/FFH FEH(FCH)/TEI1 FEH(FCH)/TEI2 FEH(FCH)/FFH Only the logical connection identified through the address combination SAP1, TEI1 will be processed in the auto mode, all others are handled as in the non-auto mode. The logical connection handled in the auto mode must have a window size 1 between transmitted and acknowledged frames. HDLC frames with address fields that do not match with any of the address combinations, are ignored by the IPAC. In case of a 1-byte address, TEI1 and TEI2 will be used as compare registers. According to the X.25 LAPB protocol, the value in TEI1 will be interpreted as COMMAND and the value in TEI2 as RESPONSE. The control field is stored in RHCRD register and the I field in RFIFOD. Additional information is available in RSTAD. Non-Auto Mode (MDS2, MDS1 = 01) Characteristics: Full address recognition (1 or 2 bytes) Arbitrary window sizes All frames with valid addresses are accepted and the bytes following the address are transferred to the µP via RHCRD and RFIFOD. Additional information is available in RSTAD. Semiconductor Group 43 11.97 PSB 2115 PSF 2115 Functional Description Transparent Mode 1 (MDS2, MDS1, MDS0 = 101). Characteristics: TEI recognition A comparison is performed only on the second byte after the opening flag, with TEI1, TEI2 and group TEI (FFH). In case of a match, the first address byte is stored in SAPR, the (first byte of the) control field in RHCRD, and the rest of the frame in the RFIFOD. Additional information is available in RSTAD. Transparent Mode 2 (MDS2, MDS1, MDS0 = 110). Characteristics: no address recognition Every received frame is stored in RFIFOD (first byte after opening flag to CRC field). Additional information can be read from RSTAD. Transparent Mode 3 (MDS2, MDS1, MDS0 = 111). Characteristics: SAPI recognition A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and group SAPI (FEH/FCH). In the case of a match, all the following bytes are stored in RFIFOD. Additional information can be read from RSTAD. Semiconductor Group 44 11.97 PSB 2115 PSF 2115 Functional Description 2.2.1.2 Reception of Frames A 2x32-byte FIFO buffer (receive pools) is provided in the receive direction. The control of the data transfer between the CPU and the IPAC is handled via interrupts. There are two different interrupt indications concerned with the reception of data: – RPF (Receive Pool Full) interrupt, indicating that a 32-byte block of data can be read from the RFIFOD and the received message is not yet complete. – RME (Receive Message End) interrupt, indicating that the reception of one message is completed, i.e. either • one message ≤ 32 bytes, or • the last part of a message ≥ 32 bytes is stored in the RFIFOD. Depending on the message transfer mode the address and control fields of received frames are processed and stored in the receive FIFO or in special registers as depicted in figure 15. The organization of the RFIFOD is such that, in the case of short (≤ 32 bytes), successive messages, up to two messages with all additional information can be stored. The contents of the RFIFOD would be, for example, as shown in figure 14. RFIFOD 0 Interrupts in Wait Line Receive Message 1 _ ( < 32 bytes) 31 0 Receive Message 2 _ (< 32 bytes) RME 31 RME ITD09622 Figure 14 Contents of RFIFOD (short message) Semiconductor Group 45 11.97 PSB 2115 PSF 2115 Functional Description Flag Address High Address Low Control Information CRC Flag Auto-Mode (U and I frames) SAP1,SAP2 FE,FC (Note 1) TEI1,TEI2 FF (Note 2) TEI1,TEI2 FF (Note 2) TEI1,TEI2 FF RHCRD (Note 3) RHCRD (Note 4) RHCRD (Note 4) RFIFOD RSTAD Non-Auto Mode SAP1,SAP2 FE,FC (Note 1) RFIFOD RSTAD Transparent Mode 1 SAPR RFIFOD RSTAD Transparent Mode 2 RFIFOD RSTAD Transparent Mode 3 SAP1,SAP2 FE,FC RFIFOD RSTAD ITD09623 Description of Symbols: Checked automatically by IPAC Compared with register or fixed value Stored into register or RFIFOD Figure 15 Receive Data Flow Note 1: Only if a 2-byte address field is defined (MDS0 = 1 in MODED register). Note 2: Comparison with Group TEI (FFH) is only made if a 2-byte address field is defined (MDS0 = 1 in MODED register). Note 3: In the case of an extended, modulo 128 control field format (MCS = 1 in SAP2 register) the control field is stored in RHCRD in compressed form (I frames). Note 4: In the case of extended control field, only the first byte is stored in RHCRD, the second in RFIFOD. Semiconductor Group 46 11.97 PSB 2115 PSF 2115 Functional Description When 32 bytes of a message longer than that are stored in RFIFOD, the CPU is prompted to read out the data by an RPF interrupt. The CPU must handle this interrupt before more than 32 additional bytes are received, which would cause a “data overflow” (figure 16). This corresponds to a maximum CPU reaction time of 16 ms (data rate 16 kbit/s). After a remaining block of less than or equal to 16 bytes has been stored, it is possible to store the first 16 bytes of a new message (see figure 16). The internal memory is now full. The arrival of additional bytes will result in “data overflow” and a third new message in “frame overflow”. The generated interrupts are inserted together with all additional information into a wait line to be individually passed to the CPU. After an RPF or RME interrupt has been processed, i.e. the received data has been read from the RFIFOD, this must be explicitly acknowledged by the CPU issuing a RMC (Receive Message Complete) command. The IPAC can then release the associated FIFO pool for new data. If there is an additional interrupt in the wait line it will be generated after the RMC acknowledgment. RFIFOD 0 Interrupts in the Queue 0 RFIFOD Interrupts in the Queue Long Message Long Message 1 _ ( < 48 bytes) 31 0 RPF 31 0 RPF 15 16 Message 2 _ ( < 32 bytes) 31 RPF 31 RME RME ITD09624 Figure 16 Contents of RFIFOD (long message) Semiconductor Group 47 11.97 PSB 2115 PSF 2115 Functional Description Information about the received frame is available for the µP when the RME interrupt is generated, as shown in table 2. Table 2 Receive Information at RME Interrupt Register SAPR Bit – Mode Transparent mode 1 Information First byte after flag (SAPI of LAPD address field) Control field RHCRD – – – – C/R Auto mode, I (modulo 8) and U frames Auto mode, I frames (modulo 128) Non-auto mode, 1-byte address field Non-auto mode, 2-byte address field Transparent mode 1 Auto mode, 2-byte address field Non-auto mode, 2-byte address field Transparent mode 3 Auto mode, 2-byte address field Non-auto mode, 2-byte address field Transparent mode 3 All except Transparent mode 2,3 All Compressed control RHCRD field 2nd byte after flag 3rd byte after flag Type of frame (Command/ Response) RHCRD RHCRD RSTAD Recognition of SAPI RSTAD SA1-0 Recognition of TEI Result of CRC check (correct/ incorrect) Data available in RFIFOD (yes/no) Abort condition detected (yes/no) Data overflow during reception of a frame (yes/no) RSTAD RSTAD TA CRC RSTAD RSTAD RDA RAB All All RSTAD RDO All Number of bytes RBCLD received in RFIFOD Message length RBCLD RBCHD RBC4-0 All RBC11-0 All Semiconductor Group 48 11.97 PSB 2115 PSF 2115 Functional Description 2.2.1.3 Transmission of Frames A 2×32 byte FIFO buffer (transmit pools) is provided in the transmit direction. If the transmit pool is ready (which is true after an XPR interrupt or if the XFW bit in STARD is set), the CPU can write a data block of up to 32 bytes to the transmit FIFO. After this, data transmission can be initiated by command. The transmission of transparent frames (command: XTF) and I frames (command: XIF) is shown in figure 17. * Transmit Transparent Frame * Transmit I Frame (auto-mode only!) XFIFOD XAD1 XAD2 XFIFOD Transmitted HDLC Frame Flag Address High Address Low If 2 byte address field selected Control INFORMATION CRC Flag Appended if CPU has issued transmit message end (XME) command. ITD09625 Description of Symbols: Generated automatically by IPAC Written initially by CPU (into register) Loaded (repeatedly) by CPU upon IPAC request (XPR interrupt) Figure 17 Transmit Data Flow Semiconductor Group 49 11.97 PSB 2115 PSF 2115 Functional Description For transparent frames, the whole frame including address and control field must be written to the XFIFOD. The transmission of I frames is possible only if the IPAC is operating in the auto mode. The address and control field is autonomously generated by the IPAC and appended to the frame, only the data in the information field must be written to the XFIFOD. If a 2-byte address field has been selected, the IPAC takes the contents of the XAD 1 register to build the high byte of the address field, and the contents of the XAD 2 register to build the low byte of the address field. Additionally the C/R bit (bit 1 of the high byte address, as defined by LAPD protocol) is set to “1” or “0” depending on whether the frame is a command or a response. In the case of a 1-byte address, the IPAC takes either the XAD 1 or XAD 2 register to differentiate between command or response frame (as defined by X.25 LAPB). The control field is also generated by the IPAC including the receive and send sequence number and the poll/final (P/F) bit. For this purpose, the IPAC internally manages send and receive sequence number counters. In the auto mode, S frames are sent autonomously by the IPAC. The transmission of U frames, however, must be done by the CPU. U frames must be sent as transparent frames (XTF), i.e. address and control field must be defined by the CPU. Once the data transmission has been initiated by command (XTF or XIF), the data transfer between CPU and IPAC is controlled by interrupts. The IPAC repeatedly requests another data packet or block by means of an XPR interrupt, every time no more than 32 bytes are stored in the XFIFOD. The processor can then write further data to the XFIFOD and enable the continuation of frame transmission by issuing an XIF/XTF command. If the data block which has been written last to the XFIFOD completes the current frame, this must be indicated additionally by setting the XME (Transmit Message End) command bit. The IPAC then terminates the frame properly by appending the CRC and closing flag. If the CPU fails to respond to an XPR interrupt within the given reaction time, a data underrun condition occurs (XFIFOD holds no further valid data). In this case, the IPAC automatically aborts the current frame by sending seven consecutive “ones” (ABORT sequence). The CPU is informed about this via an XDU (Transmit Data Underrun) interrupt. It is also possible to abort a message by software by issuing an XRES (Transmitter RESet) command, which causes an XPR interrupt. After an end of message indication from the CPU (XME command), the termination of the transmission operation is indicated differently, depending on the selected message transfer mode and the transmitted frame type. Semiconductor Group 50 11.97 PSB 2115 PSF 2115 Functional Description If the IPAC is operating in the auto mode, the window size (= number of outstanding unacknowledged frames) is limited to 1; therefore an acknowledgment is expected for every I frame sent with an XIF command. The acknowledgment may be provided either by a received S or I frame with corresponding receive sequence number (see figure 14). If no acknowledgment is received within a certain time (programmable), the IPAC requests an acknowledgment by sending an S frame with the poll bit set (P = 1) (RR or RNR). If no response is received again, this process is repeated in total CNT times (retry count, programmable via TIMR1 register). The termination of the transmission operation may be indicated either with: – XPR interrupt, if a positive acknowledgment has been received, – XMR interrupt, if a negative acknowledgment has been received, i.e. the transmitted message must be repeated (XMR = Transmit Message Repeat), – TIN interrupt, if no acknowledgment has been received at all after CNT times the expiration of the time period t1 (TIN = Timer INterrupt, XPR interrupt is issued additionally). Note: Prerequisite for sending I frames in the auto mode (XIF) is that the internal operational mode of the timer has been selected in the MODED register (TMD bit = 1). The transparent transmission of frames (XTF command) is possible in all message transfer modes. The successful termination of a transparent transmission is indicated by the XPR interrupt. A transmission may be aborted from the outside (E ≠ D) which has the effect that the stop/go bit is set to 1, provided DIM1-0 (MODED register) are programmed appropriately. An example of this is the occurrence of an S bus D-channel collision. If this happens before the first FIFO pool has been completely transmitted and released, the IPAC will retransmit the frame automatically as soon as transmission is enabled again. Thus no µP interaction is required. On the other hand, if a transmission is inhibited by the Stop/Go bit after the first pool has already been released (and XPR generated), the IPAC aborts the frame and requests the processor to repeat the frame with an XMR interrupt. In LT-T mode the Stop/Go bit can be output on pin AUX7 which may be used for test purposes. Semiconductor Group 51 11.97 PSB 2115 PSF 2115 Functional Description 2.3 Control Procedures Control procedures describe the commands and messages required to control the IPAC PSB 2115 in different modes and situations. This chapter shows the user how to activate and deactivate the device under various circumstances. In order to keep this chapter as application oriented as possible only actions and reactions the user needs to initiate or may observe are mentioned. 2.3.1 ← → ← ← ← → Activation Initiated by Exchange (LT-S) LT-S IOM®-2 (1111b) (1111b) (0100b) (1000b) (1100b) (1000b/1001b) C/I C/I C/I C/I C/I DC (1111b) DI (1111b) ← ; Initial state is G1 deactivated → ; and F3 Power Down _ ; Start activation TE/LT-T IOM®-2 C/I C/I C/I C/I C/I C/I DC DI RSY AR AI AR8/AR10 AR (1000b) AR (1000) AI (1100) → → ; Activation completed 2.3.2 Activation Initiated by Terminal (TE/LT-T) The following scheme illustrates how a terminal initiates an activation. TE/LT-T IOM®-2 ← → _ ← _ _ ← ← ← C/I C/I C/I C/I C/I DC DI TIM PU AR8 (1111b) (1111b) (0000b) (0111b) (1000b) ; Start Activation (0100b) (1000b) (1100b) C/I C/I AR AI (1000b) (1100b) → → ; Transfer to G3 Activated ; ; LT-S IOM®-2 C/I C/I DC DI (1111b) (1111b) ← → ; Initial state is G1 Deactivated ; and F3 Power Down ; Request timing (IOM clocks) TIM Release C/I C/I C/I RSY AR AI Semiconductor Group 52 11.97 PSB 2115 PSF 2115 Functional Description 2.3.3 Deactivation A deactivation of the S-interface can only be initiated by the exchange side (IPAC in LT-S mode). It is possible to begin a deactivation process from all interim activation states, i.e. not only from the fully activated state. The following example nevertheless assumes that the line is fully activated when the deactivation is initialized. TE/LT-T IOM®-2 ← ← _ ← C/I C/I C/I C/I AI8 DR DI DC (1100b) (0000b) (1111b) (1111b) LT-S IOM®-2 C/I C/I C/I C/I C/I AI DR TIM DI DC (1100b) (0000b) (0000b) (1111b) (1111b) → → → _ _ ; Initial state ; start deactivation ; ; “G1 Deactivated” ; Transfer to “F3 Power Down” (only in intelligent NT mode, not in LT-S mode Semiconductor Group 53 11.97 PSB 2115 PSF 2115 Functional Description 2.3.4 D-Channel Access Control D-channel access control was defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Figure 18 illustrates that collisions are possible on the TIC- and the S-bus. Figure 18 D-Channel Access Control on TIC Bus and S Bus Semiconductor Group 54 11.97 PSB 2115 PSF 2115 Functional Description The TIC bus is used to control D-channel access on the IOM interface when more than one HDLC controller is connected. This configuration is illustrated in the above figure for TE1 where three ICCs are connected to one IOM-2 bus. On the S bus the D-channel control is handled according to the ITU recommendation I.430. This control mechanism is required everytime a point to multipoint configuration is implemented (NT → TE1 … TE8). While the S-bus collision detection is handled by the S interface control of the IPAC, TIC bus access is mainly controlled by the D-Channel HDLC controller of the IPAC or from external devices on the IOM-2 interface (e.g. ICC). The following sections describe both control mechanisms because the TIC bus, although largely handled by the HDLC controller, represents an important part of D-channel access. 2.3.4.1 TIC Bus D-Channel Control in TE The TIC bus was defined to organize D- and C/I channel access when two or more Dand C/I channel controllers can access the same IOM-2 timeslot. Bus access is controlled by five bits in IOM-2 channel No. 2 (see section 2.7.1): Upstream: Downstream: BAC TBA0 … 2 S/G Bus access control bit TIC bus address bits 0 … 2 Stop/Go bit When a controller wants to write to the D or C/I channel the following procedure is executed: 1. Controller checks whether BAC bit is set to ONE. If this is not the case access currently is not allowed: the controller has to postpone transmission. Only if BAC = 1 the controller may continue with the access procedure. 2. The controller transmits its TIC bus address (TBA0…2). This is done in the same frame in which BAC = “1” was recognized. On the TIC bus binary “ZERO”s overwrite binary “ONE”s. Thus low TIC bus addresses have higher priority. 3. After transmitting a TIC bus address bit, the value is read back (with the falling edge) to check whether its own address has been overwritten by a controller with higher priority. This procedure will continue until all three address bits are sent and confirmed. In case a bit is overwritten by an external controller with higher priority, the controller asking for bus access has to withdraw immediately from the bus by setting all TIC bus address bits to ONE. 4. If access was granted, the controller will put the D-channel data onto the IOM-2 bus in the following frame provided the S/G bit is set to ZERO (i.e. S-bus free to transmit). The BAC bit will be set to ZERO by the controller to block all remaining controllers. In case the S/G bit is ONE this prevents only the D-channel data to be switched Semiconductor Group 55 11.97 PSB 2115 PSF 2115 Functional Description through to the IOM-2 bus. The TIC bus request remains unaffected (i.e. if access was granted the TIC address and BAC bit are activated). As soon as the S-bus D-channel is clear and the S/G bit was set back to “GO” the controller will commence with data transmission. The S/G Bit generation in IOM-2 channel 2 is handled automatically by the IPAC operating in TE mode. 5. After the transmission of an HDLC frame has been completed the D-Channel controller withdraws from the TIC bus for two IOM-2 frames. This also applies when a new HDLC frame is to be transmitted in immediate succession. With this mechanism it is ensured that all connected controllers receive an equally fair chance to access the TIC bus. 2.3.4.2 S-Bus Priority Mechanism for D-Channel The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus. To implement collision detection the D (channel) and E (echo) bits are used. The Dchannel S-bus condition is indicated towards the IOM-2 interface with the S/G bit (see previous section). The access to the D-channel is controlled by a priority mechanism which ensures that all competing TEs are given a fair access chance. This priority mechanism discriminates among the kind of information exchanged and information exchange history: Layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). Furthermore, once a TE having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. The TE is given back its normal level within a priority class when all TEs have had an opportunity to transmit information at the normal level of that priority class. The priority mechanism is based on a rather simple method: A TE not transmitting layer2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by flags consisting of the binary pattern “01111110” and zero bit insertion is used to prevent flag imitation, the D-channel may be considered idle if more than seven consecutive 1s are detected on the D-channel. Hence by monitoring the D echo channel, the TE may determine if the D-channel is currently used by another TE or not. A TE may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. This number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. A TE, when in the active condition, is monitoring the D echo channel, counting the number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the number of consecutive binary 1s. If the required number of 1s according to the actual Semiconductor Group 56 11.97 PSB 2115 PSF 2115 Functional Description level of priority has been detected, the TE may start transmission of an HDLC frame. If a collision occurs, the TE immediately shall cease transmission, return to the D-channel monitoring state, and send 1s over the D-channel. 2.3.4.3 S-Bus D-channel Control in TEs If the IPAC is not in a point-to-point configuration in TE mode, D-channel collision on the S-bus can occur. For this purpose the characteristic of the D-channel Mode register must be programmed to DIM2-0 = 001 or 011 (refer to table 27 of chapter 4.3.7) for D-channel collision resolution according to ITU I.430. In this case the IPAC continuously compares the D data bits with the received E-echo bits. Depending on the priority class selected (8 or 10), the S/G bit is controlled in a way that data transmission by the internal D-channel controller or by an externally connected ICC will start after the appropriate number of E-bits set to ’1’ are detected by the layer 1 transceiver. The priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the Command/Indication (C/I) channel of the IOM-2 interface to the IPAC S-interface. If the activation is initiated by a TE, the priority class is selected implicitly by the choice of the activation command. If the S-interface is activated from the NT, an activation command selecting the desired priority class should be programmed at the TE on reception of the activation indication (AI8). In the activated state the priority class may be changed whenever required by simply programming the desired activation request command (AR8 or AR10). Semiconductor Group 57 11.97 PSB 2115 PSF 2115 Functional Description Application 1. Priority Class 8/10 Selection with NT Initiated Activation TE IOM®-2 ← → ← ← ← _ _ ← C/I C/I C/I C/I C/I C/I C/I C/I DC DI RSY AR AI AR8 (1111b) (1111b) (0100b) (1000b) (1100b) (1000b) C/I C/I Al Al (1100b) (1100b) → _ LT-S (NT) IOM®-2 C/I C/I C/I C/I DC DI AR AR (1111b) (1111b) (1000b) (1000b) ← → _ → ← → ; Request timing (IOM clocks) ; Activation with second C/I C/I C/I C/I AR AR AI AI (1000b) (1000b) (1100b) (1100b) → _ → _ ; ; Allocate highest priority ; priority (e.g. for packet data) ; Start activation from ; NT side ; ; Allocate highest priority ; (e.g. for signaling data) ; Allocate lower priority ; for packet data D: transfer HDLC frame AR10 (1001b) AI10 (1101b) D: transfer packet data 2. Priority Class 8/10 Selection with TE Initiated Activation TE IOM®-2 ← → _ ← _ _ ← ← ← _ ← C/I C/I C/I C/I C/I C/I C/I C/I C/I C/I C/I DC DI TIM PU (1111b) (1111b) (0000b) (0111b) NT IOM®-2 C/I C/I DC DI (1111b) (1111b) AR10 (1001b) TIM Release RSY AR AI10 AR8 AI8 (0100b) (1000b) (1101b) (1000b) (1100b) D: transfer packet data D: transfer HDLC frame Semiconductor Group 58 11.97 PSB 2115 PSF 2115 Functional Description 2.3.4.4 S-Bus D-Channel Control in LT-T In LT-T mode the IPAC is primarily considered to be in a point-to-point configuration. In these configurations no S-bus D-channel collision can occur, therefore the default setting after resetting the IPAC is transparent (IOM-2 → S-bus) D-channel transmission. In case a point to multipoint configuration is implemented, the characteristic of the Dchannel Mode register must be programmed to DIM2-0 = 001 or 011 (refer to table 27 of chapter 4.3.7) for D-channel collision resolution according to ITU I.430. Priority allocation is identical to that described for the TE mode. 2.3.4.5 D-Channel Control in the Intelligent NT (TIC- and S-Bus) In intelligent NT applications both the IPAC and one or more D-channel controllers on the S interface and/or the IOM-2 interface have to share a single upstream D-channel. The intelligent NT configuration involves a layer-1 device (e.g. IEC-Q TE) operating in TE mode (1.536 MHz DCL rate) and an IPAC in LT-S mode with its D-channel controller operating in TE timing mode (D-channel transmitting in IOM-2 channel 0). The IPAC incorporates an elaborate statemachine for D-channel priority handling on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is performed for the local D-channel sources (local access), i.e. for the IPAC D-channel controller and for a D-channel controller connected to the IOM-2 interface (e.g. ICC PEB 2070). Due to this an equal and fair access is guaranteed for all D-channel sources on both the S interface and the IOM-2 interface. For this purpose the IPAC is set in LT-S mode with its layer 1 function programmed to channel 1 and NT state machine activated. Therefore the layer 1 uses the C/I1 channel (which is realized by the layer 2 function), however the B1-, B2- and D-channels have to be mapped in IOM channel 0. The layer 2 function is configured to TE timing mode (D- and C/I-channel controller transmits on C/I0 and evaluates C/I0 and C/I1) with S/G bit evaluation (refer to table 27 of chapter 4.3.7). The priority handler for D-channel access on IOM-2 is enabled and the priority 8 or 10 is selected. The configuration settings of the IPAC in intelligent NT applications are summarized in table 3. Semiconductor Group 59 11.97 PSB 2115 PSF 2115 Functional Description Table 3 IPAC Configuration Settings in Intelligent NT Applications Configuration Description Select LT-S mode Configuration Setting Pins: MODE0 = 1 MODE1 = 0 Pins: CH2-0 = 001 MON-8 Configuration Register: FSMM = 1 MON-8 IOM-2 Channel Register: B1L = 1, B2L = 1, DL = 1 Register: SPCR:SPM = 0 Register: MODED:DIM2-0 = 001 Register: CONF:IDH = 1 Functional Block Layer 1 Select IOM-2 channel 1 Activate NT state machine Map channels B1, B2 and D to IOM channel 0 Layer 2 Select TE timing mode Enable S/G bit evaluation Enable D-channel priority handler on IOM-2 Select priority 8 or 10 for Register: D-channel priority handler on IOM-2 SCFG:PRI With the configuration settings shown above the IPAC in intelligent NT applications provides for equal access to the D-channel for terminals connected to the S-interface and for D-channel sources on IOM-2. For a detailed understanding the following sections provide a complete description on the procedures used by the D-channel priority handler on IOM-2, although this may not be necessary to use this mode. Semiconductor Group 60 11.97 PSB 2115 PSF 2115 Functional Description 1. NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The IPAC S-transceiver thus receives BAC = “1” (IOM-2 DU line) and transmits S/G = “0” (IOM-2 DD line). The access will then be established according to the following procedure: • Local D-channel source verifies that BAC bit is set to ONE (currently no bus access). • Local D-channel source issues TIC bus address and verifies that no controller with higher priority requests transmission. • Local D-channel source issues BAC = “0” to block other sources on IOM-2 and starts D-channel transmission. • IPAC S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). • Local D-channel source commences with D data transmission on IOM-2 as long as it receives S/G = “0”. • After D-channel data transmission is completed the controller sets the BAC bit to ONE. • IPAC S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel controller on IOM-2. • IPAC S-transceiver transmits non-inverted echo (E = D). • IPAC S-transceiver pulls S/G bit to ZERO (’Idle’ state) as soon as n D-bits = ’1’ are counted on IOM-2 (see note) to allow for further D-channel access. Note: Right after transmission the S/G bit is pulled to ’1’ until n successive D-bits = ’1’ occur on the IOM-2 interface. As soon as n D-bits = ’1’ are seen, the S/G bit is set to ’0’ and the IPAC D-channel controller may start transmission again. This allows an equal access for D-channel sources on IOM-2 and on the S interface. The number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). Figure 19 illustrates the signal flow in an intelligent NT and the algorithm of the Dchannel priority handler on IOM-2 implemented in the IPAC. Semiconductor Group 61 11.97 PSB 2115 PSF 2115 Functional Description 2. Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • IPAC S-transceiver (in intelligent NT) recognizes that the D-channel on the S-bus is active. • IPAC S-transceiver sets S/G = 1 to block local D-channel sources. • IPAC S-transceiver transfers S-bus D-channel data transparently through to the upstream IOM-2 bus (IOM-2 channel 0). • After D-channel transmission has been completed by the terminal and the IPAC S-transceiver in the intelligent NT recognizes the idle condition (i.e. eight consecutive D=1) on the S-bus D-channel, the S/G bit is set to ZERO. For both cases described above the exchange indicates via the A/B bit (controlled by layer 1) that D-channel transmission on this line is permitted (A/B = “1”). Data transmission could temporarily be prohibited by the exchange when only a single D-channel controller handles more lines (A/B = “0”, ELIC-concept). In case the exchange prohibits D data transmission on this line the A/B bit is set to “0” (block). For UPN applications with S extension this forces the intelligent NT IPAC Stransceiver to transmit an inverted echo channel on the S-bus, thus disabling all terminal requests, and switches S/G to A/B , which blocks the D-channel controller in the intelligent NT. Note: Although the IPAC S-transceiver operates in LT-S mode and is pinstrapped to IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position. Semiconductor Group 62 11.97 PSB 2115 PSF 2115 Functional Description Figure 19 Data Flow for Collision Resolution Procedure in Intelligent NT Semiconductor Group 63 11.97 PSB 2115 PSF 2115 Functional Description The state machine for D-channel access in the intelligent NT describes four states and four types of conditions for state transition: States Ready The D-channel is transparent to the layer 1 (D,20 = D6) and no device occupies the D-channel (BAC=1). The echo bits correspond to the received D-bits on the S-interface. The layer 2 is blocked (S/G=1) until the required number (priority) of D=1 are counted on IOM-2. This state is identical to the ’Ready’ state, except the layer 2 may also start transmission on the D-channel (S/G=0). The D-channel is transparent to the layer 1 and occupied by a source on the S-interface. The layer 2 is blocked (S/G=1). The D-channel is occupied by the IPAC D-channel controller or by another D-channel controller on IOM-2. This is indicated by BAC=0. The Echo-bits are set to ‘D’ (terminals on S are blocked). A terminal on the S-interface has started transmission on the Dchannel (DS=0). Preceeding this, the required number of D=1 (according to the priority setting) was written and read back (E-bits) on the S-interface. The required number of D=1 is counted on the IOM-2 interface, so the IPAC D-channel controller may start transmission again. The IPAC layer 2 controller has started transmission on the D-channel (DD = idle). The IPAC layer 2 controller has stoped transmission on the D-channel (DD = idle), i.e. the end flag of the previous frame or an abort is detected. Idle S Access Local Access State transition conditions T1 T2 T3 T4 The number n of D=1 which has to be counted on IOM-2 by the state machine for state transition T2 is described in the table below: Previous transmission of NT D-channel controller Configured Priority Prio = 8 (SCFG:PRI=0) Prio = 10 (SCFG:PRI=1) successful (end flag seen) n=9 n = 11 not successful (abort seen) n=8 n = 10 Note: D=idle implies that 8 consecutive ’1’ are detected on the D-channel. Semiconductor Group 64 11.97 PSB 2115 PSF 2115 Functional Description 2.3.5 IOM®-2 Interface Channel Switching In order to realize intelligent NT configurations the IPAC provides basic switching functions. These include: • Individual channel transfer from the selected (i.e. pin strapped) IOM-2 channel (channel 0 or 1) to IOM-2 channel 0. • Individual channel reversion on input and output lines. All switching functions are controlled via the MON-8 “IOM-2 channel” register (see MON8 description). The following sections illustrate a variety of possible switching combinations typical for the intelligent NT. To facilitate the description of the switching function figure 20 illustrates a typical intelligent NT with the speech CODEC ARCOFI combined with several terminals. Monitor programming for both ARCOFI and IPAC can only be performed in monitor channel 1. Figure 20 Intelligent NT-Configuration for IOM®-2 Channel Switching Semiconductor Group 65 11.97 PSB 2115 PSF 2115 Functional Description The following four examples illustrate typical switching operations. Three of them are programmed in the “IOM-2 Channel” register, example No. 4 makes use of the “Loopback” register. All register bits related to the B1 or B2 channel are set to ZERO unless otherwise stated. 1. Connection B1 (e.g. TE1) → Exchange, B2 (e.g. TE8) → Exchange IPAC (LT-S) DU B 1L = 1 DD B1 B2 DIN Exchange B 2L = 1 IOM -2 Reg. R B1 B2 DOUT DU R DD ARCOFI Power-Down ITS09627 2. Connection B1 (e.g. TE1) → Exchange, B2 (e.g. TE8) → U-TE IPAC (LT-S) DU B 1L = 1 DD IC2 B1 IOM -2 Reg. R B1 DIN Exchange D OUT B 2D = 1 IC2 DU R DD ARCOFI Voice Data to IC2 ITS09628 Semiconductor Group 66 11.97 PSB 2115 PSF 2115 Functional Description 3. Connection U-TE (B1) → Exchange, B2 (e.g. TE1) → Exchange IPAC (LT-S) DU B 2L = 1 DD R B2 DIN B1 B2 B1 D OUT Exchange IOM -2 Reg. DU R DD ARCOFI Voice Data to B1 ITS09629 4. Connection TE1 (B1) ↔ TE8 (B2), U-TE (B1 or B2) → Exchange IPAC (LT-S) DU IB1 = 1 IB2 = 1 IB12 = 1 R DIN B2 or B1 B2 or B1 D OUT Exchange B1 B2 B2 B1 DD (IOM -2 channel 1) Loopback Reg. DU R DD ARCOFI Voice Data to B1 or B2 R (IOM -2 channel 0) ITS09630 Semiconductor Group 67 11.97 PSB 2115 PSF 2115 Functional Description 2.4 2.4.1 S/T Interface Operating Modes The S-transceiver supports terminal mode (TE), line termination subscriber side mode (LT-S) and line termination trunk side mode (LT-T). The selection is performed by two mode pins (see table 4), additionally the B-channel receive and transmit data paths are switched to DU or DD line depending on the mode (figure 21). In other words, the DU line always carries data which is transferred from the subscriber to the central office and the DD line carries data which comes from the central office to the subscriber. Therefore the direction of DU and DD is mode dependent: • DU is input, DD is output (TE and LT-T) • DU is output, DD is input (LT-S) In LT-S and LT-T mode the EAW pin is used as the second mode pin. Table 4 Mode Setting MODE0 TE-mode LT-T mode LT-S mode 0 1 1 MODE1/ EAW EAW 1 0 Transmit-data on S DU on IOM DU on IOM DD on IOM Receive-data on S DD on IOM DD on IOM DU on IOM Figure 21 Data Path Switching Semiconductor Group 68 11.97 PSB 2115 PSF 2115 Functional Description 2.4.2 S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. Pseudo-ternary coding with 100 % pulse width is used (see following section). 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. The IPAC uses two symmetrical, differential outputs (SX1, SX2) and two symmetrical, differential inputs (SR1, SR2). These signals are coupled via external circuitry and two transformers onto the 4 wire S-interface. The nominal pulse amplitude on the S-interface is 750 mV (zero-peak). The following figure illustrates the code used. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: The first binary ZERO following the framing balance bit is of the same polarity as the framing-balancing bit (required code violation) and the last binary ZERO before the framing bit is of the same polarity as the framing bit. Figure 22 S/T -Interface Line Code (without code violation) A standard S/T frame consists of 48 bits. In the direction TE → NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT → TE and TE → NT) with all framing and maintenance bits. Semiconductor Group 69 11.97 PSB 2115 PSF 2115 Functional Description Figure 23 Frame Structure at Reference Points S and T (ITU I.430) –F – L. –D –E – FA –N – B1 – B2 –A –S –M Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) → identifies new frame (always positive pulse) L. = (0b) → number of binary ZEROs sent after the last L. bit was odd Signaling data specified by user E = D → no D-channel collision. ZEROs overwrite ONEs See section 6.3 in ITU I.430 N = FA User data User data A = (0b) → INFO 2 transmitted A = (1b) → INFO 4 transmitted S1 or S2 channel data (see note below) M = (1b) → Start of new multi-frame Note: The ITU I.430 standard specifies S1 - S5 for optional use. The IPAC supports S1 - S2. Semiconductor Group 70 11.97 PSB 2115 PSF 2115 Functional Description 2.4.3 S/T-Interface Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer 1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Qchannel). The Q bits are defined to be the bits in the FA bit position. In the NT-to-TE direction the S channel bits are used for information transmission. Two S channels (S1 and S2) out of five possible S channels can be accessed by the IPAC. The S and Q channels are accessed via the IOM-2 interface monitor channel. The following table shows the S and Q bit positions within the multi-frame. Table 5 Multiframe Structure NT-to-TE FA Bit Position ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE M Bit ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE S Bit S11 S21 ZERO ZERO ZERO S12 S22 ZERO ZERO ZERO S13 S23 ZERO ZERO ZERO S14 S24 ZERO ZERO ZERO S11 S21 TE-to-NT FA Bit Position Q1 ZERO ZERO ZERO ZERO Q2 ZERO ZERO ZERO ZERO Q3 ZERO ZERO ZERO ZERO Q4 ZERO ZERO ZERO ZERO Q1 ZERO Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 Semiconductor Group 71 11.97 PSB 2115 PSF 2115 Functional Description In TE and LT-T mode the IPAC identifies the Q-bit position (after multi-frame synchronization has been established) by waiting for the FA bit inversion in the received S/T-interface data stream (FA [NT → TE] = binary ONE). After successful identification, the Q data will be inserted at the upstream (TE → NT) FA bit position. When synchronization is not achieved or lost, it mirrors the received FA bits. Multi-frame synchronization is achieved after two complete multi-frames have been detected with reference to FA/N bit and M bit positions. Multi-frame synchronization is lost after two or more bit errors in F A/N bit and M bit positions have been detected in sequence, i.e. without a complete valid multi-frame between. The multi-frame synchronization can be disabled by programming (MFD-bit in MON-8 configuration register). 2.4.4 2.4.4.1 S/T Transceiver Control MON-8 Commands (Internal Register Access) The S/T transceiver of the IPAC PSB 2115 contains four internal registers. Access to these registers is only possible via the IOM-2 monitor channel. The following registers are implemented in the IPAC: • • • • Configuration Register Loop-back Register IOM-2 Channel Register SM/CI Register The structure of MON-8 write and read request/response commands are shown in the three tables below: Semiconductor Group 72 11.97 PSB 2115 PSF 2115 Functional Description Table 6 MON-8 “Write to Register” Structure 1. Byte 2. Byte r r r D7 D6 D5 D4 D3 D2 D1 D0 Reg. Address Register Data Write 1 0 0 0 r MON-8 Table 7 MON-8 “Read Register Request” Structure 1. Byte 2. Byte 0 0 0 0 0 0 0 r r r r Reg. Address 1 0 0 0 0 MON-8 The response issued by the IPAC after having received a “Read Register Request” has the following structure. Table 8 MON-8 “Read Response” Structure 1. Byte 2. Byte r r r D7 D6 D5 D4 D3 D2 D1 D0 Reg. Adr. Confirmation Register Data Read 1 0 0 0 r MON-8 The following sections describe the register features. Semiconductor Group 73 11.97 PSB 2115 PSF 2115 Functional Description 2.4.4.2 MON-8 Configuration Register In the configuration register the user programs the IPAC for different operational modes, and selects required S-bus features. The following paragraphs describe the application relevance of all individual configuration register bits. Address: 1h MFD Value after Reset: 00H 0 FSMM LP SQM RCVE C/W/P 0 RD/WR MFD Multi-Frame-Disable. Selects whether multiframe generation (LT-S) or synchronization (TE, LT-T) is prohibited (MFD=1) or allowed (MFD=0). Enable multiframing if S/Q channel data transfer is desired. If MFD=1 no S/Q MONITOR messages are released. When reading this register the bit indicates whether multiframe synchronization has been established (MFD=1) or not (MFD=0). Finite State Machine Mode. By programming this bit the user has the possibility to exchange the state machines of LT-S and NT, i.e. an IPAC pin strapped for LT-S operates with a NT state machine. All other operation mode specific characteristics are retained. This function is used in intelligent NT configurations where the IPAC needs to be pin-strapped to LT-S mode but the state machine of an NT is desirable. Loop Transparency. In case analog loop-backs are closed with C/I = ARL or bit SC in the loop-back register, the user may determine with this bit, whether the data is forwarded to the S/T-interface outputs (transparent) or not. The default setting depends on the operational mode. TE/LT-T modes: 0 = non transparent 1= transparent ext. loop LT-S mode: 0= transparent 1= non transparent In LT-S by default transparency is selected (LP=0), for LT-T and TE nontransparency is standard (LP=0). FSMM LP Semiconductor Group 74 11.97 PSB 2115 PSF 2115 Functional Description SQM Selects the SQ channel handling mode. In non-auto mode operation, the IPAC issues S1 and Q messages in the IOM-2 monitor channel only after a change has been detected. The S2 channel is not available in non-auto mode. In transparent mode monitor messages containing the S1, S2 and Q data are forwarded to IOM-2 once per multiframe (5 ms), regardless of the data content. Programming the SQM bit is only relevant if multiframing on S/T is selected (bit MFD configuration register). See also MON-1 and MON-2 monitor messages. Receive Code Violation Errors. The user has the option to issue a C/I error code (CVR) everytime an illegal code violation has been detected. The implementation is realized according to ANSI T1.605. This bit has three different meanings depending on the operational mode of the IPAC: In LT-S mode the S/T bus configuration is programmed. For point-to-point or extended passive bus configurations an adaptive timing recovery must be chosen. This allows the IPAC to adapt to cable length dependent round trip delays. In LT-T mode the user selects the amount of permissible wander before a C/I code warning will be issued by the IPAC. The warning may be sent after 25 µs (C/W/P=1) or 50 µs (C/W/P=0). Note: The C/I indication SLIP which will be issued if the specified wander has been exceeded, is only a warning. Data has not been lost at this stage. In TE mode this bit is not used RCVE C/W/P Semiconductor Group 75 11.97 PSB 2115 PSF 2115 Functional Description 2.4.4.3 MON-8 Loop-Back Register The loop-back register controls all analog (S/T-interface) and digital (IOM-2 interface) loop-backs. Additionally the wake-up mode can be programmed. Address: 2h AST SB1 SB2 SC IB1 IB2 1 IB12 RD/WR Value after Reset: 02H . AST Asynchronous Timing. Defines the length of the Timing signal (DU = 0) on IOM-2. If synchronous timing is selected (AST=0) the IPAC in LT-S mode will issue the timing request only in the C/I channel of the selected timeslot (C/I = 0000b). This mode is useful for applications where IOM-2 clock signals are not switched off. Here the IPAC can pass the TE initiated activation via C/I = 0000b in IOM-2 cannel 0 upstream to the U-interface device. In case IOM-2 clocks can be turned off during power-down or the LT-S IPAC is pin-strapped to a different timeslot than the U-interface device, synchronous timing signals will not succeed in waking the U-interface device. Under these circumstances asynchronous timing needs to be programmed (AST=1). Here the line DU is set to ZERO for a period long enough to wake any Uinterface device, independent of timeslot or clocks. Typically asynchronous timing is programmed for intelligent NT applications (IPAC pin-strapped to LT-S with NT state machine). Note: The asynchronous timing option is restricted to configurations with the IPAC operating with NT state machine (i.e., LT-S pin-strap & FSMM bit programmed). Closes the loop-back for B1 channel data close to the activated S/Tinterface (i.e., loop-back IOM-2 data) in LT-S mode. Closes the loop-back for B2 channel data close to the activated S/Tinterface (i.e., loop-back IOM-2 data) in LT-S mode. Close complete analog loop-back (2B+D) close to the S/T-interface. Corresponds to C/I = ARL. Transparency is optional. Operational in LT-S mode. Close the loop-back for B1 channel close to the IOM-2 interface (i.e. loopback S/T data). Transparent. IB1 and IB2 may be closed simultaneously. SB1 SB2 SC IB1 Semiconductor Group 76 11.97 PSB 2115 PSF 2115 Functional Description IB2 IB12 Close the loop-back for B2 channel close to the IOM-2 interface (i.e. loopback S/T data). Transparent. IB1 and IB2 may be closed simultaneously. Exchange B1 and B2 channels. IB1 and/or IB2 need to be programmed also. Loops back data received from S/T and interchanges it, i.e. B1 input (S/T) → B2 output (S/T) and vice versa. Semiconductor Group 77 11.97 PSB 2115 PSF 2115 Functional Description 2.4.4.4 MON-8 IOM®-2 Channel Register The features accessible via the IOM-2 Channel register allow to implement simple switching functions. These make the IPAC the ideal device for intelligent NT applications. Please refer also to the section “IOM-2 channel switching”. Two types of manipulation are possible: the transfer from the pin-strapped IOM-2 channel (0 … 7) into IOM-2 channel 0 and a change of the B1, B2 and D data source. Address: 3h B1L B1D B2L B2D DL 0 CIL CIH RD/WR Value after Reset: 00H B1L B1D Transfers the B1 channel from its pin-strapped location into IOM-2 channel 0. Direction of the B1 channel. The normal direction (input/output) of DU and DD depends on the mode and is shown in table 4 below. By setting B1D the direction for the B1 data channel is inverted. Transfers the B2 channel from its pin-strapped location into IOM-2 channel 0. Direction of the B2 channel. The normal direction (input/output) of DU and DD depends on the mode and is shown in table 4 below. By setting B2D the direction for the B2 data channel is inverted. Transfers the D-channel from its pin-strapped location into IOM-2 channel 0. C/I Channel location: The timeslot position of the C/I Channel can be programmed as “normal“ (LT-S and LT-T modes: pin strapped IOM-2 channel, TE mode: IOM-2 channel 0) or “fixed“ to IOM-2 channel 0 (regardless the selected mode). C/I Channel handling: Normally the C/I commands are read from the pinstrapped IOM-2 channel. With this bit programmed C/I channel access is only possible via the SM/CI register. B2L B2D DL CIL CIH Table 9 DU/DD Direction MODE0 MODE1 /EAW Transmit data on S DU (input) DU (input) DD (input) Receive data on S DD (output) DD (output) DU (output) TE-mode 0 EAW 1 0 LT-T mode 1 LT-S mode 1 Semiconductor Group 78 11.97 PSB 2115 PSF 2115 Functional Description 2.4.4.5 MON-8 SM/CI Register This multifeature register allows access to the C/I channel and controls the monitor timeout. Address: 4h CI3 CI2 CI1 CI0 TOD 0 0 0 RD/WR Value after Reset: X0H (X contains the C/I code) C/I Allows the user to access the C/I channel if the CIH bit in the IOM-2 register has been set previously. If the CIH bit was not programmed the content of the CI bits will be ignored and the IPAC will access the IOM-2 C/I channel. When reading the SM/CI register these bits will always return the current C/I indication (independent of CIH bit). Time Out Disable. Allows the user to disable the monitor time-out function. Refer to section “Monitor Timeout” for details. TOD Semiconductor Group 79 11.97 PSB 2115 PSF 2115 Functional Description 2.5 Layer-1 Functions for the S/T Interface The common functions in all operating modes are: – line transceiver functions for the S/T interface according to the electrical specifications of CCITT I.430; – conversion of the frame structure between IOM and S/T interface; – conversion from/to binary to/from pseudo-ternary code; – level detect. – Mode specific functions are: • receive timing recovery for point-to-point, passive bus and extended passive bus configuration; • S/T timing generation using IOM timing synchronous to system, or vice versa; • D-channel access control and priority handling; • D-channel echo bit generation by handling of the global echo bit; • activation/deactivation procedures, triggered by primitives received over the IOM C/I channel or by INFO's received from the line; • execution of test loops. The wiring configurations in user premises, in which the IPAC can be used, are illustrated in figure 24. Semiconductor Group 80 11.97 PSB 2115 PSF 2115 Functional Description _ < 1000 m1) IPAC TE TR TR IPAC LT-S _ < 1000 m 1) IOM IPAC LT-T 1) R TR TR SBCX NT Point-to-Point Configurations The maximum line attenuation tolerated by the IPAC is 15 dB at 96 kHz. IPAC LT-S _ < 100 m IOM TR _ < 10 m R TR SBCX NT Short Passive Bus IPAC TE1 TE8 IPAC IPAC _ < 500 m _ < 25 m LT-S IOM R TR _ < 10 m TR SBCX NT Extended Passive Bus TR : Terminating Resistor IPAC TE1 TE8 IPAC ITS09677 Figure 24 Wiring Configurations in User Premises Semiconductor Group 81 11.97 PSB 2115 PSF 2115 Functional Description 2.5.1 Analog Functions For both receive and transmit direction, a 2:1 transformer is used to connect the ISACS transceiver to the 4 wire S/T interface (CONF:AMP=0). As an option, the receiver can also be operated with a 1:1 transformer (CONF:AMP=1). The connections are shown in figure 25. Figure 25 Connection of the Line Transformers and Power Supply to the IPAC The external transformers are needed in both receive and transmit direction to provide for isolation and transform voltage levels according to CCITT recommendations. The equivalent circuits of the integrated receiver and transmitter are shown in figure 26. The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a current limited voltage source. Semiconductor Group 82 11.97 PSB 2115 PSF 2115 Functional Description IPAC 50 k Ω 40 k Ω + - IPAC SR1 SR2 2.1 V _ Ι < 13.4 mA SX1 40 k Ω 50 k Ω 2.1 V SX2 2.5 V (CONF : AMP = O) ITS09631 IPAC 50 k Ω 20 k Ω + - SR1 SR2 20 k Ω 50 k Ω 2.5 V (CONF : AMP = 1) ITS09678 Figure 26 Equivalent Internal Circuits of Receiver and Transmitter Stages The transmitter of the PSB 2115 IPAC is identical to that of the well known PEB 2086 ISAC-S, hence, the line interface circuitry should be similar. The external resistors (24 ... 33 Ω) are required in order to adjust the output voltage to the pulse mask (nominal 750 mV according CCITT I.430) on the one hand and in order to meet the output impedance of minimum 20 Ω (transmission of a binary zero according to CCITT I.430) on the other hand. The S-bus receiver of the PSB 2115 is designed as a threshold detector with adaptively switched threshold levels. Pin SR1 delivers 2.5 V as an output, which is the virtual ground of the input signal on pin SR2. The S-bus receiver of the PSB 2115 is symmetrical, which allows for a simple external circuitry and PCB layout to meet the I.430 receiver input impedance specification. Semiconductor Group 83 11.97 PSB 2115 PSF 2115 Functional Description 2.5.2 2.5.2.1 S/T Interface Circuitry S/T Interface Pre-Filter Compensation To compensate for the extra delay introduced into the receive and transmit path by the external circuit, the delay of the transmit data can be reduced by 260 ns (i.e. two oscillator cycles). Therefore PDS of the CONF register must be programmed to “1“. This delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of CCITT recommendation I.430 which specifies a phase deviation in the range of – 7% to + 15% of a bit period. 2.5.2.2 External Protection Circuitry The CCITT specification for both transmitter and receiver impedances in TEs results in a conflict with respect to external S-protection circuitry requirements: – To avoid destruction or malfunctioning of the S-device it is desirable to drain off even small overvoltages reliably. – To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs only, CCITT sections 8.5.1.2a and 8.6.1.1) the protection circuit must be dimensioned such that voltages below 2.4 V are not affected (1.2 V CCITT amplitude multiplied by transformer ratio 1:2). This requirement results from the fact that this test is to be performed with no supply voltage being connected to the TE. Therefore the second reference point for overvoltages VDD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is greater than the combined forward voltages of the diodes, a current exceeding the specified one may pass the protection circuit. Semiconductor Group 84 11.97 PSB 2115 PSF 2115 Functional Description The following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 kHz impedance tests. If the device is not used in TE or LT-T applications, the four diodes could be bridged and the 5.4 V Zener diode could be omitted. Protection Circuit for Transmitter TE and LT-T modes: SX1 20-40 Ω 5.6 V GND SX2 20-40 Ω ITS09632 2:1 VDD S Bus LT-S mode: SX1 20-40 Ω 2:1 GND SX2 20-40 Ω VDD S Bus ITS10289 Figure 27 External Circuitry for Transmitters Figure 27 illustrates the secondary protection circuit recommended for the transmitter. An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to VDD + 0.4 V. Via the two resistors (typ. 20 ... 40 Ω) the transmitted pulse amplitude is adjusted to comply with the requirements. Two mutually reversed diode paths (low capacitive diodes are recommended, e.g. 1N4151) protect the device against positive or negative overvoltages on both lines. The pin voltage range is increased from – 0.7 V to VDD + 3.5 V. The resulting forward voltage will prevent the protection circuit to become active if the 96 kHz test signal is applied while no supply voltage is present. In TE / LT-T modes the 5.6 V zener diode is provided to be completely on the safe side, however, system tests may reveal that it can be omitted. Semiconductor Group 85 11.97 PSB 2115 PSF 2115 Functional Description Protection Circuit for Receivers Figure 28 illustrates the external circuitry used in combination with a symmetrical receiver. Protection of symmetrical receivers is rather comfortable. Note: Capacitors are optional for noise reduction (up to 47 pF) Figure 28 External Circuitry for Symmetrical Receivers Between each receive line and the transformer a 10 kΩ resistor is used. This value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 kHz test, and the second one between input pin and protection diodes to limit the maximum input current ot the chip. With symmetrical receivers no difficulties regarding LCL measurements are observed; compensation networks thus are obsolete. In order to comply to the physical requirements of CCITT recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compability (EMC), the IPAC needs additional circuitry. Semiconductor Group 86 11.97 PSB 2115 PSF 2115 Functional Description 2.5.3 2.5.3.1 Receiver Functions Receiver Characteristics In order to additionally reduce the bit error rate in severe conditions, the IPAC performs oversampling of the received signal and uses majority decision logic. The receiver consists of a differential to single ended input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. The following figure 29 describes the functional blocks of the receiver (for receiver tansformer ratio 2:1). The equivalent internal circuit for transformer ratio 1:1 (CONF:AMP=1) is shown in figure 26. CONF:AMP=0 Figure 29 Receiver Circuit The input stage works together with external 10 kΩ resistors to match the input voltage to the internal thresholds. The data detection thresholds are chosen to 35 % of the peak voltage to increase the performance in extended passive bus configurations. However they never go below 85 mV with respect to the line signal level. This guarantees a maximum line attenuation of at least 13 dB in point-to-point configurations with a margin of more than 70 mVpp with respect to the specified 100 mVpp noise. Semiconductor Group 87 11.97 PSB 2115 PSF 2115 Functional Description Figure 30 Receiver Thresholds The peak detector requires maximum 2 µs to reach the peak value while storing the peak level for at least 250 µs (RC > 1 ms). The additional level detector for power up/down control works with fixed thresholds at 100 mV. The level detector monitors the line input signals to detect whether an INFO is present. In TE and LT-T mode, when closing an analog loop, it is therefore possible to indicate an incoming signal during activated loop. In LT-S analog loop-back mode the level detector monitors its own loop signal and an incoming signal is not recognized. 2.5.3.2 Level Detection Power Down (TE mode) If CONF:CFS is set to “0“, the clocks are also provided in power down state, whereas if CFS is set to “1“, only an analog level detector is active in power down state. All clocks, including the IOM interface, are stopped. The data lines are "high", whereas the clocks are "low". An activation initiated from the exchange side (Info 2 on S-bus detected) will have the consequence that a clock signal is provided automatically. From the terminal side an activation must be started by setting and resetting the SPUbit in the SPCR register and writing TIM to CIX0 or by resetting CFS=0. Semiconductor Group 88 11.97 PSB 2115 PSF 2115 Functional Description 2.5.4 S/T Transmitter Disable The transmitter of the S/T interface can be disabled by configuration (see figure 31). By default (SCFG:TXD=0) both the S/T receiver and transmitter are active, but in order to reduce power consumption, the transmitter can be disabled (SCFG:TXD=1) separately. In power down mode the power consumption is reduced to a minimum and the IPAC recognizes the activation of the S/T interface (incoming call). With several terminals connected to the S/T interface, another terminal may keep the interface activated although the IPAC does not establish a connection. In this case the IPAC receiver will monitor for incoming calls while the transmitter is disabled, thus reducing power consumption. Figure 31 Disabling of S/T Transmitter Semiconductor Group 89 11.97 PSB 2115 PSF 2115 Functional Description 2.5.5 LT-S In LT-S mode, the 192-kHz transmit bit clock is synchronized to the IOM clock. In the receive direction two cases have to be distinguished depending on whether a bus or a point-to-point operation is programmed in MON-8 Configuration Register (see figure 32): – In a bus configuration (C/W/P=0), the 192-kHz receive bit clock is identical to the transmit bit clock, shifted by 4.6 µs with respect to the transmit edge. According to CCITT I.430, the receive frame is shifted by two bits with respect to the transmit frame. – In a point-to-point or extended passive bus configuration (C/W/P=1), the 192-kHz receive bit clock is recovered from the receive data stream on the S interface. According to CCITT I.430, the receive frame can be shifted by 2-8 bits with respect to the transmit frame at the LT-S. However, note that other shifts are also allowed by the IPAC (including 0). Timing Recovery LT-S Mode PLL MP DCL FSC PLL PP ITS09633 MP: Receive clock for bus configuration PP: Receive clock for point-to-point configuration Figure 32 Clock System of the IPAC in LT-S Mode Semiconductor Group 90 11.97 PSB 2115 PSF 2115 Functional Description TE and LT-T In TE/LT-T applications, the transmit and receive bit clocks are derived, with the help of the DPLL, from the S interface receive data stream. The received signal is sampled several times inside the derived receive clock period, and a majority logic is used to additionally reduce bit error rate in severe conditions (see chapter 2.5.3). The transmit frame is shifted by two bits with respect to the received frame. In TE mode the output clocks (DCL, FSC etc.) are synchronous to the S interface timing. In LT-T mode the IPAC provides a 1.536 MHz clock on the SCLK pin synchronous to the S interface. This can be used as the reference clock for an external PLL which provides the FSC and DCL clocks. Since the IPAC provides different dividers, the clocks can also be generated internally from the DCL input connected to SCLK (see chapter 2.8.2.2). TE Mode PLL DCL FSC BCL LT-T Mode Slip Detector PLL FSC "NT2" Clock Generator DCL (PLL) SCLK Reference Clock ITS09634 Figure 33 Clock System of the IPAC in TE and LT-T Modes 91 11.97 Semiconductor Group PSB 2115 PSF 2115 Functional Description 2.5.6 Activation/Deactivation An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT. Setting of the IPAC for CTS Test Procedures for Frame Alignment The IPAC needs to be programmed for multiframe operation with the Q-bits set to "1". MON-8 Configuration Register : MFD = 0 MON-1 Command/Message = 0001 1111B (1Fh) Frame Alignment Tests For frame alignment tests the following settings are valid: • n=2 • m = 3 or 4 Semiconductor Group 92 11.97 PSB 2115 PSF 2115 Functional Description 2.5.7 Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as soon as the layer 1 is activated (see figure 34). Figure 34 ACL Indication of Activated Layer 1 By default (PCFG:ACL=0) the state of layer 1 is indicated at pin ACL. If the automatic indication of the activated layer 1 is not required, the state on pin ACL can also be programmed by the host (see figure 35). If PCFG:ACL=1 the LED on pin ACL can be switched on (PCFG:LED=1) and off (PCFG:LED=0) by the host. Figure 35 ACL Configuration Semiconductor Group 93 11.97 PSB 2115 PSF 2115 Functional Description 2.5.8 Terminal Specific Functions (TE mode only) In addition to the standard functions supporting the ISDN basic access, the IPAC contains optional functions, useful in various terminal configurations. The terminal specific functions are enabled by setting bit TSF (STCR register) to “1”. This has two effects: • In TE mode the MODE1/EAW line is defined as External Awake input, but additionally this function is only enabled by setting STCR:TSF=1 • Second, the interrupts SAW and WOV (EXIRD register) are enabled: – SAW (Subscriber Awake) generated by a falling edge on the EAW line – WOV (Watchdog Timer Overflow) generated by the watchdog timer. This occurs when the processor fails to write two consecutive bit patterns in ADF1: ADF1 WTC1 WTC2 Watchdog Timer Control 1,0. The WTC1 and WTC2 bits have to be successively written in the following manner within 128 ms: WTC1 1. 2. 1 0 WTC2 0 1 As a result the watchdog timer is reset and restarted. Otherwise a WOV is generated. Deactivating the terminal specific functions is only possible with a hardware reset. Having enabled the terminal specific functions via TSF = 1, the user can make the IPAC generate a reset signal by programming the Reset Source Select RSS bit (CIX0 register), as follows: 0 → A reset signal is generated as a result of – a falling edge on the EAW line (subscriber awake) – a C/I code change (exchange awake). – layer-1 part leaves power down state and supplies DCL and FSC clocks. A falling edge on the EAW line also forces the DU line of the IOM interface to zero. Note: In case the layer-1 part of the IPAC is switched off (CONF:TEM=1), a falling edge on EAW should normally induce the attached layer-1 device to leave the power down state and supply clocking to IPAC via DCL and FSC. A corresponding interrupt status (CIC or SAW) is also generated. Semiconductor Group 94 11.97 PSB 2115 PSF 2115 Functional Description 1 → A reset signal is generated as a result of the expiration of the watchdog timer (indicated by the WOV interrupt status). Note: The watchdog timer is not running when the IPAC is in the power-down state (IOM not clocked). Note: Bit RSS has a significance only if terminal specific functions are activated (TSF=1). The RSS bit should be set to “1” by the user when the IPAC is in power-up to prevent an edge on the EAW line or a change in the C/I code from generating a reset pulse. Switching RSS from 0 to 1 or from 1 to 0 resets the watchdog timer. The reset pulse generated by the IPAC (output via RES pin) has a pulse width of 5 ms and is an active high signal. It has no internal reset function. Before and after this reset pulse the RES pin is input. Semiconductor Group 95 11.97 PSB 2115 PSF 2115 Functional Description 2.5.9 2.5.9.1 Test Functions B-Channel Test Mode To provide for fast and efficient testing, the IPAC can be operated in the test mode by setting the TLP bit in the MODEB register. The serial data input and output (DU – DD) are connected generating a local loopback between XFIFOB and RFIFOB. The DD input is ignored and DU remains active. As a result, the user can perform a simple test of the HDLC channels of the IPAC. 2.5.9.2 D-Channel and S/T Interface Test Mode The IPAC provides several test and diagnostic functions for D-Channel and S/T interface which can be grouped as follows: – digital loop via TLP (Test Loop, SPCR register) command bit (figure 36): TX-path of layer 2 is internally connected with RX-path of layer 2, output from layer 1 (S/T) on DD is ignored; this is used for testing D-channel functionality excluding layer 1 (loopback between XFIFOD and RFIFOD) and excluding the B-channel controller; Figure 36 Layer 2 Test Loops – test of layer-2 functions while disabling all layer-1 functions and pins associated with them (including clocking in TE mode), via bit TEM (Test Mode in CONF register); the IPAC is then fully compatible to the ICC (PEB 2070) seen at the IOM interface. Semiconductor Group 96 11.97 PSB 2115 PSF 2115 Functional Description – loop at the analog end of the S interface; TE / LT-T mode Test loop 3 is activated with the C/I channel command Activate Request Loop (ARL). An S interface is not required since INFO3 is looped back internally to the receiver. When the receiver has synchronized itself to this signal, the message "Test Indication" (or "Awake Test Indication") is delivered in the C/I channel. No signal is transmitted over the S interface. In the test loop mode the S interface awake detector is enabled, i.e. if a level is detected (e.g. Info 2/Info 4) this will be reported by the Awake Test Indication (ATI). The loop function is not effected by this condition and the internally generated 192kHz line clock does not depend on the signal received at the S interface. LT-S mode Test loop 2 is likewise activated over the IOM interface with Activate Request Loop (ARL). No S line is required. INFO4 is looped back internally to the receiver and also sent to the S interface. When the receiver is synchronized, the message "AIU" is sent in the C/I channel. In the test loop mode the S interface awake detector is disabled, and echo bits are set to logical "0". – special loops are programmed via C2C1-0 and C1C1-0 bits (register SPCR) – transmission of special test signals on the S/T interface according to the modified AMI code are initiated via a C/I command written in CIX0 register (cf. chapter 3.6). Two kinds of test signals may be sent by the IPAC: • single pulses and • continuous pulses. The single pulses are of alternating polarity, one S interface bit period wide, 0.25 ms apart, with a repetition frequency of 2 kHz. Single pulses can be sent in all applications. The corresponding C/I command in TE, LT-S and LT-T applications is SSZ (Send single zeros). Continuous pulses are likewise of alternating polarity, one S-interface bit period wide, but they are sent continuously. The repetition frequency is 96 kHz. Continuous pulses may be transmitted in all applications. This test mode is entered in LT-S, LT-T and TE applications with the C/I command SCZ. Semiconductor Group 97 11.97 PSB 2115 PSF 2115 Functional Description 2.6 2.6.1 Microprocessor Interface Operation Modes The IPAC is programmed via an 8-bit parallel microprocessor interface. Easy and fast microprocessor access is provided by 8-bit address decoding on the chip. The IPAC provides three types of µP buses (see table 10), which are selected via pin ALE: Table 10 (1) (2) Bus Operation Modes Motorola type with control signals CS, R/W, DS Siemens/Intel non-multiplexed bus type with control signals CS, WR, RD Siemens/Intel multiplexed address/data bus type with control signals CS, WR, RD, ALE ALE tied to VDD ALE tied to VSS (3) Edge on ALE The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Note: If the multiplexed address/data bus type (3) is selected, the unused address pins A0-A7 must be tied to VDD. Register Addressing Modes The common way to read write registers is for non-multiplexed mode to set the register address to the address bus and then access the register location. In multiplexed mode, the address on the address/data bus is latched in, before a read or write access to the register is performed. The IPAC provides two different ways to access its register contents. In the direct mode the register address to be read or written is directly set on the bus in the way described above. This mode is selected, if the address select mode pin AMODE is set to 0. Semiconductor Group 98 11.97 PSB 2115 PSF 2115 Functional Description As a second option, the IPAC allows for indirect access of the registers (AMODE=1). Only the LSB of the address line is used to select either the ADDRESS register or the DATA register. The host writes the register address to the ADDRESS register (write only register), before it reads/writes data from/to the corresponding register location through the DATA register. Figure 37 shows both register addressing modes. In indirect address mode (AMOD=1) all other address lines except A0 are not evaluated by the IPAC. They may be tied to log. ’0’ or ’1’, however they must not be left open. Figure 37 Indirect Register Address Mode 2.6.2 Register Set The communication between the host and the IPAC is done via a set of directly or indirectly accessible 8-bit registers. The host sets the operating modes, controls function sequences and gets status information by writing or reading these registers (Command/ Status transfer). Each of the two B-channels of the IPAC is controlled via an equal, but totally independent register file (channel A and channel B). Additional registers are available for D-channel control, the PCM and the Auxiliary interface. Semiconductor Group 99 11.97 PSB 2115 PSF 2115 Functional Description 2.6.3 Data Transfer Mode Data transfer between the system memory and the IPAC for both transmit and receive direction is controlled either by interrupts (Interrupt Mode), or independently from host interaction using the IPAC’s 4-channel DMA interface (DMA Mode). DMA transfer is available for transfer of B-channel data only and not for D-channel data. After RESET, the IPAC operates in Interrupt Mode, where data transfer must be done by the host. The user selects the DMA Mode by setting the DMA bit in a register. In TE mode both channels can independently be operated in either Interrupt or DMA Mode (e.g. Channel A in DMA mode, Channel B in interrupt mode). In LT-S and LT-T mode, only channel B can be operated either in Interrupt or DMA mode, channel A can only be operated in Interrupt mode. 2.6.4 Interrupt Interface Special events in the IPAC are indicated by means of a single interrupt output, which requests the host to read status information from the IPAC or transfer data from/to the IPAC. Two interrupt lines with invers polarity are available to meet the requirements of different kinds of applications. A low active interrupt output INT (pin 2) can be connected to a pull up resistor together with further interrupt sources on the system. This pin is available in all modes. The inverted interrupt signal is available in TE mode only if pin AUX2 (pin 33) is programmed as output (see chapter 2.8.1). This may be used in single chip solutions (e.g. PC cards) with only one interrupt source that can directly be connected to the ISA bus. This high active interrupt line INT is not available in LT-modes and in TE-mode with AUX2 used as input (default after reset). IPAC TE-Mode Interrupt 33 INT IPAC LT-Modes Interrupt 2 INT 2115_3 2 INT Figure 38 High and Low Active Interrupt Output Since only one interrupt request output is provided, the cause of an interrupt must be determined by the host reading the IPAC’s interrupt status registers. The structure of the interrupt status registers is shown in figure 39. Semiconductor Group 100 11.97 PSB 2115 PSF 2115 Functional Description Figure 39 IPAC Interrupt Status Registers Two interrupt indications can be read directly from the ISTA register and another six interrupt indications from separate interrupt status registers and extended interrupt registers for the B-channels (ISTAB, EXIRB, each for B-Channel A and B) and the Dchannel (ISTAD, EXIRD). Each interrupt source can individually be disabled by setting the corresponding mask bit in the interrupt mask register. An overview of the interrupt sources is given below, a detailed description of the interrupt structure is provided in chapter 3.3. Semiconductor Group 101 11.97 PSB 2115 PSF 2115 Functional Description Table 11 Bit Auxiliary Interface Interrupts Interrupt External Interrupt 0/1 Register INT0/1 ISTA Table 12 Bit ICD EXD D-Channel Interrupts Interrupt ISTA D-Channel EXIR D-Channel Register ISTA ISTA Receive Interrupts: Bit RPF RME RFO Register ISTAD ISTAD EXIRD Interrupt Receive Pool Full Receive Message End Receive Frame Overflow Transmit Interrupts: Bit XPR XMR XDU RSC Register ISTAD EXIRD EXIRD ISTAD Interrupt Transmit Pool Ready Transmit Message Repeat Transmit Data Underrun Receive Status Change Special Condition Interrupts: Bit TIN CIC SIN TIN2 SOV Register ISTAD ISTAD ISTAD ISTAD EXIRD Interrupt Timer Interrupt C/I-Channel Change Synchronous Transfer Interrupt Timer 2 Interrupt Synchronous Transfer Overflow 102 11.97 Semiconductor Group PSB 2115 PSF 2115 Functional Description Table 12 MOS SAW WOV D-Channel Interrupts MONITOR Status Subscriber Awake Watchdog Timer Overflow EXIRD EXIRD EXIRD Table 13 Bit ICA/ ICB EXA/ EXB B-Channel Interrupts Interrupt ISTA B-Channel A/B EXIR B-Channel A/B Register ISTA ISTA Receive Interrupts: Bit RPF RME RFO RFS Register ISTAB ISTAB EXIRB EXIRB Interrupt Receive Pool Full Receive Message End Receive Frame Overflow Receive Frame Start Transmit Interrupts: Bit XPR XMR XDU Register ISTAB EXIRB EXIRB Interrupt Transmit Pool Ready Transmit Message Repeat Transmit Data Underrun Semiconductor Group 103 11.97 PSB 2115 PSF 2115 Functional Description 2.6.5 DMA Interface To support efficient data exchange between system memory and the FIFOs an additional DMA-interface is provided. The FIFOs have separate DMA-request lines for each direction (DRQRA/B for Receive FIFO, DRQTA/B for Transmit FIFO) and a common DMA-acknowledge input for receive and transmit direction (DACKA/B). The DMA-controller has to operate in the level triggered, demand transfer mode. If the DMAcontroller provides a DMA-acknowledge signal, each bus cycle implicitly selects the top of FIFO and neither address nor chip select is evaluated. If no DACKA/B signal is supplied, normal read/write operations (providing addresses) must be performed (memory to memory transfer). In the paragraphs below the following abbreviations are used: DRQR = DRQRA or DRQRB DRQT = DRQTA or DRQTB DACKA or DACKB DACK = The IPAC activates the DRQT and DRQR-lines as long as data transfers are needed from/to the specific FIFOs. A special timing scheme is implemented to guarantee safe DMA-transfers regardless of DMA-controller speed. If in transmit direction a DMA-transfer of n bytes is necessary (n < 64 or the remainder of a long message), the DRQT-pin is active up to the rising edge of WR of DMA-transfer (n-1). If n > 64 the same behavior applies additionally to transfers 63, 127, …, ((k × 64) - 1). DRQT is activated again with the next rising edge of DACK, if there are further bytes to transfer (figure 41). When a fast DMA-controller is used (> 16 MHz), byte n (or bytes k × 64) will be transferred before DRQT is deactivated from the IPAC. In this case pin DRQT is not activated any more up to the next block transfer (figure 40). Figure 40 Timing Diagram for DMA-Transfers (fast) Transmit (n < 64, remainder of a long message or n = k × 64) Semiconductor Group 104 11.97 PSB 2115 PSF 2115 Functional Description Figure 41 Timing Diagram for DMA-Transfers (slow) Transmit (n < 64, remainder of a long message or n = k × 64) In receive direction the behavior of pin DRQR is implemented correspondingly. If k × 64 bytes are transferred, pin DRQR is deactivated with the rising edge of RD of DMAtransfer ((k × 64) − 1) and it is activated again with the next rising edge of DACK, if there are further bytes to transfer (figure 43). When a fast DMA-controller is used (> 16 MHz), byte n (or bytes k × 64) will be transferred immediately (figure 42). However, if 4, 8, 16, 32 or 64 bytes have to be transferred (only these discrete values are possible in receive direction), DRQR is deactivated with the falling edge of RD (figure 44). Figure 42 Timing Diagram for DMA-Transfer (fast) Receive (n = k × 64) Semiconductor Group 105 11.97 PSB 2115 PSF 2115 Functional Description Figure 43 Timing Diagram for DMA-Transfers (slow) Receive (n = k × 64) Figure 44 Timing Diagram for DMA-Transfers (slow or fast) Receive (n = 4, 8, 16 or 32) Generally it is the responsibility of the DMA-controller to perform the correct bus cycles as long as a request line is active. Figure 45 DMA-Transfers with Pulsed DACK (read or write) Semiconductor Group 106 11.97 PSB 2115 PSF 2115 Functional Description If a pulsed DACK-signal is used the DRQR/DRQT-signal will be deactivated with the rising edge of RD/WR-operation (n-1) but activated again with the following rising edge of DACK. With the next falling edge of DACK (DACK ‘n’) it will be deactivated again (see figure 45). This behaviour might cause a short negative pulse on the DRQR/DRQT-line depending on the timing of DACK vs. RD/WR. Semiconductor Group 107 11.97 PSB 2115 PSF 2115 Functional Description 2.6.6 FIFO Structure for B-Channels In both transmit and receive direction 128 byte deep FIFO’s are provided for the intermediate storage of B-Channel data between the serial interface and the CPU interface. The FIFO’s are divided into two halves of 64 bytes, where only one half is accessible to the CPU at any time. The organization of the Receive FIFO (RFIFOB) is such, that in the case of a frame at most 128 bytes long, the whole frame may be stored in the RFIFOB. After the first 64 bytes have been received, the IPAC prompts to read the 64 byte block by means of interrupt or DMA request (RPF interrupt or activation of DRQR line). This block remains in the RFIFOB until a confirmation is given to the IPAC acknowledging the transfer of the data block. This confirmation is either a RMC (Receive Message Complete) command via the CMDRB register in Interrupt Mode or is implicitely achieved in DMA mode after 64 byte have been read from the RFIFOB. As a result, it’s possible to read out the data block any number of times until the RMC command is issued. The configuration of the RFIFO prior to and after acknowledgment is shown in figure 46. 2115_1 Figure 46 Configuration of RFIFOB (Long Frames) Semiconductor Group 108 11.97 PSB 2115 PSF 2115 Functional Description If frames longer than 128 bytes are received, the device will repeatedly prompt to read out 64 byte data blocks via interrupt. In the case of several shorter frames, up to 17 may be stored in the IPAC. If the accessible half of the RFIFOB contains a frame i (or the last part of frame i), up to 16 short frames may be stored in the other half (i + 1, … , i + n) meanwhile, prior to frame i being fetched from the RFIFOB. This is illustrated in figure 47. For a description of a transmit and receive sequence please refer to chapter 3.4. 2115_1 Figure 47 Configuration of RFIFOB (Short Frames) Note: The number of 17 frames applies e.g. for the IPAC operating in the non-auto mode (address recognition), and short frames only containing the HDLC Address and Control field are received. Since the address is not stored, the control field is always stored first in the RFIFOB, and an additional status byte is always appended at the end of each frame in the RFIFOB, these frames will occupy two bytes. Semiconductor Group 109 11.97 PSB 2115 PSF 2115 Functional Description 2.6.7 Timer Modes TIMR1 - Timer 1 Register (Adr. A3H) TIMR2 - Timer 2 Register (Adr. CCH) Timer 1 provides two modes of operation which can be selected by the ’Timer Mode’ bit in MODED register (figure 48): The IPAC provides two timers which can be used for various purposes: Figure 48 Timer 1 Register 1. Internal Timer Mode (MODED:TMD=1) In the internal mode the timer is used internally by the IPAC D-channel controller for timeout and retry conditions for handling of LAPD/HDLC protocol, i.e. this mode is only used in automode. The number of S commands ’N1’ which are transmitted autonomously by the IPAC after expiration of time period T1 (see note) is indicated in parameter CNT. The internal prodedure is started after begin of an I-frame transmission or after Semiconductor Group 110 11.97 PSB 2115 PSF 2115 Functional Description an ’RNR’ S-frame has been received. A timer interrupt (ISTAD:TIN) is generated after the last retry. The procedure is stopped when either a TIN interrupt is generated or the TIMR1 register is written or when a positive or negative acknowledgement is received. CNT can have any value up to 6, with CNT=7 the number of retries is unlimited. A detailed description for the use of the internal timer mode is provided with the automode description (see chapter 2.2.1.3). Note: The time period T1 is determined by the parameter VALUE (chapter 4.3.8). 2. External Timer Mode (MODED:TMD=0) In the external mode the host controls the timer by setting bit CMDRD:STI to start the timer and by writting register TIMR1 to stop the timer. After time period T2 an interrupt (ISTAD:TIN) is generated continuously (if CNT=7) or once (if CNT 1 mode 3 SAP1,SAP2,SAPG – Semiconductor Group 242 11.97 PSB 2115 PSF 2115 Detailed Register Description Note: SAP1, SAP2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); SAPG = fixed value FC / FEH. TEI1, TEI2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; TEIG = fixed value FFH TMD ...Timer Mode Sets the operating mode of the IPAC timer 1. In the external mode (0) the timer is controlled by the processor. It is started by setting the STI bit in CMDRD and it is stopped by a write of the TIMR1 register. In the internal mode (1) the timer is used internally by the IPAC for timeout and retry conditions (handling of LAPD/HDLC protocol in auto mode). RAC ... Receiver Active The HDLC receiver is activated when this bit is set to “1”. DIM2-0 ... Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD) according to following table: Table 27 IOM®-2 Modes 000 x 001 x x x x 010 011 100...111 Characteristics DIM2, DIM1, DIM0 Last octet of IOM channel 2 used for TIC bus access Stop/go bit evaluated for D-channel access handling Reserved Applications TE mode LT-T mode with D-channel collision resolution LT-T, LT-S modes with transparent D-channel x x x x Semiconductor Group 243 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.8 TIMR1 - Timer 1 Register (Read/Write) Value after reset: (not defined, previous value) 7 TIMR1 CNT 5 4 VALUE 0 (A3) CNT ... The meaning depends on the selected timer mode (MODED:TMD): • Internal Timer Mode (TMD=1) CNT indicates the maximum number of S commands “N1” which are transmitted autonomously by the IPAC after expiration of time period T1 (retry, according to HDLC). The internal procedure will be started in automode: • after start of an I-frame transmission or • after an ’RNR’ S-frame has been received After the last retry a timer interrupt (TIN-bit in ISTAD) is generated. The timer procedure will be stopped when • a TIN interrupt is generated. The time between the start of an I-frame transmission or reception of an ’RNR’ S-frame and the generation of a TIN interrupt is equal to: ( CNT + 1 ) x T1 • or the TIMR1 is written • or a positive or negative acknowledgment has been received. Note: The maximum value of CNT can be 6. If CNT is set to 7, the number of retries is unlimited. • External Timer Mode (TMD=0) CNT together with VALUE determine the time period T2 after which a TIN interrupt will be generated in the normal case: T2 = CNT x 2.048 sec + T1 with T1 = ( VALUE+1 ) x 0.064 sec When TLP=1 (test loop activated, SPCR register): T2 = 16348 x CNT x DCL + T1 with T1 = 512 x ( VALUE+1 ) x DCL DCL denotes the period of the DCL clock. The timer can be started by setting the STI-bit in CMDRD and will be stopped when a TIN interrupt is generated or the TIMR1 register is written. Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of T1. VALUE ... Determines the time period T1 T1 = ( VALUE + 1 ) x 0.064 sec (SPCR:TLP = 0, normal mode) T1 = 512 x ( VALUE + 1 ) x DCL (SPCR:TLP = 1, test mode) Semiconductor Group 244 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.9 EXIRD - Extended Interrupt Register (Read) Value after reset: 00H. 7 EXIRD XMR XDU PCE RFO SOV MOS SAW 0 WOV (A4) XMR ... Transmit Message Repeat The transmission of the last frame has to be repeated because: – the IPAC has received a negative acknowledgment to an I frame in auto mode (according to HDLC/LAPD) – or a collision on the S bus has been detected after the 32nd data byte of a transmit frame. XDU ... Transmit Data Underrun The current transmission of a frame is aborted by transmitting seven “1’s” because the XFIFOD holds no further data. This interrupt occurs whenever the processor has failed to respond to an XPR interrupt (ISTAD register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete. When a XMR or an XDU interrupt is generated, it is not possible to send transparent frames or I frames until the interrupt has been acknowledged by reading EXIR. PCE ... Protocol Error (Used in auto mode only) A protocol error has been detected in auto mode due to a received – – – – S or I frame with an incorrect sequence number N (R) or S frame containing an I field or I frame which is not a command or S-frame with an undefined control field. RFO ... Receive Frame Overflow The received data of a frame could not be stored, because the RFIFOD is occupied. The whole message is lost. This interrupt can be used for statistical purposes and indicates that the processor does not respond quickly enough to an RPF or RME interrupt (ISTAD). SOV ... Synchronous Transfer Overflow The synchronous transfer programmed in STCR has not been acknowledged in time via the SC0/SC1 bit. Semiconductor Group 245 11.97 PSB 2115 PSF 2115 Detailed Register Description MOS ... MONITOR Status A change in the MONITOR Status Register (MOSR) has occured. SAW ... Subscriber Awake Used only in TE mode (MODE0=0) and if terminal specific functions are enabled (STCR:TSF=1). Indicates that a falling edge on EAW line has been detected. WOV ... Watchdog Timer Overflow Used only if terminal specific functions are enabled (STCR:TSF=1). Signals the expiration of the watchdog timer, which means that the processor has failed to set the watchdog timer control bits WTC1 and WTC2 (ADF1 register) in the correct manner. A reset pulse has been generated by the IPAC. Semiconductor Group 246 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.10 XAD1 - Transmit Address 1 (Write) Value after reset: (not defined) 7 XAD1 Used in auto mode only. XAD1 contains a programmable address byte which is appended automatically to the frame by the IPAC in auto mode. Depending on the selected address mode XAD1 is interpreted as follows: 2-Byte Address Field XAD1 is the high byte (SAPI in the ISDN) of the 2-byte address field. Bit 1 is interpreted as the command/response bit “C/R”. It is automatically generated by the IPAC following the rules of ISDN LAPD protocol and the CRI bit value in SAP1 register. Bit 1 has to be set to “0”. C/R Bit Command 0 1 Response 1 0 Transmitting End subscriber network CRI Bit 0 0 0 (A4) In the ISDN LAPD the address field extension bit “EA”, i.e. bit 0 of XAD1 has to be set to “0”. or 1-Byte Address Field According to the X.25 LAPB protocol, XAD1 is the address of a command frame. Note: In standard ISDN applications only 2-byte address fields are used. Semiconductor Group 247 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.11 XAD2 - Transmit Address 1 (Write) Value after reset: (not defined) 7 XAD2 Used in auto mode only. XAD2 contains the second programmable address byte, whose function depends on the selected address mode: 2-Byte Address Field XAD2 is the low byte (TEI in the ISDN) of the 2-byte address field. or 1-Byte Address Field According to the X.25 LAPB protocol, XAD2 is the address of a response frame. 0 (A5) Note: See note to XAD1 register description. 4.3.12 RBCLD - Receive Frame Byte Count Low for D-Channel (Read) Value after reset: 00H 7 RBCLD RBC7 0 RBC0 (A5) RBC7-0 ... Receive Byte Count Eight least significant bits of the total number of bytes in a received message. Bits RBC4-0 indicate the length of a data block currently available in the RFIFOD, the other bits (together with RBCHD) indicate the number of whole 32-byte blocks received. If exactly 32 bytes are received RBCLD holds the value 20H. Semiconductor Group 248 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.13 SAPR - Received SAPI Register (Read) Value after reset: (not defined) 7 SAPR 0 (A6) When transparent mode 1 is selected SAPR contains the value of the first address byte of a receive frame. 4.3.14 SAP1 - SAPI1 Register (Write) Value after reset: (not defined) 7 SAP1 SAPI1 ... SAPI1 value Value of the first programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD protocol. CRI ... Command/Response Interpretation CRI defines the end of the ISDN user-network interface the IPAC is used on, for the correct identification of “Command” and “Response” frames. Depending on the value of CRI the C/R-bit will be interpreted by the IPAC, when receiving frames in auto mode, as follows: C/R Bit CRI Bit 0 1 Receiving End subscriber network Command 1 0 Response 0 1 SAPI1 CRI 0 0 (A6) For transmitting frames in auto mode, the C/R-bit manipulation will also be done automatically, depending on the value of the CRI-bit (refer to XAD1 register description). In message transfer modes with SAPI address recognition the first received address byte is compared with the programmable values in SAP1, SAP2 and the fixed group SAPI. In 1-byte address mode, the CRI-bit is to be set to “0”. Semiconductor Group 249 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.15 SAP2 - SAPI2 Register (Write) Value after reset: (not defined) 7 SAP2 SAPI2 ... SAPI2 value Value of the second programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD-protocol. MCS ... Modulo Count Select. Used in auto-mode only. This bit determines the HDLC-control field format as follows: 0: One-byte control field (modulo 8) 1: Two-byte control field (modulo 128) SAPI2 MCS 0 0 (A7) 4.3.16 RSTAD - Receive Status Register (Read) Value after reset: (not defined) 7 RSTAD RDA RDO CRC RAB SA1 SA0 C/R 0 TA (A7) RDA ... Receive Data A “1” indicates that data is available in the RFIFOD. After an RME-interrupt, a “0” in this bit means that data is available in the internal registers RHCRD or SAPR only (e.g. Sframe). See also RHCRD-register description table. RDO ... Receive Data Overflow If RDO=1, at least one byte of the frame has been lost, because it could not be stored in RFIFOD. CRC ... CRC Check The CRC is correct (1) or incorrect (0). RAB ... Receive Message Aborted The receive message was aborted by the remote station (1), i.e. a sequence of seven 1’s was detected before a closing flag. Semiconductor Group 250 11.97 PSB 2115 PSF 2115 Detailed Register Description SA1-0 ... SAPI Address Identification TA ... TEI Address Identification SA1-0 are significant in auto-mode and non-auto-mode with a two-byte address field, as well as in transparent mode 3. TA is significant in all modes except in transparent modes 2 and 3. Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value FC/FEH), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG of value FFH), are available for address comparison. The result of the address comparison is given by SA1-0 and TA, as follows: Address Match with SA1 Number of Address Bytes = 1 x x 0 0 0 0 1 1 1 SA0 x x 0 0 1 1 0 0 1 TA 0 1 0 1 0 1 0 1 x 1st Byte TEI2 TEI1 SAP2 SAP2 SAPG SAPG SAP1 SAP1 2nd Byte TEIG TEI2 TEIG TEI1 or TEI2 TEIG TEI1 reserved Number of address Bytes=2 Note: If the SAPI values programmed to SAP1 and SAP2 are identical the reception of a frame with SAP2/TEI2 results in the indication SA1=1, SA0=0, TA=1. Normally RSTAD should be read by the processor after an RME-interrupt in order to determine the status of the received frame. The contents of RSTAD are valid only after an RME-interrupt, and remain so until the frame is acknowledged via the RMC-bit. C/R ... Command/Response The C/R-bit identifies a receive frame as either a command or a response, according to the LAPD-rules: Command 0 1 Response 1 0 Direction Subscriber to network Network to subscriber Semiconductor Group 251 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.17 TEI1 - TEI1 Register 1 (Write) Value after reset: (not defined) 7 TEI1 TEI1 0 EA (A8) TEI1 ... Terminal Endpoint Identifier EA ... Address field Extension bit This bit is set to “1” according to HDLC/LAPD. In all message transfer modes except in transparent modes 2 and 3, TEI1 is used by the IPAC for address recognition. In the case of a two-byte address field, it contains the value of the first programmable Terminal Endpoint Identifier according to the ISDN LAPD-protocol. In the auto-mode with a two-byte address field, numbered frames with the address SAPI1-TEI1 are handled autonomously by the IPAC according to the LAPD-protocol. Note: If the value FFH is programmed in TEI1, received numbered frames with address SAPI1-TEI1 (SAPI1-TEIG) are not handled autonomously by the IPAC. In auto and non-auto-modes with one-byte address field, TEI1 is a command address, according to X.25 LAPB. 4.3.18 TEI2 - TEI2 Register (Write) Value after reset: (not defined) 7 TEI2 TEI2 0 EA (A9) TEI2 ... Terminal Endpoint Identifier EA ... Address field Extension bit This bit is to be set to “1” according to HDLC/LAPD. In all message transfer modes except in transparent modes 2 and 3, TEI2 is used by the IPAC for address recognition. In the case of a two-byte address field, it contains the value of the second programmable Terminal Endpoint Identifier according of the ISDN LAPD-protocol. In auto and non-auto-modes with one-byte address field, TEI2 is a response address, according to X.25 LAPD. Semiconductor Group 252 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.19 RHCRD - Receive HDLC Control Register for D-Channel (Read) Value after reset: (not defined) 7 RHCRD 0 (A9) In all modes except transparent modes 2 and 3, this register contains the control field of a received HDLC-frame. In transparent modes 2 and 3, the register is not used. Contents of RHCRD Mode Modulo 8 (MCS=0) Modulo 128 (MCS=1) U-frames only: Control field 2) U-frames only: Control field 2) Contents of RFIFOD From 3rd byte after flag 3) From 4th byte after flag 3) Control field Auto-mode, 1-byte 1) address (U/I frames) Auto-mode, 2-byte Control field 1) address (U/I frames) Auto-mode, 1-byte address (I frames) Auto-mode, 2-byte address (I frames) Non-auto-mode, 1-byte address Non-auto-mode, 2-byte address Transparent mode 1 Transparent mode 2 Transparent mode 3 1) 2) 3) 4) Control field From 4th byte after flag 3) compressed form 4) Control field in From 5th byte after flag 3) compressed form 4) 2nd byte after flag 3rd byte after flag 3rd byte after flag – – From 3rd byte after flag From 4th byte after flag From 4th byte after flag From 1st byte after flag From 2nd byte after flag S-frames are handled automatically and are not transferred to the microprocessor. For U-frames (bit 0 of RHCRD = 1) the control field is as: in the modulo 8 case. I-field. For I-frames (bit 0 of RHCRD = 0) the compressed control field has the same format as in the modulo 8 case, but only the three LSB’s of the receive and transmit counters are visible: 7 N(R) 2-0 P N(S) 2-0 0 0 Semiconductor Group 253 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.20 RBCHD - Receive Frame Byte Count High for D-Channel (Read) Value after reset: 0XXX00002. 7 RBCHD XAC --OV RBC11 0 RBC8 (AA) XAC ... Transmitter Active The HDLC-transmitter is active when XAC = 1. This bit may be polled. The XAC-bit is active when: – either an XTF/XIF-command is issued and the frame has not been completely transmitted – or the transmission of an S-frame is internally initiated and not yet completed. OV ... Overflow A “1” in this bit position indicates a message longer than 4095 bytes. RBC8-11 ... Receive Byte Count Four most significant bits of the total number of bytes in a received message. Note: Normally RBCHD and RBCLD should be read by the processor after an RMEinterrupt in order to determine the number of bytes to be read from the RFIFOD, and the total message length. The contents of the registers are valid only after an RME-interrupt, and remain so until the frame is acknowledged via the RMC-bit. Semiconductor Group 254 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.21 STAR2 - Status Register 2 (Read) Value after reset: (not defined) 7 STAR2 0 0 0 0 WFA 0 0 TREC SDET (AB) WFA ... Waiting for Acknowledge This bit shows, if the last transmitted I-frame was acknowledged, i.e. V(A) = V(S) (=> WFA= 0) or was not yet acknowledged, i.e. V(A) < V(S) (=> WFA = 1). TREC ... Timer recovery status 0: The device is not in the Timer Recovery state. 1: The device is in the Timer Recovery state. SDET ... S-frame detected This bit is set to “1” by the first received correct I-frame or S-command with p = 1. It is reset by reading the STAR2 register or by a HW reset. Semiconductor Group 255 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.22 SPCR - Serial Port Control Register (Read/Write) Value after reset: 00x00000B 7 SPCR SPU SDL SPM TLP 0 C1C1 C1C0 C2C1 C2C0 (B0) SPU ... Software Power UP. (Used in TE-mode only) Setting this bit to 1 will pull the DU-line to low. This will enforce connected layer 1 devices to deliver IOM-clocking. After power down in TE-mode the SPU-bit has to be set to “1” and then cleared again. After a subsequent CIC-interrupt (C/I-code change; ISTAD) and reception of the C/Icode “PU” (Power Up indication in TE-mode) the reaction of the processor would be: • to write an Activate Request or TIM command as C/I-code in the CIX0-register. • to reset the SPU bit and wait for the following CIC-interrupt. SDL ... Switch Data Line The switching of receive and transmit data of the D-channel controller to the IOM-2 interface is programmable by the SDL bit. 0: Transmit data is forwarded to the DU line, receive data comes from the DD line. 1: Transmit data is forwarded to the DD line, receive data comes from the DU line. SPM ... Serial Port Timing Mode Depending on the interface mode, the following timing options for the D-channel controller are provided. 0: Terminal Mode 1: Non Terminal Mode All three channels of the IOM-2 interface are used (Typical applications: TE mode, LT-S in intelligent NT). The selected IOM-2 channel (ADF1:CSEL2-0) is used (Typical applications: LT-T, LT-S modes, 8 channel structure on IOM-2) Note: The reset value for SPM is determined by pin MODE0 strapped to VDD or VSS (see chapter 2.4.1), however after reset the host can reconfigure the serial port timing mode for the D-channel controller. TLP ... Test Loop When set to 1 the DU and DD-lines are internally connected together, and the times T1 and T2 are reduced (see TIMR1 register). Data coming from the layer 1 controller will not be forwarded to the layer 2 controller (see chapter 2.5.9.2). Semiconductor Group 256 11.97 PSB 2115 PSF 2115 Detailed Register Description C1C1, C1C0 ... Channel 1 Connect Determines which of the two channels B1 or IC1 is connected to register C1R and/or B1CR, for monitoring, test-looping and switching data to/from the processor. C1R C1C1 0 0 1 C1C0 0 1 0 Read IC1 IC1 – Write – IC1 B1 B1CR Read B1 B1 B1 Application(s) B1-monitoring + IC1-monitoring B1-monitoring + IC1-looping from/to IOM B1-access from/to S; transmission of a constant value in B1-channel to S. B1-looping from S; transmission of a variable pattern in B1-channel to S. 1 1 B1 B1 – C2C1, C2C0 ... Channel 2 Connect Determines which of the two channels B2 or IC2 is connected to register C2R and/or B2CR, for monitoring, test-looping and switching data to/from the processor. C2R C2C1 0 0 1 C2C0 0 1 0 Read IC2 IC2 – Write – IC2 B2 B2CR Read B2 B2 B2 Application(s) B2-monitoring + IC2-monitoring B2-monitoring + IC2-looping from/to IOM B2-access from/to S; transmission of a constant value in B2-channel to S. B2-looping from S; transmission of a variable pattern in B2-channel to S. 1 1 B2 B2 – Note: B-channel access is only possible in TE-mode. Semiconductor Group 257 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.23 CIR0 - Command/Indication Receive 0 (Read) Value after reset: 7CH 7 CIR0 0 BAS CODR0 CIC0 0 CIC1 (B1) BAS ... Bus Access Status Indicates the state of the TIC-bus: 0: the IPAC itself occupies the D- and C/I-channel 1: another device occupies the D- and C/I-channel CODR0 ... C/I Code 0 Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 ... C/I Code 0 Change A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames. It is reset by a read of CIR0. CIC1 ... C/I Code 1 Change A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by a read of CIR0. CIC1 is only used if Terminal Mode is selected. Note: The BAS and CODR0 bits are updated every time a new C/I-code is detected in two consecutive IOM-frames. If several consecutive valid new codes are detected and CIR0 is not read, only the first and the last C/I code (and BAS bit) is made available in CIR0 at the first and second read of that register, respectively. Semiconductor Group 258 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.24 CIX0 - Command/Indication Transmit 0 (Write) Value after reset: 3FH 7 CIX0 RSS BAC CODX0 1 0 1 (B1) RSS ... Reset Source Select Only valid if the terminal specific functions are activated (STCR:TSF). 0 → Subscriber or Exchange Awake As reset source serves: – a falling edge on the EAW-line (External Subscriber Awake) – a C/I code change (Exchange Awake). A logical zero on the EAW-line activates also the IOM-interface clock and frame signal, just as the SPU-bit (SPCR) does. 1 → Watchdog Timer The expiration of the watchdog timer generates a reset pulse. The watchdog timer will be reset and restarted, when two specific bit combinations are written in the ADF1-register within the time period of 128 ms (see also ADF1 register description). After a reset pulse generated by the IPAC and the corresponding interrupt (WOV, SAW or CIC) the actual reset source can be read from the ISTAD and EXIRD-register. Note: ’External Awake’ is only available in TE mode. BAC ... Bus Access Control Only valid if the TIC-bus feature is enabled (MODED:DIM2-0). If this bit is set, the IPAC will try to access the TIC-bus to occupy the C/I-channel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: Access is always granted by default to the IPAC with TIC-Bus Address (TBA2-0, STCR register) “7”, which has the lowest priority in a bus configuration. CODX0 ... C/I-Code 0 Transmit Code to be transmitted in the C/I-channel / C/I-channel 0. Semiconductor Group 259 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.25 MOR0 - MONITOR Receive Channel 0 (Read) Value after reset: (not defined) 7 MOR0 0 (B2) Contains the MONITOR data received in IOM-2 MONITOR Channel 0 according to the MONITOR channel protocol. 4.3.26 MOX0 - MONITOR Transmit Channel 0 (Write) Value after reset: (not defined) 7 MOX0 0 (B2) Contains the MONITOR data transmitted in IOM-2 MONITOR Channel 0 according to the MONITOR channel protocol. 4.3.27 CIR1 - Command/Indication Receive 1 (Read) Value after reset: (not defined) 7 CIR1 CODR1 MR1 0 MX1 (B3) CODR1 ... C/I-Code 1 Receive (only valid in terminal mode) MR1 ... MR bit Bit 1 of C/I channel 1 MX1 ... MX bit Bit 0 of C/I/channel 1 Semiconductor Group 260 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.28 CIX1 - Command/Indication Transmit 1 (Write) Value after reset: FFH 7 CIX1 CODX1 1 0 1 (B3) CODX1 ... C/I-Code 1 Transmit (significant only in terminal mode) Bits 7-2 of C/I-channel 1 4.3.29 MOR1 - MONITOR Receive Channel 1 (Read) Value after reset: (not defined) 7 MOR1 Used only in terminal mode. Contains the MONITOR data received in IOM MONITOR channel 1 according to the MONITOR channel protocol. 0 (B4) 4.3.30 MOX1 - MONITOR Transmit Channel 1 (Write) Value after reset: (not defined) 7 MOX1 Used only in terminal mode. Contains the MONITOR data to be transmitted in IOM MONITOR channel 1 according to the MONITOR channel protocol. 0 (B4) Semiconductor Group 261 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.31 C1R - Channel Register 1 (Read/Write) Value after reset: (not defined) 7 C1R Used only in terminal mode. Contains the value received/transmitted in IOM-channel B1 or IC1, as the case may be (cf. C1C1, C1C0, SPCR-register). 0 (B5) 4.3.32 C2R - Channel Register 2 (Read/Write) Value after reset: (not defined) 7 C2R Used only in terminal mode. Contains the value received/transmitted in IOM-channel B2 or IC2, as the case may be (cf. C2C1, C2C0, SPCR-register). 0 (B6) Semiconductor Group 262 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.33 STCR - Synchronous Transfer Control Register (Write) Value after reset: 00H 7 STCR TSF TBA2 TBA1 TBA0 ST1 ST0 SC1 0 SC0 (B7) TSF ... Terminal Specific Functions (only in TE mode) 0 → No terminal specific functions 1 → The terminal specific functions are activated, such as – Watchdog Timer – Subscriber/Exchange Awake (EAW). In this case the EAW-line is always an input signal which can serve as a request signal from the subscriber to initiate the awake function in a terminal. A falling edge on the EAW-line generates an SAW-interrupt (EXIRD). When the RSS-bit in the CIX0-register is zero, a falling edge on the EAW-line (Subscriber Awake) or a C/I-code change (Exchange Awake) initiates a reset pulse. When the RSS-bit is set to one a reset pulse is triggered only by the expiration of the watchdog timer (see also CIX0-register description). Note: The TSF-bit will be cleared only by a hardware reset. The ’Exchange Awake’ functionality is only available in TE mode. TBA2-0 ... TIC Bus Address Defines the individual address for the IPAC on the IOM-bus. This address is used to access the C/I- and D-channel on the IOM. Note: One device liable to transmit in C/I- and D-fields on the IOM should always be given the address value “7”. ST1 ... Synchronous Transfer 1 When set, causes the IPAC to generate a SIN-interrupt status (ISTAD-register) at the beginning of an IOM-frame. ST0 ... Synchronous Transfer 0 When set, causes the IPAC to generate a SIN-interrupt status (ISTAD-register) at the middle of an IOM-frame. Semiconductor Group 263 11.97 PSB 2115 PSF 2115 Detailed Register Description SC1 ... Synchronous Transfer 1 Completed After a SIN interrupt the processor has to acknowledge the interrupt by setting the SC1 bit before the middle of the IOM frame, if the interrupt was originated from a Synchronous Transfer 1 (ST1). Otherwise a SOV interrupt (EXIRD register) will be generated. SC0 ... Synchronous Transfer 0 Completed After a SIN interrupt the processor has to acknowledge the interrupt by setting the SC0 bit before the end of the IOM frame, if the interrupt was originated from a Synchronous Transfer 0 (ST0). Otherwise a SOV interrupt (EXIRD register) will be generated. Note: ST0/1 and SC0/1 are useful for synchronizing processor accesses and receive/ transmit operations. 4.3.34 B1CR - B1 Channel Register (Read) Value after reset: (not defined) 7 B1CR Used only in terminal mode. Contains the value received in IOM-channel B1, if programmed (cf. C1C1, C1C0, SPCR-register). 0 (B7) 4.3.35 B2CR - B2 Channel Register (Read) Value after reset: (not defined) 7 B2CR Used only in terminal mode. Contains the value received in the IOM-channel B2, if programmed (cf. C2C1, C2C0, SPCR-register). 0 (B8) Semiconductor Group 264 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.36 ADF1 - Additional Feature Register 1 (Write) Value after reset: 0000xxx02 7 ADF1 WTC1 WTC2 CI1E 0 CSEL2 CSEL1 CSEL0 0 ITF (B8) WTC1, 2 ... Watchdog Timer Control 1, 2 After the watchdog timer mode has been selected (STCR:TSF = CIX0:RSS = 1) the watchdog timer is started. During every time period of 128 ms the processor has to program the WTC1- and WTC2bit in the following sequence: WTC1 1. 2. 1 0 WTC2 0 1 to reset and restart the watchdog timer. If not, the timer expires and a WOV-interrupt (EXIRD) together with a reset pulse is generated. CI1E ... C/I-channel 1 interrupt enable Interrupt generation ISTAD:CIC of CIR0:CIC1 is enabled (1) or masked (0). CSEL2-0 ... IOM-2 Channel Select (in LT modes only) Select one IOM-channel out of 8, where the IPAC is to receive/transmit B-Channel data. “000” channel 0 (first channel in IOM-frame) “001” channel 1 ... “111” channel 7 (last channel in IOM-frame) The reset value for CSEL2-0 is determined by the pins CH2-0 strapped to VDD or VSS. After reset the selected channel can be reconfigured by the host and the setting of pins CH2-0 has no further effect. Semiconductor Group 265 11.97 PSB 2115 PSF 2115 Detailed Register Description ITF ... Inter-Frame Time Fill Selects the inter-frame time fill signal which is transmitted between HDLC-frames. 0: idle (continuous 1 s), 1: flags (sequence of patterns: “0111 1110”) Note: In TE- and LT-T-applications with D-channel access handling (collision resolution), the only possible inter-frame time fill signal is idle (continuous 1s). Otherwise the D-channel on the S/ T-bus cannot be accessed. 4.3.37 MOSR - MONITOR Status Register (Read) Value after reset: 00H 7 MOSR 0 (BA) MDR1 MER1 MDA1 MAB1 MDR0 MER0 MDA0 MAB0 MDR1 ... MONITOR channel 1 Data Received MER1 ... MONITOR channel 1 End of Reception MDA1 ... MONITOR channel 1 Data Acknowledged The remote end has acknowledged the MONITOR byte being transmitted. MAB1 ... MONITOR channel 1 Data Abort MDR0 ... MONITOR channel 0 Data Received MER0 ... MONITOR channel 0 End of Reception MDA0 ... MONITOR channel 0 Data Acknowledged The remote end has acknowledged the MONITOR byte being transmitted. MAB0 ... MONITOR channel 0 Data Abort Semiconductor Group 266 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.3.38 MOCR - MONITOR Control Register (Write) Value after reset: 00H 7 MOCR 0 (BA) MRE1 MRC1 MIE1 MXC1 MRE0 MRC0 MIE0 MXC0 MRE1 ... MONITOR receive interrupt enable (IOM-channel 1) MONITOR interrupt status MDR1 generation is enabled (1) or masked (0). MRE0 ... MONITOR receive interrupt enable (IOM-channel 0) MONITOR interrupt status MDR0, MER0 generation is enabled (1) or masked (0). MRC1, 0 ... Determines the value of the MR-bit: 0: Determines the value of the MR-bit: MR always “1”. In addition, the MDR1/MDR0 interrupt is blocked, except for the first byte of a packet (if MRE 1/0=1). 1: MR internally controlled by the IPAC according to MONITOR channel protocol. In addition, the MDR1/MDR0-interrupt is enabled for all received bytes according to the MONITOR channel protocol (if MRE1,0=1). MIE1 ... MONITOR interrupt enable (IOM-channel 1) MONITOR interrupt status MER1, MDA1, MAB1 generation is enabled (1) or masked (0). MIE0 ... MONITOR interrupt enable (IOM-channel 0) MONITOR interrupt status MDA0, MAB0 generation is enabled (1) or masked (0). MXC1, 0 ... MX Bit Control (IOM-channel 1,0) Determines the value of the MX-bit: 0.. MX always “1”. 1.. MX internally controlled by the IPAC according to MONITOR channel protocol. Semiconductor Group 267 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4 4.4.1 General IPAC Registers CONF - IPAC Configuration Register (Read/Write) Value after reset: 00H 7 CONF AMP CFS TEM PDS IDH SGO ODS 0 IOF (C0) AMP ... Amplification of S/T receiver 0: an external transformer of ratio 2:1 is connected to the receive lines. 1: an external transformer of ratio 1:1 is connected to the receive lines. CFS ... Configuration Select This bit determines clock relations and recovery on S/T and IOM interfaces. • TE and LT-T Modes 0: The IOM interface clock and frame signals are always active, "Power Down" state included. The states "Power Down" and "Power Up" are thus functionally identical except for the indication: PD = 1111 and PU = 0111. With the C/I command Timing (TIM) the processor can enforce the "Power Up" state. With C/I command Deactivation Indication (DIU) the "Power Down" state is reached again. However, it is also possible to activate the S-Interface directly with the C/I command Activate Request (AR 8/10/L) without the TIM command. 1: The IOM interface clock and frame signals are normally inactive ("Power Down"). For activating the IOM-2 clocks the "Power Up" state can be induced by software (SPU-bit in SPCR register) or by resetting again CFS. After that the S-interface can be activated with the C/I command Activate Request (AR 8/10/L). The "Power Down" state can be reached again with the C/I command Deactivation Indication (DIU). Note: After reset the IOM interface is always active. To reach the "Power Down" state the CFS-bit has to be set. • LT-S Mode CFS has to be set to "0" always. Semiconductor Group 268 11.97 PSB 2115 PSF 2115 Detailed Register Description TEM ... Test Mode In test mode (TEM=1) all layer-1 functions are disabled and the IPAC behaves like a DChannel HDLC controller (e.g. ICC PEB 2070) with a two channel HDLC communications controller (e.g. HSCX-TE PSB 21525). PDS ... Phase Deviation Select Defines the phase deviation of the S-transceiver in TE or LT-T mode. 0: the phase deviation is two S-bits plus analog delay plus delay of the external circuitry. 1: the above phase deviation is reduced by 2 oscillator clocks (= 260 ns). IDH ... IOM D-Channel Priority Handler The state machine for D-channel priority handling on IOM-2 is 0: disabled 1: enabled Note: This mode is used in intelligent NT applications. The priority 8 or 10 is selected via bit SCFG:PRI. SGO ... Stop/Go Bit Output (LT-T mode) In LT-T mode the S/G bit can be output on pin AUX7. This may be used for test purposes in order to observe the Stop/Go indications. 0: Pin AUX7 has default I/O functionality. 1: The S/G bit is output on pin AUX7. ODS ... Output Driver Selection Defines the output driver of the IOM-2 interface: 0: open drain 1: push pull IOF ... IOM OFF 0: IOM interface is operational 1: IOM interface is switched off (DU, DD, FSC, DCL, BCL/SCLK, SDS high impedant). IOF should be set to ’1’ if external devices connected to the IOM interface should be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM connection between layer 1 and layer 2. However, the IPAC internal operation between S-transceiver, B-channel and D-channel controller is independent of the IOF bit. In Non-TE mode FSC and DCL (both input) are not switched off from the IOM-2 interface. Semiconductor Group 269 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4.2 ISTA - IPAC Interrupt Status Register (Read) Value after reset: 00H 7 ISTA INT1 INT0 ICD EXD ICA EXA ICB 0 EXB (C1) INT1, INT0 ... Interrupt 1/0 from external devices A low level or negative state transition (programmable in ACFG: EL1, EL0) was detected at pin AUX6 or AUX7 respectively. ICD ... Interrupt from D-Channel An interrupt is caused by the D-channel, its source can be read in the interrupt status register of the D-Channel (ISTAD). EXD ... Extended Interrupt from D-Channel An extended interrupt is caused by the D-channel, its source can be read in the extended interrupt status register of the D-Channel (EXIRD). ICA, ICB ... Interrupt from B-Channel A, B An interrupt is caused by the B-channel A, B. Its source can be read in the interrupt status register of the B-Channel A or B, respectively (ISTAB). EXA, EXB ... Extended Interrupt from B-Channel A, B An extended interrupt is caused by the B-channel A, B. Its source can be read in the extended interrupt status register of the B-Channel A or B, respectively (EXIRB). Semiconductor Group 270 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4.3 MASK - IPAC Mask Register (Write) Value after reset: C0H 7 MASK INT1 INT0 ICD EXD ICA EXA ICB 0 EXB (C1) Each interrupt source can selectively be masked by setting the respective bit in MASK (bit positions corresponding to ISTA register). Masked interrupts are not indicated when reading ISTA. Instead, they remain internally stored and will be indicated after the respective MASK bit is reset. Note: In the event of an extended interrupt, no interrupt request will be generated with a masked ICD, EXD, ICA, EXA, ICB, EXB bit, although a bit is set in ISTAD, EXIRD, ISTAB or EXIRB. After Reset all interrupts are enabled except INT1 and INT0. 4.4.4 ID - Identification Register (Read) Value after reset: 01H 7 ID ID ... Identification Number The version number of the IPAC can be read from ID 01H: Version 1.1 0 (C2) Semiconductor Group 271 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4.5 ACFG - Auxiliary Interface Configuration (Read/Write) Value after reset: 00H 7 ACFG OD7 OD6 OD5 OD4 OD3 OD2 EL1 0 EL0 (C3) OD7 - OD2 ... Output Driver Select for AUX7 - AUX2 0: output is open drain 1: output is push/pull Note: The ODx configuration is only valid, if the corresponding output is enabled in the AOE register. AUX2 is only available in TE mode and not in LT modes. In LT modes AUX 3-5 is only available if the PCM interface is disabled (PCFG:PLD=1). In TE mode the host must set PCFG:PLD=1 before the output driver is selected. EL1, EL0 ... Edge / Level Triggered Interrupt Input for INT1, INT0 0: a negative level ... 1: a negative edge ... on INT1/0 (pins AUX7/6) generates an interrupt to the IPAC. An interrupt is only generated to the IPAC, if the corresponding mask bit in MASK is reset. Note: This configuration is only valid, if the corresponding output enable bit in AOE is disabled. Semiconductor Group 272 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4.6 AOE - Auxiliary Output Enable (Read/Write) Value after reset: FCH 7 AOE OE7 OE6 OE5 OE4 OE3 OE2 0 0 0 (C4) OE7 - OE2 ... Output Enable for AUX7-2 0: Pin AUX7-2 is configured as output. The value of the corresponding bit in the ATX register is driven on AUX7-2. 1: Pin AUX7-2 is configured as input. The value of the corresponding bit can be read from the ARX register. Note: If pins AUX7, AUX6 are to be used as interrupt input, OE7,OE6 must be set to 1. Pin AUX2 is only available in TE mode and not in LT modes. In LT modes the pins AUX 3-5 are only available if the PCM interface is disabled (PCFG:PLD=1). The general purpose I/O pins are input after reset (OEx=1). 4.4.7 ARX - Auxiliary Interface Receive Register (Read) Value after reset: (not defined) 7 ARX AR7 AR6 AR5 AR4 AR3 AR2 0 0 0 (C5) AR7-AR2 ... Auxiliary Receive The value of AR7-AR2 reflects the level at pin AUX7-AUX2 at that time when ARX is read by the host. If the mask bit for AUX7,6 is set in the MASK register, no interrupt is generated to the IPAC, however, the current state at pin AUX7,6 can be read from AR7,6. Note: Pin AUX2 is only available in TE mode and not in LT modes. In LT modes the pins AUX 3-5 are only available if the PCM interface is disabled (PCFG:PLD=1). Semiconductor Group 273 11.97 PSB 2115 PSF 2115 Detailed Register Description 4.4.8 ATX - Auxiliary Interface Transmit Register (Write) Value after reset: 00H 7 ATX AT7 AT6 AT5 AT4 AT3 AT2 0 0 0 (C5) AT7-AT2 ... Auxiliary Transmit A ’0’ or ’1’ in AT7-AT2 will drive a low or high level at pin AUX7-AUX2, if the corresponding output is enabled in the AOE register. Note: AUX2 is only available in TE mode and not in LT modes. In LT modes AUX 3-5 is only available if the PCM interface is disabled (PCFG:PLD=1). 4.4.9 PITA1/2 - PCM Input Time Slot Assignment B1/B2 (Read/Write) Value after reset: 00H 7 PITA1/ PITA2 ENA DUDD 0 TNRX 0 (C6/C7) PITA1 refers to the B1-channel and PITA2 to the B2-channel of the IOM channel which is selected by PCFG:CSL2-0. ENA ... Enable PCMIN channel 0: Disables... 1: Enables ... reception of data in from the PCM interface line PCMIN. Note: Data from an external controller is received on the PCM interface by the IPAC. This data is then mapped to the corresponding B1/B2 channel of the IOM-2 DU line (default) or DD line. DUDD ... Switch on IOM-2 DU/DD line The selected PCM timeslot on the PCMIN line is mapped to the 0: DU-line (default) 1: DD-line ... of the IOM-2 interface. Semiconductor Group 274 11.97 PSB 2115 PSF 2115 Detailed Register Description TNRX ... Time Slot Number Receive Selects one of up to 32 possible timeslots (00h-1Fh) in which data is received from the PCM interface. Note: The configuration of the PCM timeslots is equal for B1 and B2-channel. 4.4.10 POTA1/2 - PCM Output Time Slot Assignment B1/B2 (Read/Write) Value after reset: 00H 7 POTA1 ENA 7 POTA2 ENA DUDD SRES TNTX DUDD 0 TNTX 0 (C9) 0 (C8) POTA1 refers to the B1-channel and POTA2 to the B2-channel of the IOM channel which is selected by PCFG:CSL2-0. ENA ... Enable PCMOUT channel 0: Disables... 1: Enables ... transmission of data on the PCM interface line PCMOUT. Note: Data is transmitted by the IPAC on the PCM interface to an external device. This data may be originated from the B1/B2 channel of the IOM-2 DD-line (default) or DU-line. DUDD ... Switch on IOM-2 DU/DD line The selected PCM timeslot on the PCM interface is mapped to the 0: DD-line (default) 1: DU-line ... of the IOM-2 interface. SRES... Software Reset 0: Deactivates ... 1: Activates ... the internal RESET state of the IPAC. The RESET state is activated to the internal blocks of the IPAC when a ’1’ is written to SRES and it is active until the SRES-bit is set to ’0’ again, i.e. the host must ensure the required RESET timing of the IPAC which is 4 ms. Semiconductor Group 275 11.97 PSB 2115 PSF 2115 Detailed Register Description TNTX ... Time Slot Number Transmit Selects one of up to 32 possible timeslots (00h-1Fh) in which data is transmitted to the PCM interface. Note: The configuration of the PCM timeslots is equal for B1 and B2-channel. 4.4.11 PCFG - PCM Configuration Register (Read/Write) Value after reset: 00H 7 PCFG DPS ACL LED PLD FBS 0 CSL2 CSL1 CSL0 (CA) DPS ... Data Path Select Data from the B-channel FIFOs is exchanged with the 0: IOM-2 interface 1: PCM interface ACL ... ACL Function Select 0: pin ACL indicates the S-bus activation status by a LOW level 1: the state at pin ACL is programmable by the host via bit LED. LED ... LED Control If enabled (ACL=1) the LED connected to pin ACL is switched 0: Off 1: On Note: The state (log. high/low) on pin ACL is derived from the inverted state of PCFG:LED. For ACL=0 the state of PCFG:LED has no effect. PLD ... PCM Lines Disable (LT-S and LT-T modes) 0: AUX3-5 are used for PCM interface (default) 1: AUX3-5 are used as normal I/O lines (PCM interface disabled) Note: In TE mode PLD must be set to ’1’ before AUX3-5 are used as I/O lines. Semiconductor Group 276 11.97 PSB 2115 PSF 2115 Detailed Register Description FBS ... FSC/BCL Output Select (LT-S and LT-T modes) 0: FSC is output on AUX3, which is derived from the DCL input by division of 192. 1: BCL single bit clock is output on AUX3. It is derived from the DCL input by division of 2. Note: SCLK output provides 1.536 MHz in LT-T mode. This may be used for the DCL input. This bit is ignored in TE mode. CSL2-0 ... IOM-2 Channel Selection for PCM (LT-S and LT-T modes) Selects one of eight IOM channels to which the PCM interface is connected to. 000: channel 0 001: channel 1 : : 111: channel 7 Note: These bits are ignored in TE mode. 4.4.12 SCFG - SDS Configuration Register (Read/Write) Value after reset: 00H 7 SCFG PRI TXD TLEN TSLT 0 (CB) PRI ... Priority for D-channel Handler (only in LT-S mode in intelligent NT) Determines the priority of D-channel access on IOM-2 for the D-channel controller on the IPAC and for external D-channel sources connected to the IOM-2 interface. The state machine for D-channel handling controls the S/G bit according to the setting of PRI and enables the access of internal or external D-channel sources. 0: Priority = 8 1: Priority = 10 Note: The read back value of PRI only contains the programmed value as soon as the state machine has switched to the selected priority. The D-channel handler can be enabled/disabled via bit CONF:IDH. TXD ... S-transmitter Disable The transmitter of the S-transceiver can be disabled by setting TXD to “1“. This can be used to reduce power consumption (see chapter 2.5.4). Semiconductor Group 277 11.97 PSB 2115 PSF 2115 Detailed Register Description TLEN ... Timeslot Length 0: 8 bit 1: 16 bit TSLT ... Timeslot Position Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which SDS is active high. The data strobe signal allows standard data devices to access a programmable channel. 4.4.13 TIMR2 - Timer 2 Register (Read/Write) Value after reset: 00H 7 TIMR2 TMD 0 CNT 0 (CC) TMD ... Timer Mode Timer 2 can be used in two different modes of operation. 0: Count down timer. An interrupt is generated only once after a time period of 1 ... 63 ms. 1: Periodic timer. An interrupt is periodically generated every 1 ... 63 ms (see CNT). CNT ... Timer Count 0: 1 ... 63: Timer off Timer length = 1 ... 63 ms By writing ’0’ to CNT, the timer is immediately stopped. A value different from that determines the time period after which an interrupt will be generated. If the timer is already started with a certain CNT value and is written again before an interrupt has been released, the timer will be reset to the new value and restarted again. An interrupt is indicated to the host in ISTAD:TIN2. Semiconductor Group 278 11.97 PSB 2115 PSF 2115 Electrical Characteristics 5 Electrical Characteristics Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Ambient temperature under bias Storage temperature Maximum voltage on V DD Symbol VS TA Tstg VDD Limit Values – 0.3 to VDD + 0.3 0 to 70 – 65 to 150 7 Unit V °C °C V Note: Stresses above those listed under ’Absolute Maximum Ratings’ may cause permanent damage to the device. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. This is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. Line Overload Protection The maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse (figure 99). IPAC Ι t t WI Condition: All other pins grounded ITD09658 Figure 99 Test Condition for Maximum Input Current Semiconductor Group 279 11.97 PSB 2115 PSF 2115 Electrical Characteristics Line Input Current The destruction limits are given in figure 100. Ι 5000 mA 500 50 5 t 10 -9 10 -7 10 -5 10 -3 sec ITD10061 Figure 100 Maximum Line Input Current Semiconductor Group 280 11.97 PSB 2115 PSF 2115 Electrical Characteristics DC Characteristics TA = 0 to 70 °C; VDD = 5 V ± 5 %, VDDA = 5 V ± 5 %, VSS = 0 V, VSSA = 0 V Parameter Symbol Limit Values Unit Test Condition min L-input voltage H-input voltage L-output voltage VIL VIH VOL – 0.3 2.0 max 0.8 V All pins except SX1,2, SR1,2 XTAL1/2 IOL = 7 mA (DU, DD, C768) IOL = 5 mA (ACL, AUX6,7, AD0-7) IOL = 2 mA (all others) IOH = – 5 mA (AD0-7) IOH = – 400 µA (all others) IOH = – 100 µA VDD = 5 V Inputs at VSS / VDD No output loads Remarks VDD V + 0.3 0.45 V H-output voltage H-output voltage VOH VOH 2.4 VDD – 0.5 3 V V mA Power ICC supply current power down Power supply current operational 20 20 mA DCL=1536 kHz VDD = 5 V Inputs at (96 kHz test VSS / VDD pulse) No output mA DCL=1536 kHz loads (B1=B2=FFH, (including D=1) SX1, 2) mA DCL=4096 kHz (B1=B2=FFH, D=1) 25 Semiconductor Group 281 11.97 PSB 2115 PSF 2115 Electrical Characteristics DC Characteristics TA = 0 to 70 °C; VDD = 5 V ± 5 %, VDDA = 5 V ± 5 %, VSS = 0 V, VSSA = 0 V (cont’d) Parameter Symbol Limit Values Unit Test Condition min Input leakage current Output leakage current Input leakage current internal pull-up ILI max 1 µA µA 0 V < VIN < VDD All pins except SX1,2, SR1,2 XTAL1/2, AUX7/6 AUX7/6 Remarks ILO 1 0 V < VOUT < VDD ILIPU 50 200 µA 0 V < VIN < VDD VX Absolute value of output pulse amplitude (VSX2 – VSX1) Transmitter output current Transmitter output impedance Receiver input impedance IX 2.03 2.10 2.31 2.39 V V RL = 50 Ω RL = 400 Ω SX1,2 7.5 13.4 mA RL = 5.6 Ω ZX 10 0 30 kΩ Ω kΩ Inactive or during binary one during binary zero RL = 50 Ω VDD = 5 V SR1,2 ZR Note: Due to the transformer, the load resistance seen by the circuit is four times RL. Semiconductor Group 282 11.97 PSB 2115 PSF 2115 Electrical Characteristics Capacitances TA = 25 °C, VDD = 5 V ± 5 %, VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded. Table 28 Parameter Input Capacitance I/O Capacitance Output Capacitance against VSSA Load Capacitance Capacitances Symbol CIN CI/O COUT CL Limit Values Unit min. max. 7 7 10 50 pF pF pF pF All pins except SX1,2 and XTAL1,2 SX1,2 XTAL1,2 Remarks Semiconductor Group 283 11.97 PSB 2115 PSF 2115 Electrical Characteristics Recommended Oscillator Circuits 33 pF 41 XTAL1 CL 7.68 MHz 33 pF 42 External Oscillator Signal 41 XTAL1 XTAL2 N.C. 42 XTAL2 CL Crystal Oscillator Mode Driving from External Source ITS09659 Figure 101 Oscillator Circuits Crystal Specification Parameter Frequency Frequency calibration tolerance Load capacitance Oscillator mode Symbol f CL Limit Values 7.680 max. 100 max. 50 fundamental Unit MHz ppm pF Note: The load capacitance CL depends on the recommendation of the crystal specification. Typical values for CL are 22 ... 33 pF. XTAL1 Clock Characteristics (external oscillator input) Parameter Duty cycle Limit Values min. 1:2 max. 2:1 Semiconductor Group 284 11.97 PSB 2115 PSF 2115 Electrical Characteristics AC Characteristics TA = 0 to 70 °C, VDD = 5 V ± 5% Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in figure 102. 2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test C Load = 100 pF ITS09660 Figure 102 Input/Output Waveform for AC Tests Semiconductor Group 285 11.97 PSB 2115 PSF 2115 Electrical Characteristics Microprocessor Interface Timing Siemens/Intel Bus Mode Figure 103 Microprocessor Read Cycle Figure 104 Microprocessor Write Cycle Figure 105 Multiplexed Address Timing 286 11.97 Semiconductor Group PSB 2115 PSF 2115 Electrical Characteristics WR x CS or RD X CS t AS A0-A7 Address t AH ITT09661 Figure 106 Non-Multiplexed Address Timing Motorola Bus Mode Figure 107 Microprocessor Read Timing R/W t DSD t WW CS x DS t RWD t WI t WD t DW D0 - D7 Data ITT09679 Figure 108 Microprocessor Write Cycle 287 11.97 Semiconductor Group PSB 2115 PSF 2115 Electrical Characteristics CS x DS t AS AD0 - AD7 t AH ITT09662 Figure 109 Non-Multiplexed Address Timing Microprocessor Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time DS delay after R/W setup RD pulse width Data output delay from RD Data float from RD RD control interval W pulse width Data setup time to W x CS Data hold time W x CS W control interval R/W hold from CS x DS inactive Symbol tAA tAL tLA tALS tAS tAH tAD tDSD tRR tRD tDF tRI tWW tDW tWD tWI tRWD Limit Values min. 50 15 10 0 25 10 15 0 110 110 25 70 60 35 10 70 tbd max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Semiconductor Group 288 11.97 PSB 2115 PSF 2115 Electrical Characteristics Serial Interface Timing FSC (O) t IIS DCL (O) t FSD t IIH DU/DD (I) t IOD DU/DD (O) t SDD SDS (O) t BCD FSC/BCL (O) t BCD ITD09663 Figure 110 IOM® Timing (TE mode) Semiconductor Group 289 11.97 PSB 2115 PSF 2115 Electrical Characteristics DCL (I) t FSW FSC (I) t FSS t FSH t FSS t FSH t IIH t IIS DU/DD (I) Bit 0 t IOD DU/DD (O) Bit 0 t SDD SDS (O) ITT09680 Figure 111 Parameter IOM® Timing (LT-S, LT-T mode) Symbol tIOD tIIS tIIH tFSD tSDD tBCD tFSS tFSH tFSW 50 30 40 20 20 -100 20 120 100 Limit Values min. max. 100 ns ns ns ns ns ns ns ns ns Unit IOM output data delay IOM input data setup IOM input data hold FSC strobe delay Strobe signal delay BCL / FSC delay Frame sync setup Frame sync hold Frame sync width Semiconductor Group 290 11.97 PSB 2115 PSF 2115 Electrical Characteristics PCM Interface Timing DCL (I) t FSW FSC (I) t FSS t FSH t FSS t FSH t PIH t PIS PCMIN Bit 0 t POD PCMOUT Bit 0 t BCD BCL (O) (FBOUT) t BCD ITT09681 Figure 112 PCM Interface Timing (LT-S, LT-T mode) Parameter PCM output data delay PCM input data setup PCM input data hold BCL delay Frame sync setup Frame sync hold Frame sync width Symbol tPOD tPIS tPIH tBCD tFSS tFSH tFSW Limit Values min. 20 50 100 50 30 40 max. 100 Unit ns ns ns ns ns ns ns Semiconductor Group 291 11.97 PSB 2115 PSF 2115 Electrical Characteristics Figure 113 Parameter BCL, FSC Output Delay Symbol tBCD tFSD Limit Values min. max. 100 100 ns ns Unit BCL delay from DCL FSC delay from DCL Semiconductor Group 292 11.97 PSB 2115 PSF 2115 Electrical Characteristics Auxiliary Interface Timing Certain pins from the auxiliary interface can be used as standard I/O pins (see chapter 2.8). Their timing conditions either as input or as output is shown in figure 114. The read and write signals indicate the corresponding access to the IPAC register, they are not control signals on the auxilliary interface. Figure 114 Parameter AUX Interface I/O Timing Symbol tAIS tAIH tAOD Limit Values min. max. ns ns 200 ns 30 30 Unit Auxiliary input data setup Auxiliary input data hold Auxiliary output data delay Semiconductor Group 293 11.97 PSB 2115 PSF 2115 Electrical Characteristics Clock Timing The clocks in the different operating modes are summarized in table below with the respective duty ratios. Application TE LT-T LT-S M0 M1 0X 11 10 DCL FSC BCL / SCLK o: 768 kHz 1:1 o: 1536 kHz 1:1 o: DCL/2 o: 1536 kHz o: 8kHz 1:1 1:2 i: 4096 kHz (max.) i: 4096 kHz (max.) i: 8 kHz i: 8 kHz Note: M0 and M1 denote the pins MODE0 and MODE1/EAW, respectively. In TE mode MODE 1 is don’t care (used as EAW pin). All output clocks are synchronous to the S-receiver. BCL/SCLK output in LT-S mode is derived from the DCL input clock. The 1536-kHz clock (TE mode) is phase-locked to the receive S signal, and derived using the internal DPLL and the 7.68 MHz ± 100 ppm crystal. A phase tracking with respect to "S" is performed once in 250 µs. As a consequence of this DPLL tracking, the "high" state of the 1536-kHz clock may be either reduced or extended by half of one 7.68-MHz period (duty ratio 4:5 or 5:4 instead of 5:5) once every 250 µs. Since the other signals are derived from this clock (TE mode), the "high" or "low" states may likewise be reduced or extended by the same amount once every 250 µs. The phase relationships of the clocks are shown in figure 115. 7.68 MHz 1536 kHz * * Synchronous to receive S/T. Duty Ratio 1:1 Normally 768 kHz ITD09664 Figure 115 Phase Relationships of IPAC Clock Signals Semiconductor Group 294 11.97 PSB 2115 PSF 2115 Electrical Characteristics The following tables give the timing characteristics of the clocks. Figure 116 Definition of Clock Period and Width DCL Clock Characteristics Parameter (TE) 1536 kHz Symbol tPO tWHO tWLO (LT-S, LT-T) 4096 kHz tPI tWHI tWLI Limit Values min. 585 235 300 240 100 100 typ. 651 315 315 244 max. 717 405 350 ns ns ns ns ns ns osc ± 100 ppm osc ± 100 ppm osc ± 100 ppm Unit Test Condition Semiconductor Group 295 11.97 PSB 2115 PSF 2115 Electrical Characteristics Jitter In TE mode, the timing extraction jitter of the IPAC conforms to CCITT Recommendation I.430 (– 7% to + 7% of the S-interface bit period). In the LT-S applications, the clock input FSC is used as reference clock to provide the 192-kHz clock for the S-line interface. In the case of a plesiochronous 7.68-MHz clock generated by an oscillator, the clock FSC should have a jitter less than 100 ns peak-topeak. (In the case of a zero input jitter on FSC the IPAC generates at most 65 ns "selfjitter" on the S interface.) In the case of a synchronous (fixed divider ratio between XTAL1 and DCL) 7.68-MHz clock (input XTAL1), the IPAC transfers the input jitter of XTAL1, DCL and FSC to the S interface. The maximum jitter of the LT-S output is limited to 260 ns peak-to-peak (CCITT I.430). Description of the Transmit PLL (XPLL) of the IPAC Function of the XPLL The XPLL generates a 1.536-MHz clock synchronized to the FSC 8-kHz clock by modification of the counter's divider ratio. The 1.536-MHz clock is then divided to 192 kHz and 8 kHz. The 8 kHz is used as the looped back clock and compared to the FSC 8-kHz in the phase detector. Jitter considerations in case of a synchronous 7.68-MHz clock After the XPLL has locked once, no more tracking steps are performed because there is a fixed divider ratio of 960 between 7.68 MHz and FSC. Therefore the input jitter at FSC and 7.68 MHz is transferred transparently to the S/T interface (192 kHz). Jitter considerations in case of a plesiochronous 7.68-MHz clock (crystal) Each tracking step of the XPLL produces an output jitter of 130 ns pp. In case of nonzero input jitter at DCL, this input jitter is increased by 130 ns pp. That means that the output jitter will not exceed 130 ns pp. Semiconductor Group 296 11.97 PSB 2115 PSF 2115 Electrical Characteristics 7.68 MHz Divider ÷5±1 1.536 MHz Divider ÷8 192 kHz Lead Lag Up/Down Counter Up Down Phase Detector 8 kHz Divider ÷ 192 FSC 8 kHz ITS09665 Figure 117 Block Diagram of XPLL Description of the receive PLL (RPLL) of the IPAC The receive PLL performs phase tracking each 250 µs after detecting the phase between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 65 ns to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to generate any other clock synchronized to the line. During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to have high or low times as short as 130 ns. After the S/T interface frame has achieved the synchronized state (after three consecutive valid pairs of code violations) the FSC output in TE mode is set to a specific phase relationship, thus causing once an irregular FSC timing. Semiconductor Group 297 11.97 PSB 2115 PSF 2115 Electrical Characteristics Reset Table 29 Parameter Length of active high state Reset Signal Characteristics Symbol tRST Limit Values min. 4 2 x DCL clock cycles ms Power On/Power Down to Power Up (Standby) During Power Up (Standby) Unit Test Conditions Figure 118 Reset Signal Semiconductor Group 298 11.97 PSB 2115 PSF 2115 Package Outlines 6 Package Outlines P-MQFP-64 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 299 Dimensions in mm 11.97 GPM05247 PSB 2115 PSF 2115 Package Outlines P-TQFP-64 (Plastic Thin Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 300 Dimensions in mm 11.97 GPM05613 PSB 2115 PSF 2115 Appendix 7 Appendix The following chapters contain a quick reference guide. 7.1 MON-8 Registers MON-8 Configuration Register In the configuration register the user programs the IPAC for different operational modes, and selects required S-bus features. The following paragraphs describe the application relevance of all individual configuration register bits. Address: 1h MFD Value after Reset: 00H 0 FSMM LP SQM RCVE C/W/P 0 RD/WR MFD Multi-Frame-Disable. Selects whether multiframe generation (LT-S) or synchronization (TE, LT-T) is prohibited (MFD=1) or allowed (MFD=0). Enable multiframing if S/Q channel data transfer is desired. If MFD=1 no S/Q MONITOR messages are released. When reading this register the bit indicates whether multiframe synchronization has been established (MFD=1) or not (MFD=0). Finite State Machine Mode. By programming this bit the user has the possibility to exchange the state machines of LT-S and NT, i.e. an IPAC pin strapped for LT-S operates with a NT state machine. All other operation mode specific characteristics are retained. This function is used in intelligent NT configurations where the IPAC needs to be pin-strapped to LT-S mode but the state machine of an NT is desirable. Loop Transparency. In case analog loop-backs are closed with C/I = ARL or bit SC in the loop-back register, the user may determine with this bit, whether the data is forwarded to the S/T-interface outputs (transparent) or not. The default setting depends on the operational mode. TE/LT-T modes:0 =non transparent 1 =transparent ext. loop LT-S mode:0 =transparent 1 = non transparent In LT-S by default transparency is selected (LP=0), for LT-T and TE nontransparency is standard (LP=0). FSMM LP Semiconductor Group 301 11.97 PSB 2115 PSF 2115 Appendix SQM Selects the SQ channel handling mode. In non-auto mode operation, the IPAC issues S1 and Q messages in the IOM-2 monitor channel only after a change has been detected. The S2 channel is not available in non-auto mode. In transparent mode monitor messages containing the S1, S2 and Q data are forwarded to IOM-2 once per multiframe (5 ms), regardless of the data content. Programming the SQM bit is only relevant if multiframing on S/T is selected (bit MFD configuration register). See also MON-1 and MON-2 monitor messages. Receive Code Violation Errors. The user has the option to issue a C/I error code (CVR) everytime an illegal code violation has been detected. The implementation is realized according to ANSI T1.605. This bit has three different meanings depending on the operational mode of the IPAC: In LT-S mode the S/T bus configuration is programmed. For point-to-point or extended passive bus configurations an adaptive timing recovery must be chosen. This allows the IPAC to adapt to cable length dependent round trip delays. In LT-T mode the user selects the amount of permissible wander before a C/I code warning will be issued by the IPAC. The warning may be sent after 25 µs (C/W/P=1) or 50 µs (C/W/P=0). Note: The C/I indication SLIP which will be issued if the specified wander has been exceeded, is only a warning. Data has not been lost at this stage. In TE mode this bit is not used RCVE C/W/P Semiconductor Group 302 11.97 PSB 2115 PSF 2115 Appendix MON-8 Loop-Back Register The loop-back register controls all analog (S/T-interface) and digital (IOM-2 interface) loop-backs. Additionally the wake-up mode can be programmed. Address: 2h AST SB1 SB2 SC IB1 IB2 1 IB12 RD/WR Value after Reset: 02H . AST Asynchronous Timing. Defines the length of the Timing signal (DU = 0) on IOM-2. If synchronous timing is selected (AST=0) the IPAC in LT-S mode will issue the timing request only in the C/I channel of the selected timeslot (C/I = 0000b). This mode is useful for applications where IOM-2 clock signals are not switched off. Here the IPAC can pass the TE initiated activation via C/I = 0000b in IOM-2 cannel 0 upstream to the U-interface device. In case IOM-2 clocks can be turned off during power-down or the LT-S IPAC is pin-strapped to a different timeslot than the U-interface device, synchronous timing signals will not succeed in waking the U-interface device. Under these circumstances asynchronous timing needs to be programmed (AST=1). Here the line DU is set to ZERO for a period long enough to wake any Uinterface device, independent of timeslot or clocks. Typically asynchronous timing is programmed for intelligent NT applications (IPAC pin-strapped to LT-S with NT state machine). Note: The asynchronous timing option is restricted to configurations with the IPAC operating with NT state machine (i.e., LT-S pin-strap & FSMM bit programmed). Closes the loop-back for B1 channel data close to the activated S/Tinterface (i.e., loop-back IOM-2 data) in LT-S mode. Closes the loop-back for B2 channel data close to the activated S/Tinterface (i.e., loop-back IOM-2 data) in LT-S mode. Close complete analog loop-back (2B+D) close to the S/T-interface. Corresponds to C/I = ARL. Transparency is optional. Operational in LT-S mode. Close the loop-back for B1 channel close to the IOM-2 interface (i.e. loopback S/T data). Transparent. IB1 and IB2 may be closed simultaneously. SB1 SB2 SC IB1 Semiconductor Group 303 11.97 PSB 2115 PSF 2115 Appendix IB2 IB12 Close the loop-back for B2 channel close to the IOM-2 interface (i.e. loopback S/T data). Transparent. IB1 and IB2 may be closed simultaneously. Exchange B1 and B2 channels. IB1 and/or IB2 need to be programmed also. Loops back data received from S/T and interchanges it, i.e. B1 input (S/T) → B2 output (S/T) and vice versa. Semiconductor Group 304 11.97 PSB 2115 PSF 2115 Appendix MON-8 IOM®-2 Channel Register The features accessible via the IOM-2 Channel register allow to implement simple switching functions. These make the IPAC the ideal device for intelligent NT applications. Please refer also to the section “IOM-2 channel switching”. Two types of manipulation are possible: the transfer from the pin-strapped IOM-2 channel (0 … 7) into IOM-2 channel 0 and a change of the B1, B2 and D data source. Address: 3h B1L B1D B2L B2D DL 0 CIL CIH RD/WR Value after Reset: 00H B1L B1D Transfers the B1 channel from its pin-strapped location into IOM-2 channel 0. Direction of the B1 channel. The normal direction (input/output) of DU and DD depends on the mode and is shown in table 30 below. By setting B1D the direction for the B1 data channel is inverted. Transfers the B2 channel from its pin-strapped location into IOM-2 channel 0. Direction of the B2 channel. The normal direction (input/output) of DU and DD depends on the mode and is shown in table 30 below. By setting B2D the direction for the B2 data channel is inverted. Transfers the D-channel from its pin-strapped location into IOM-2 channel 0. C/I Channel location: The timeslot position of the C/I Channel can be programmed as “normal“ (LT-S and LT-T modes: pin strapped IOM-2 channel, TE mode: IOM-2 channel 0) or “fixed“ to IOM-2 channel 0 (regardless the selected mode). C/I Channel handling: Normally the C/I commands are read from the pinstrapped IOM-2 channel. With this bit programmed C/I channel access is only possible via the SM/CI register. B2L B2D DL CIL CIH Table 30 DU/DD Direction MODE0 MODE1 /EAW Transmit data on S DU (input) DU (input) DD (input) Receive data on S DD (output) DD (output) DU (output) TE-mode 0 EAW 1 0 LT-T mode 1 LT-S mode 1 Semiconductor Group 305 11.97 PSB 2115 PSF 2115 Appendix MON-8 SM/CI Register This multifeature register allows access to the C/I channel and controls the monitor timeout. Address: 4h CI3 CI2 CI1 CI0 TOD 0 0 0 RD/WR Value after Reset: X0H (X contains the C/I code) C/I Allows the user to access the C/I channel if the CIH bit in the IOM-2 register has been set previously. If the CIH bit was not programmed the content of the CI bits will be ignored and the IPAC will access the IOM-2 C/I channel. When reading the SM/CI register these bits will always return the current C/I indication (independent of CIH bit). Time Out Disable. Allows the user to disable the monitor time-out function. Refer to section “Monitor Timeout” for details. TOD Semiconductor Group 306 11.97 PSB 2115 PSF 2115 Appendix 7.2 Register Address Arrangement 7 6 5 4 3 2 1 0 B-Channel Registers RFIFOB XFIFOB ISTAB MASKB STARB CMDRB MODEB reserved EXIRB XMR XDU EXE 0 RFO 0 RFS 0 0 RME RME RPF RPF B-Channel Receive FIFO B-Channel Transmit FIFO 0 0 XPR XPR 0 0 RLI XTF RAC 0 0 CEC 0 0 0 0 XAC 0 0 AFI RD (00-1F/40-5F) WR (00-1F/40-5F) RD (20/60) WR (20/60) RD (21/61) WR (21/61) RD/WR (22/62) RD/WR (23/63) RD (24/64) XDOV XFW XREP RFR RMC RHR XREP 0 CFT XME XRES 0 TLP MDS1 MDS0 ADM RBCLB RAH1 RAH2 RSTAB RAL1 RAL2 RHCRB XBCL reserved CCR2 RBC7 RAH1 RAH2 VFR RDO CRC RAB HA1 HA0 0 0 C/R RBC0 0 0 LA RD (25/65) WR (26/66) WR (27/67) RD (27/67) RD/WR (28/68) WR (29/69) RD (29/69) RAL1 RAL2 RHCR XBC7 XBC0 WR (2A/6A) RD/WR (2B/6B) SOC 0 XCS0 RCS0 TXD 0 RIE DIV RD/WR (2C/6C) Semiconductor Group 307 11.97 PSB 2115 PSF 2115 Appendix 7 RBCHB XBCH reserved RLCR CCR1 TSAX TSAR XCCR RCCR XBC7 RBC7 D-Channel Registers RFIFOD XFIFOD ISTAD MASKD STARD CMDRD MODED TIMR1 EXIRD XAD1 XAD2 RBCLD SAPR RBC7 RBC0 XMR RME RME RPF RPF D-Channel Receive FIFO D-Channel Transmit FIFO RSC RSC XPR XPR TIN TIN CIC CIC SIN SIN -TIN2 TIN2 MAC0 RD (80 - 9F) WR (80 - 9F) RD (A0) WR (A0) RD (A1) WR (A1) RD/WR (A2) RD/WR (A3) SAW WOV RD (A4) WR (A4) WR (A5) RD (A5) RD (A6) RC PU 0 SC RL5 0 TSNX TSNR 0 ITF 0 1 RL0 0 DMA DMA 6 0 0 5 0 0 4 3 2 1 0 RBC8 XBC8 RD (2D/6D) WR (2D/6D) RD (2E/6E) WR (2E/6E) RD/WR (2F/6F) WR (30/70) WR (31/71) WR (32/72) WR (33/73) OV RBC11 XC XBC11 XCS2 XCS1 RCS2 RCS1 XBC0 RBC0 XDOV XFW XRNR RRNR MBR MAC1 RMC RRES RNR STI XTF RAC XIF XME XRES MDS2 MDS1 MDS0 TMD CNT XDU PCE RFO DIM2 DIM1 DIM0 VALUE SOV MOS Semiconductor Group 308 11.97 PSB 2115 PSF 2115 Appendix 7 SAP1 SAP2 RSTAD TEI1 TEI2 RHCRD RBCHD STAR2 SPCR CIR0 CIX0 MOR0 MOX0 CIR1 CIX1 MOR1 MOX1 C1R C2R STCR B1CR B2CR ADF1 WTC1 WTC2 CI1E 0 CSEL2 CSEL1 CSEL0 ITF TSF TBA2 TBA1 TBA0 ST1 ST0 SC1 SC0 CODR1 CODX1 MR1 1 MX1 1 XAC 0 SPU 0 RSS -0 SDL BAS BAC -0 SPM OV RBC11 0 TLP WFA 0 RBC8 TREC SDET RDA RDO 6 5 4 3 2 1 CRI MCS SA1 SA0 C/R 0 0 0 TA EA EA WR (A6) WR (A7) RD (A7) WR (A8) WR (A9) RD (A9) RD (AA) RD (AB) RD/WR (B0) RD (B1) WR (B1) RD (B2) WR (B2) RD (B3) WR (B3) RD (B4) WR (B4) RD/WR (B5) RD/WR (B6) WR (B7) RD (B7) RD (B8) WR (B8) SAPI1 SAPI2 CRC RAB TEI1 TEI2 C1C1 C1C0 C2C1 C2C0 CIC0 1 CIC1 1 CODR0 CODX0 Semiconductor Group 309 11.97 PSB 2115 PSF 2115 Appendix 7 reserved MOSR MOCR 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 RD/WR (B9) RD (BA) WR (BA) MDR1 MER1 MDA1 MAB1 MDR0 MER0 MDA0 MAB0 MRE1 MRC1 MIE1 MXC1 MRE0 MRC0 MIE0 MXC0 General IPAC Registers CONF ISTA MASK ID ACFG AOE ARX ATX PITA1 PITA2 POTA1 POTA2 PCFG SCFG TIMR2 AMP INT1 INT1 CFS INT0 INT0 TEM ICD ICD PDS EXD EXD IDH ICA ICA SGO EXA EXA ODS ICB ICB IOF EXB EXB RD/WR (C0) RD (C1) WR (C1) RD (C2) OD7 OE7 AR7 AT7 OD6 OE6 AR6 AT6 OD5 OE5 AR5 AT5 0 0 0 OD4 OE4 AR4 AT4 OD3 OE3 AR3 AT3 OD2 OE2 AR2 AT2 TNRX TNRX TNTX TNTX EL1 0 0 0 EL0 0 0 0 RD/WR (C3) RD/WR (C4) RD (C5) WR (C5) RD/WR (C6) RD/WR (C7) RD/WR (C8) RD/WR (C9) RD/WR (CA) RD/WR (CB) RD/WR (CC) ENA DUDD ENA DUDD ENA DUDD ENA DUDD SRES DPS PRI TMD ACL TXD 0 LED TLEN PLD FBS CSL2 CSL1 CSL0 TSLT CNT Semiconductor Group 310 11.97 PSB 2115 PSF 2115 Appendix 7.3 State Diagrams TE/LT-T Modes State Diagram DC DI TIM i0 ARp DI TIM ARp i0 DI i0 DI TIM it * TMI TMI 5) Test Mode i F3 Power Down PU AR p 3) F4 Pend. Act. i1 i0 2) PU TIM DIS F3 Power Up i0 i0 i0 TMI Any State i0 RSY i4 X F5/8 Unsynchron i0 i0 i2 i0 X DI 2) 1) Reset/Loop TIM AR X 2) i2 & i4 RST Any State RES+ARL F6 Synchronized i3 i4 AI p 4) i2 i2 X 2) DI i2 & i4 i0 DR AR TIM F7 Activated i3 Slip SLIP i2 X 2) F3 Pend. Deact. i0 i0 i4 0.5 ms i2 & i4 OUT IN IOM R Ind. Cmd. F7 Slip Detected i3 i4 S/T ix State ir ITD09694 Notes: 1. See state diagram for unconditional transitions for details 2. x = TM1 or TM 2 or RES or ARL x = TM1 & TM2 & RES & ARL 3. ARP = AR8 or AR10 4. AIP = AI8 or AI10 5. TMI = TM1 or TM2 B- and D-channel on SX transparent if the command equals to AR8 or AR10. Figure 119 State Transition Diagram in TE/LT-T Modes Semiconductor Group 311 11.97 PSB 2115 PSF 2115 Appendix F3 Power Down Any State ARL F3 Power Up RST F3 Power Down DI ARL ARL TIM RES ARL TIM RES RES DI * Loop A Closed i3 i3 * i3 1) Reset i0 RSY ARL AIL Loop A Activated DI i3 * RES TIM RES IOM Any State S/T ix R OUT IN Ind. Cmd. State ir ITD09695 Note: 1. In state “loop A activated” I3 is the internal signal, the external signal is I0. Figure 120 State Diagram of the TE/LT-T Modes, Unconditional Transitions Semiconductor Group 312 11.97 PSB 2115 PSF 2115 Appendix LT-S Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI 2) Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 AR DC ARD i0 G2 Pend. Act. i2 i3 AI DC ARD i3 DR G3 Activated i4 i3 RSY i3 DR OUT i3 DC ARD IOM R IN Ind. Cmd. G2 Lost Framing i2 i3 DR State S/T ix ir ITD09696 Notes: 1. ARD stands for AR or ARL 2. TMI = TM1 or TM2 Figure 121 State Transition Diagram in LT-S Mode Semiconductor Group 313 11.97 PSB 2115 PSF 2115 Appendix Intelligent NT Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State G4 Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 i0 AR DC DR G1 i0 Detected i0 * ARD1) AR ARD G2 Pend. Act. i2 i3 AID RSY ARD G2 Lost Framing S/T i2 RSY DR i3 AID ARD1), AID 2) 2) DR i3 OUT IN i3 & ARD1) RSY i3 AI ARD DR IOM R Ind. Cmd. G2 Wait for AID i2 i3 State S/T ix ir ARD 1) AI i3 & AID 2) RSY i4 i3 ITD09697 RSY RSY G3 Lost Framing U AID DR G3 Activated Notes: 1. ARD = AR or ARL 2. AID = AI or AIL i2 * Figure 122 NT Mode State Diagram Semiconductor Group 314 11.97 PSB 2115 PSF 2115 Appendix 7.4 C/I Codes Code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LT-S IN DR RES TM1 TM2 – – – – AR – ARL – – – – DC OUT TIM – – – RSY – – – AR – – CVR AI – – DI NT IN DR RES TM1 TM2 RSY – – – AR – ARL – AI – AIL DC OUT TIM – – – RSY – – – AR – – CVR AI – – DI TE/LT-T IN TIM RES TM1 TM2 – – – – AR8 AR10 ARL – – – – DI OUT DR RES TM1 TM2 SLIP 1) RSY – – PU AR – ARL CVR AI8 AI10 AIL DC 1) In LT-T mode only AI Activation Indication DI AI8 Activation Indication with high priority DR AI10 Activation Indication with low priority PU AIL Activation Indication Loop RES AR Activation Request RSY AR8 Activation Request with high priority SLIP AR10 Activation Request with low priority TIM ARL Activation Request Loop TIM1 CVR Code Violation Received TM2 DC Deactivation Confirmation Deactivation Indication Deactivation Request Power-Up Reset Resynchronizing IOM Frame Slip Timer Test Mode 1 (2-kHz signal) Test Mode 2 (96-kHz signal) Semiconductor Group 315 11.97 PSB 2115 PSF 2115 Index A Abort 50, 64 Activation 52, 88, 92, 188, 191 Activation LED 93 ARCOFI 65 Auto mode 43, 50 Auxiliary interface 143 B BAC-bit 55, 61 Back to back frames Block diagram 26 I I frames 50 I.430 55–57, 69 I/O lines 143 ICC 59 IEC-Q TE 59 Indirect address mode 99 Intelligent NT 59, 65 Interrupt input 144 Interrupt mode 100, 174, 180 Interrupt output 143 IOM-2 Interface 113 ISAC-S TE 32 L LAPB 42 LAPD 42 LED Output 93, 144 Level detection 88 Logic symbol 16 Loopback 66, 96 LT-S mode 68, 122 LT-T mode 59, 68, 121 M Message transfer modes B-channel 32 D-channel 42 Microprocessor interface 98 MON-1 137 MON-2 137 MON-8 65, 72, 301 MONITOR channel 129 MONITOR Procedure Timeout MOS interrupt 171 Multiline applications 151 Multiplexed mode 98 177 C C/I-channel 57, 139 Channel switching 65 CIC interrupt 170 Clock mode 5 36 Continuous transmission (DMA mode) 40 D Data encoding 38 Data path switching 68 Data underrun 50 D-channel access 54 D-channel collision 51 Deactivation 53, 92, 188, 191 DMA mode 100, 104, 143, 178, 181 E E-bit 56 Exchange Awake 94 External awake 94 F Features 15 FIFO structure 108 FSC/BCL generation 150 Functional description 32 H HSCX-TE 32, 36 136 Semiconductor Group 316 11.97 PSB 2115 PSF 2115 Index N Non-auto mode B-channel 32 D-channel 43 Non-multiplexed mode NRZ 38 NRZI 38 NT state machine 59 O Open drain 117 Output driver 117 Overview 14 P PCM interface 146 Phase deviation 84 Pin configuration 17 Pin descriptions 18 Point to multipoint 59 Point-to-point protocols 42 Power down 88–89 Pre-filter compensation 84 Priority class 57 Priority mechanism 56 Protection circuitry 84 Pulse mask 83 Push pull 117 Q Q-bit 72 98 S S/Q-channel 137 S/T-interface coding 69 S/T-interface multiframing 71 S-bus 54 Serial interface 36 Software reset 112 State diagrams 192 Stop/Go bit 51, 55, 61, 142 Strobe signal 116 Subscriber Awake 94 System integration 27 T TE mode 55, 68, 119 Test Mode 96 Test signals 97 TIC bus 141 TIC-bus 54 Timer 110 Timeslot assignment B-channel 36 PCM interface 152 Transformer 82 Transmit data B-channel 35, 174 D-channel 49, 183 Transmitter disable 89 Transparent modes B-channel 33, 39 D-channel 34, 180 44, 50 R Receive data B-channel D-channel 45, 185 Receive length check 40 W Watchdog 94 Window size 51 Semiconductor Group 317 11.97