BF 1012S
Silicon N-Channel MOSFET Tetrode • For low noise, high gain controlled input stages up to 1GHz • Operating voltage 5V • Integrated stabilized bias network
ESD: Electrostatic discharge sensitive device, observe handling precaution!
Type
Marking Ordering Code Q62702-F1627
Pin Configuration 1=S 2=D 3 = G2 4 = G1
Package SOT-143
BF 1012S NYs
Maximum Ratings Parameter Drain-source voltage
Symbol
Value 16 25 10 3 200 -55 ...+150 150
Unit V mA V mW °C
VDS ID
±I G1/2SM +VG1SE
Continuos drain current Gate 1/gate 2 peak source current Gate 1 (external biasing) Total power dissipation, T S ≤ 76 °C Storage temperature Channel temperature
Ptot T stg T ch
Thermal Resistance Channel - soldering point
Rthchs
≤370
K/W
Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode.
Semiconductor Group Semiconductor Group
11
Au 1998-11-01 -25-1998
BF 1012S
Electrical Characteristics at TA = 25°C, unless otherwise specified. Parameter DC characteristics Drain-source breakdown voltage Symbol min. Values typ. 12 0.9 max. 12 16 60 50 500 µA nA µA mA V V Unit
V(BR)DS
±V (BR)G1SS ±V (BR)G2SS +I G1SS ±I G2SS
16 8 10 8 -
I D = 300 µA, -V G1S = 4 V, - V G2S = 4 V Gate 1 source breakdown voltage
±I G1S = 10 mA, VG2S = V DS = 0 Gate 2 source breakdown voltage ±I G2S = 10 mA, VG1S = 0 V, V DS = 0 V Gate 1 source current
VG1S = 6 V, V G2S = 0 V
Gate 2 source leakage current ±VG2S = 8 V, V G1S = 0 V, V DS = 0 V Drain current
I DSS I DSO VG2S(p)
VDS = 12 V, V G1S = 0 , V G2S = 6 V
Operating current (selfbiased)
VDS = 12 V, V G2S = 6 V
Gate 2-source pinch-off voltage
VDS = 12 V, I D = 100 µA
AC characteristics Forward transconductance (self biased)
g fs Cg1ss Cdss G ps F 800
∆Gps
26 18 40
30 2.1 0.9 22 1.4 50
2.7 -
mS pF
VDS = 12 V, V G2S = 6 V, f = 1 kHz
Gate 1-input capacitance (self biased)
VDS = 12 V, V G2S = 6 , f = 1 MHz
Output capacitance (self biased)
VDS = 12 V, V G2S = 6 , f = 1 MHz
Power gain (self biased) dB
VDS = 12 V, V G2S = 6 , f = 800 MHz
Noise figure (self biased)
VDS = 12 V, V G2S = 6 , f = 800 MHz
Gain control range (self biased)
VDS = 12 V, V G2S = 6 V, f = 800 MHz
Semiconductor Group Semiconductor Group 22
Au 1998-11-01 -25-1998
BF 1012S
Total power dissipation P tot = f (T S)
Drain current ID = f (VG2S)
300
15 mA
mW
12 11
P tot
200
10
ID
150 100 50 0 0 120 °C
9 8 7 6 5 4 3 2 1
20
40
60
80
100
150
0 0.0
1.0
2.0
3.0
4.0
V
6.0
TS
VG2S
Insertion power gain | S 21 | 2 = f (V G2S)
Forward transfer admittance | Y 21 | = f (V G2S)
10 dB
28
mS
24 -5 22 20
| S21 |2
-10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 0.0 1.0 2.0 3.0 4.0
V
|Y21|
18 16 14 12 10 8 6 4 2
6.0
0 0.0
1.0
2.0
3.0
4.0
V
6.0
VG2S
VG2S
Semiconductor Group Semiconductor Group
33
Au 1998-11-01 -25-1998
BF 1012S
Gate 1 input capacitance Cg1ss = f (V g2s) f = 200MHz
Output capacitance C dss = f (V G2)
f = 200MHz
3.0 pF
3.0 pF
2.4 2.2
2.4 2.2
Cg1ss
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 1.0 2.0 3.0 4.0
V
Cdss
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
6.0
0.0 0.0
1.0
2.0
3.0
4.0
V
6.0
VG2S
VG2S
Semiconductor Group Semiconductor Group
44
Au 1998-11-01 -25-1998
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