Q67000-A-5000

FM-IF with Counter Output, Field Strength Indicator, Noise Detector and MUTE Setting TDA 4320X 1 1.1 • • • • • • • Overview Features 7-stage limiter amplifier Coincidence demodulator Counter output with request input Field strength output Multipath identification circuit Adjustable muting depth (with full muting ≥ 80 dB) This device is ESD protected Ordering Code Q67000-A-5000 P-DSO-16-1 Type TDA 4320X Package P-DSO-16-1 Semiconductor Group 35 04.96 TDA 4320X 1.2 Pin Configuration (top view) P-DSO-16-1 Figure 1 1.3 1 Pin Definitions and Functions Function Ground Decoupling capacitors for bias, VS and VREF Pins are to be connected directly to Pin 1 GND Pin No. Symbol 2 Multipath Multipath identification input identification input High impedance input (Ri ~ 10 kΩ). This input receives the filtered field strength output (high pass or band pass). Rectifier time constant Multipath identification output MUTE input Rectifier time constant Determines the attack and release time of the identification circuit. Multipath identification output Open npn-collector output, which is low during (V4/V1 ≤ 0.7 V) multipath interference. MUTE input For DC voltage (usually derived from field strength output voltage) which attenuates the AF output voltage by the setting muting depth (Pin 7). Max. attenuation when V5 = 0 V, no attenuation when V5 ≥ 0.5 V. AF output Demodulated FM-IF. 36 04.96 3 4 5 6 AF output Semiconductor Group TDA 4320X 1.3 7 Pin Definitions and Functions (cont’d) Function MUTE depth Adjustment by connecting a dc voltage to ground the requested muting depth can be set. Maximal attenuation of AF output voltage with V7 = 2.4 V (typ. 38 dB), minimal attenuation with V7 = 4.8 V (typ. 0 dB). Full muting with V7 ≤ 1 V (≥ 80 dB). Demodulator tank circuit Driven via two on-chip capacitors (approx.15 pF ± 25 %). The tank circuit voltage should be typ. 400 mVpp. Demodulator circuit Reference voltage Should be RF decoupled to Pin 1. IF counter output Provides the IF carrier frequency (low impedance output Rout ≈ 1.5 kΩ). Supply voltage RF decoupled to Pin 1 Field strength output Supplies a DC voltage proportional to the IF input level with very low delay time. Field strength adjust Adjustment of slope and starting point of field strength output voltage IF input bias To be RF decoupled to Pin 1 IF input FM-lF input MUTE depth Pin No. Symbol 8 Demodulator tank circuit Demodulator circuit Reference voltage IF counter output 9 10 11 12 13 VS Field strength output Field strength adjust IF input bias IF input 14 15 16 Semiconductor Group 37 04.96 TDA 4320X 1.4 Functional Block Diagram Figure 2 Semiconductor Group 38 04.96 TDA 4320X 2 Functional Description The FM-IF demodulator TDA 4320X has been developed especially for car radio applications. The on-chip multipath identification circuit activates an interference suppression circuit in case of multipath interferences. 3 Circuit Description The IC includes a 7-stage capacitive coupled limiter amplifier with coincidence demodulator and AF output. The AF output signal can be continuously attenuated to decrease the noise. In case of multipath interferences, the TDA 4320X includes an identification circuitry. There is a field strength output (with min. 76 dB dynamic range, typ. ± 1 dB nonlinearity and typ. ± 3 dB temperature drift), an IF counter output and an adjustable muting (with full muting ≥ 80 dB). Semiconductor Group 39 04.96 TDA 4320X 4 4.1 Electrical Characteristics Absolute Maximum Ratings Symbol 0 Limit Values min. max. 13.2 150 125 105 –4 4 V °C °C K/W kV Unit Remarks TA = – 40 °C to + 85 °C Parameter Supply voltage VS Junction temperature Tj Storage temperature TS Thermal resistance (system-air) RthSA ESD voltage, HBM (1.5 kΩ, 100 pF) VESD Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 4.2 Operating Range Symbol Limit Values min. Supply voltage Ambient temperature max. 13.2 85 V °C 7.5 – 40 Unit Remarks TA = – 40 °C to + 85 °C Parameter VS TA Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 40 04.96 TDA 4320X 4.3 AC/DC Characteristics VS = 10 V; filF = 10.7 MHz; ∆f = 75 kHz; fmod = 1 kHz; ViIFrms = 10 mV; TA = – 40 °C to + 85 °C Parameter Current consumption Stabilized voltage Field strength output – Dynamic range – Nonlinearity – Temperature drift – Load capacitance – Load resistance 1 Symbol Limit Values min. typ. max. mA 5.1 V dB dB ±3 50 dB pF kΩ 5.5 2.7 30 480 60 76 Signal-to-noise ratio Counter output voltage 76 50 3.2 4.3 2.5 2.5 Discharge current Pin 3 840 1.2 6.0 3.2 1.2 V V V µVrms 30 4.5 4.8 80 ±1 Unit Test Condition Test Circuit 1 1 D1 D2 D3 I12 V10 V13 V5 = 4.8 V; V7 = 4 V V5 = 4.8 V; V7 = 4 V V5 = 4.8 V; V7 = 4 V V13 V13 V13 Input voltage for limiter threshold AF output voltage AM suppression 5.0 2.2 0 VilFrms = 200 mV VilFrms = 1 mV VilFrms = 0 mV VqAF = – 3 dB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V16 VqAF aAM aS/N V11 mVrms V5 = 4.8 V; V7 = 4 V % dB dB dB Total harmonic distortion THDqAF V5 = 4.8 V; V7 = 4 V m = 80 % m = 30 % V5 = 4.8 V; V7 = 4 V mVrms CL = 5 pF; Ri11 = 1.5 kΩ mVrms f2 = 20 kHz mVrms f2 = 300 kHz mA mA µA Noise detector sensitivity V2 V2 Charge current Pin 3 I3 f2 = 20 kHz; V2 ≥ 6 mVrms f2 = 300 kHz; V2 ≥7 mVrms V2AC = 0 V I3 20 Semiconductor Group 41 04.96 TDA 4320X 4.3 AC/DC Characteristics (cont’d) VS = 10 V; filF = 10.7 MHz; ∆f = 75 kHz; fmod = 1 kHz; ViIFrms = 10 mV; TA = – 40 °C to + 85 °C Parameter AF MUTE Symbol Limit Values min. typ. max. dB 2 38 46 dB dB dB dB V V 0 –2 30 80 80 Voltage for MUTE OFF Voltage for MUTE ON 0.7 0 Unit Test Condition Test Circuit aAF V5 = 4.8 V; V7 = 4.8 V D4 V5 = 0 V; V7 = 4.8 V V5 = 0 V; V7 = 2.4 V V5 = 0 V; V7 ≤1.0 V D4 D4 D4 1 1 V5 = 4.8 V; V7 ≤ 1.0 V D4 V5 V5 VS = 10 V; filF = 10.7 MHz; ∆f = 75 kHz; fmod = 1 kHz; ViIFrms = 10 mV; TA = 25 °C Parameter Current consumption Stabilized voltage Field strength output Dynamic range Nonlinearity Temperature drift Load capacitance Load resistance Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit I12 V10 V13 30 4.6 74 4.8 80 ±1 ±3 50 1 5.0 mA V dB dB dB pF kΩ V V V V5 = 4.8 V; V7 = 4 V 1 V5 = 4.8 V; V7 = 4 V 1 V5 = 4.8 V; V7 = 4 V D1 D2 D3 V13 V13 V13 Input voltage for limiter threshold AF output voltage 5.1 2.3 0 5.5 2.7 30 5.9 3.1 1.1 39 750 1.2 VilFrms = 200 mV VilFrms = 1 mV VilFrms = 0 mV 1 1 1 1 V16 VqAF aAM µVrms VqAF = – 3 dB 550 60 76 650 mVrms V5 = 4.8 V; V7 = 4 V 1 % dB dB V5 = 4.8 V; V7 = 4 V 1 Total harmonic distortion THDqAF AM suppression m = 80 % m = 30 % 1 1 82 Semiconductor Group 42 04.96 TDA 4320X 4.3 AC/DC Characteristics (cont’d) VS = 10 V; filF = 10.7 MHz; ∆f = 75 kHz; fmod = 1 kHz; ViIFrms = 10 mV; TA = 25 °C Parameter Signal-to-noise ratio Counter output voltage Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit aS/N V11 76 50 2 2.7 1.6 1.6 84 80 3.2 4.3 2.5 2.5 20 0 6 7 4 4 40 dB V5 = 4.8 V; V7 = 4 V 1 1 1 1 1 1 1 D4 D4 D4 D4 D4 1 1 mVrms CL = 5 pF; Ri11 = 1.5 kΩ mVrms f2 = 20 kHz mVrms f2 = 300 kHz mA mA µA dB 2 dB dB dB dB V 0.1 V f2 = 20 kHz; V2 ≥ 6 mVrms f2 = 300 kHz; V2 ≥ 7 mVrms V2AC = 0 V V5 = 4.8 V; V7 = 4.8 V V5 = 0 V; V7 = 4.8 V V5 = 0 V; V7 = 2.4 V V5 = 4.8 V; V7 ≤1.0 V V5 = 0 V; V7 ≤ 1.0 V Noise detector sensitivity V2 V2 Charge current Pin 3 I3 Discharge current Pin 3 AF MUTE I3 aAF 10 –2 32 80 80 Voltage for MUTE OFF Voltage for MUTE ON 38 44 V5 V5 0.5 0 Semiconductor Group 43 04.96 TDA 4320X Test Circuit 1 Figure 3 Semiconductor Group 44 04.96 TDA 4320X Application Circuit Figure 4 Semiconductor Group 45 04.96 TDA 4320X Diagrams Diagram D1 VF Dynamics The dynamic range of VF voltage is determined by the test points M1 through M4 as follows: M1: M2: M3: M4: test point (at ViIF = – 60 dBm) supplies VF(M1) test point (at ViIF = – 20 dBm) supplies VF(M2) test point (at ViIF = – 90 dBm) supplies VF(M3) test point (at ViIF = + 5 dBm) supplies VF(M4) Hence follows: MVF max := – 20 dBm + (VF(M4) – VF(M2))/(VF(M2) – VF(M1)) × 40 dB MVF min := – 60 dBµV – (VF(M1) – VF(M3))/(VF(M2) – VF(M1)) × 40 dB VF Dynamics = MVF max – MVF min Semiconductor Group 46 04.96 TDA 4320X Diagram D2 Test points to determine VF linearity: VF is determined at 25 °C Slope: m = (VF(M2) – VF(M1))/40 dB. The tolerance range of the VF-linearity is determined by two parallel lines: VF max = VF(M1) + m(M + 60 dB + 1 dB) VF min = VF(M1) + m(M + 60 dB – 1 dB) The VF values within the VF dynamic range (MVF min ≤ M ≤ MVF max) must be inside the predetermined tolerance range: VF min ≤ VF(M) ≤ VF max Semiconductor Group 47 04.96 TDA 4320X Diagram D3 Test points to determine VF temperature drift: VF-temperature drift: it is determined within – 40 to + 85 °C. Slope: m = (VF(M2) – VF(M1))/40 dB (at 25 °C). The tolerance range of the VF-temperature is determined by two parallel lines: VF max = VF(M1) + m(M + 60 dB + 3 dB) VF min = VF(M1) + m(M + 60 dB – 3 dB) The VF values for temperatures between – 40 to + 85 °C within the VF dynamic range (MVF min ≤ VF ≤ MVF max) must be inside the predetermined tolerance field: VF min ≤ VF(M) ≤ VF max Semiconductor Group 48 04.96 TDA 4320X Diagram D4 Mute Characteristics Semiconductor Group 49 04.96 TDA 4320X 5 Package Outlines P-DSO-16-1 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 50 Dimensions in mm 04.96 GPS05119