Q67000-H8437

Quad Driver Incl. Short-Circuit Signaling FZL 4145 D Bipolar IC Features q q q Short-circuit shutdown with clock generator Four driver circuits for controlling power transistors Overload and short-circuit signaling P-DIP-18-1 Type FZL 4145 D General Description Ordering Code Q67000-H8437 Package P-DIP-18-1 The IC comprises four driver circuits capable of driving power transistors for high output currents. The output transistors are protected against short-circuit to ground and supply voltage. The input threshold can be adjusted between 1.5 V and 7 V. Overload or shortcircuit failure at an output will be indicated at pin SQ (signaling output). Functional Description Each driver circuit has one active high driver input Dl and a common enable input (ENA) (active high) is provided for all stages. The (Q) outputs are designed to drive the output transistors. The load current is sampled via pin W. If the load current exceeds the preset value, the output stage switches off. Switching-on again is provided by the built-in clock generator. Its operation requires an external capacitor CT at pin C. If CT is bridged by a break-key, switching on can only be carried out by operating a key. The duty cycle of the clock generator is 1:50 (e.g. 40 µs/2 ms with CT = 33 nF). In case of overcurrent or short-circuit failure at any output stage the signaling output (SQ) will go low. In clock-governed operation (i.e. when there is automatic switching on by the clock and not by a key), SQ goes high and low at the clock rate as long as a shortcircuit or overload exists. SQ is an open-collector output. Unused W pins must be connected to Vs. Open W pins would simulate a short-circuit and activate the signaling output. Semiconductor Group 1 09.94 FZL 4145 D Pin Configuration (top view) Semiconductor Group 2 FZL 4145 D DI ENA C Q TS W SQ GND Driver inputs Enable input Clock capacitor Outputs Input for threshold switching Input for output current limiter Signaling output Ground Block Diagram The switching threshold at inputs Dl and ENA can be adjusted between 1.5 V and 7 V via connection TS: VTS = 0 V; VTS = 0 to 5 V; VTS = VS: input threshold = 1.5 V (for 5 V logic) input threshold = VTS + 1.5 V input threshold = 7 V (for 12/15 V and 24/28 V logic) If the output is disabled due to the logic states of inputs Dl or ENA this disable is effective over the total supply voltage range between VS = 0 V and VS = 35 V. The inputs are protected with clamp diodes. Semiconductor Group 3 FZL 4145 D Absolute Maximum Ratings Parameter Symbol Limit Values min. Supply voltage max. 35 45 35 45 V V V V V V mA mA mA mA mW °C K/W K/W 100 ms duration, 1 s interval 1) Unit Remarks VS VS VDI, ENA VTS, SQ VQ , VC VW IDI, ENA IDI, ENA – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 Input voltage at Dl and ENA Voltage at TS and SQ Output voltage VQ and voltage at C Voltage at W VS VS 1 2 5 8 50 VS – 5 –3 –6 –6 3) 2) 2) Input current at DI and ENA IDI, ENA 100 ms duration, 1 s interval 2) 100 µs duration, 1 ms interval Output current at SQ Power dissipation of all input diodes Storage temperature Thermal resistance system - air system - case Operating Range Supply voltage for input threshold 1.5 V 1.5 V to 6.5 V 7V Ambient temperature Notes: 1) 2) ISQ Ptot Tstg Rth SA Rth SC – 65 125 65 45 VS VS VS TA 4.5 VTS + 4.5 10 – 25 35 35 35 85 V V V °C VTS = 0 V VTS = 0 V to 5 V VTS = VS VDI, ENA > 35 V requires a protective resistor before Dl, ENA. VDI, ENA may increase to more than 35 V during current nodes. 3) Unused W connections must be connected to V . S Semiconductor Group 4 FZL 4145 D Characteristics Supply voltage 4.5 V ≤ VS ≤ 30 V Parameter Symbol min. Supply current H-input voltage at DI, ENA H-input voltage at DI, ENA L-input voltage at DI, ENA L-input voltage at DI, ENA Input current at DI, ENA L-output voltage at SQ Output current available1) Current from TS Switching threshold at W Current in W Current from C Current in C Upper switching threshold at C Lower switching threshold at C Saturation voltage at T2) H-output voltage Limit Values typ. 6 2 8 0.7 6 50 200 0.5 1.5 1.7 2.5 max. 8.5 mA V V V V µA V mA mA 10 µA Unit Test Condition IS VIH VIH VIL VIL IDI, ENA VSQ L IQ IQ – ITS VENA = 0 V, VW = VS VTS = 0 V VTS = VS VTS = 0 V VTS = VS 0.5 V ≤ VDI, ENA ≤ 30 V ISQ = 5 mA VQ = VS – 1.5 V TA = 0 °C VQ = VS – 1.5 V VTS = 0 V 2 VW IW – IC IC VCU VCL VQ R VQ H VS – 0.6 VS – 0.5 VS – 0.4 V 12 0.6 1.6 0.6 20 1 2.1 100 34 1.7 1.7 µA µA mA V V V V TA = 20 °C TA = 20 °C TA = 20 °C TA = 20 °C VW = VS – 2 V, IQ = 0 VENA = 0 V 0.9 1.2 VS – 0.3 VS – 0.25 VS – 0.02 1) 2) The actual output current is typically 0.5 mA higher, a value which is required as current for the short-circuit protection. However, only the value specified above is available to drive the external output transistors. See block diagram Semiconductor Group 5 FZL 4145 D DI ENA C SQ Q TS W Schematic Circuit Diagram of One Stage Semiconductor Group 6 Driver input Enable input Clock capacitor Signaling output Output Input for threshold switching Input for output current limiter FZL 4145 D Mode of Operation: Switching-ON again after Overload with Key H Semiconductor Group 7 FZL 4145 D Mode of Operation: Automatic Switching-ON again after Overload Semiconductor Group 8 FZL 4145 D Typical Application Circuits The load conditions at Q depend on the permissible power dissipation of the used power transistors. The pulsed power dissipation in case of a short circuit must be observed. In order to suppress oscillations of the power stage in case of a short circuit, a capacitor C at Q1 to Q4 is necessary if e.g. fast switching transistors are used. Typical value X of C: approx. 20 nF. The output circuit 1 is suited for currents up to approx. IQ = 100 mA. The output circuit 2 and 3 are suited for currents up to approx. IQ = 2 A. A minimum power dissipation can be achieved with circuit 3. A break key in parallel to CT allows a manual switch-on in case of short-circuit. RP = Precision resistor (current measurement) CT = 0.8 x tp (nF, µs) tp = Short-circuit current pulse length Note: Circuit 1 does not permit a capacitor between Q1 and Q4 and the collector. Circuit 2 does not permit a capacitor between Q1 and Q4 and base or emitter, respectively. Otherwise too high current spikes would arise in case of a short circuit. Semiconductor Group 9 FZL 4145 D Typical Application of Short-Circuit Signaling Output SQ 1. LED Display 2. TTL/CMOS/LSL Driving If the pulses appearing at SQ during clocked operation disturb the remainder of the circuit, a lowpass filter will be necessary. For a load current of ISQ = 1 mA a capacitor C of approx. 10 nF is necessary to limit the output pulses of up to 10 µs (depending on CT) to 1 V. Signaling occurs after approx. 50 µs. Semiconductor Group 10