TLE4470

Dual Low-Drop Voltage Regulator TLE 4470 Features • • • • • • • • • • • • • Stand-by output 180 mA; 5 V ± 2 % Adjustable reset switching threshold Main output 350 mA; tracked to the stand-by output Low quiescent current consumption in standby mode Disable function for main output Wide operation range: up to 45 V Very low dropout Power-On-Reset circuit sensing the stand-by voltage Early warning comparator for supply undervoltage Output protected against short circuit Wide temperature range: – 40 °C to 150 °C Over-temperature protection Over-load protection P-DSO-14-4 P-DSO-20-6 Type TLE 4470 GS TLE 4470 G Functional Description Ordering Code Q67006-A9309 Q67006-A9308 Package P-DSO-14-4 (SMD) P-DSO-20-6 (SMD) The TLE 4470 is a monolithic integrated voltage regulator with two very low-drop outputs, a main output Q2 for loads up to 350 mA and a stand by output Q1 providing a maximum of 180 mA. The device is available in both the P-DSO-14-4 and P-DSO-20-6 packages. It is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against over load, short circuit and over temperature. Of course the TLE 4470 can also be used in other applications where two stabilized voltages are required. The device operates in the wide temperature range of – 40 °C to 150 °C. The stand by regulator transforms an input voltage VI in the range of 5.6 V ≤ VI ≤ 45 V to VQ1rated = 5 V within an accuracy of 2%, whereas the main regulator is adjustable. By use of an external voltage divider the main output voltage can be set to VQ2 ≥ 5 V for the Semiconductor Group 1 1998-11-01 TLE 4470 TLE 4470 G type (P-DSO-20-6 package). VQ1 is compared to the voltage at pin VA, which is proportional to the output voltage VQ2. A control amplifier drives the base of the series PNP transistor via a buffer. The main output voltage VQ2 is tracked to the accuracy of the stand by output. For the TLE 4470 GS (P-DSO-14-4 package) the output voltage is fixed to 5 V. To save energy e.g. in battery powered body electronic applications, the main regulator can be switched off via the disable input, which causes the current consumption to drop to 180 µA typical. Two additional features of the TLE 4470 are an early warning comparator (can be used e.g. to monitor the supply voltage VI) and reset generator with an adjustable reset delay time. The TLE 4470 G (P-DSO-20-6 package) has in addition an adjustable reset switching threshold. This feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 V typical. Two functions are included in the reset generator, a power on reset and an under-voltage reset. The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. The reset LOW signal is generated for a certain delay time after the output voltage VQ1 of the regulator has surpassed the reset threshold. An external delay capacitor sets the delay time. The under voltage reset circuit supervises the stand-by output voltage. In case VQ1 falls below the reset switching threshold the reset output is set LOW after a short reaction time. The reset LOW signal is generated down to an output voltage VQ1 of 1 V. Pin Configuration (top view) P-DSO-14-4 D DIS GND GND GND RQ SQ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI P-DSO-20-6 RADJ D DIS GND GND GND GND RQ SQ Q1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SI Ι1 Ι2 GND GND GND GND Q2 Q2 ADJ2 AEP02151 Ι GND GND GND Q2 Q1 AEP02152 Figure 1 Semiconductor Group 2 1998-11-01 TLE 4470 Pin Definitions and Functions P-DSO-20-6 Pin No. 1 Symbol RADJ Function Reset switching threshold adjust; for setting the reset switching threshold connect to a voltage divider from Q1 to GND. If this input is connected to GND, the reset is triggered at the internal threshold. Reset delay; connect a capacitor CD to GND for delay time adjustment Disable input main regulator; Q2 disabled with high signal Ground Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Stand-by regulator output voltage; block to GND with a capacitor CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz Main regulator adjust input; Q2 can be set to higher values by an external divider Main regulator output voltage; block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz Ground Main regulator input voltage; block to GND directly at the IC with a ceramic capacitor Stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor Sense comparator input 2 3 4, 5, 6, 7 8 9 10 11 12, 13 14, 15, 16, 17 18 19 20 D DIS GND RQ SQ Q1 ADJ2 Q2 GND I2 I1 SI Semiconductor Group 3 1998-11-01 TLE 4470 P-DSO-14-4 Pin No. 1 2 3, 4, 5 6 7 8 9 Symbol D DIS GND RQ SQ Q1 Q2 Function Reset delay; connect a capacitor CD to GND for delay time adjustment Disable input main regulator; Q2 disabled with high signal Ground Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Stand-by regulator output voltage; block to GND with a capacitor, CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz Main regulator output voltage; 5 V output tracking to Q1, block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz Ground Main and stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor Sense comparator input 10, 11, 12 13 14 RADJ ADJ2 GND I SI Reset switching threshold adjust not available in P-DSO-14-4 package. Reset is always triggered at the internal threshold. Main regulator adjust input is internally connected to VQ2 Semiconductor Group 4 1998-11-01 TLE 4470 Ι1 19 10 Q1 Reference 18 3 Stand-by-Regulator 12, 13 11 Ι2 DIS V REF Q2 ADJ2 Main Regulator V REF 2 Ιd 8 30 k Ω V Q1 1 30 k Ω 9 D RQ = V RADJTH Reset RADJ SQ SI 20 = Sense 4-7 14-17 GND V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AEB02153 Figure 2 Block Diagram Semiconductor Group 5 1998-11-01 TLE 4470 Absolute Maximum Ratings – 40 °C < Tj < 150 °C Parameter Symbol Limit Values min. Stand-by Regulator Input Voltage VI1 Voltage Current max. Unit Remarks VI1 II1 – 42 – 45 – V mA – Internally limited Main Regulator Input Voltage VI2 Voltage Current Stand-by Output VQ1 Voltage Current Main Output VQ2 Voltage Current VI2 II2 – 42 – 45 – V mA – Internally limited VQ1 IQ1 –1 – 7 – V mA – Internally limited VQ2 IQ2 –1 – 36 – V mA – Internally limited Main Regulator Adjust Input ADJ2 Voltage Current Sense Output SQ Voltage Current Reset Output RQ Voltage Current VADJ2 IADJ2 – 0.3 – 18 – V mA – Internally limited VSQ ISQ – 0.3 –5 25 5 V mA – – VRQ IRQ – 0.3 –5 25 5 V mA – – Semiconductor Group 6 1998-11-01 TLE 4470 Absolute Maximum Ratings (cont’d) – 40 °C < Tj < 150 °C Parameter Symbol Limit Values min. Disable Input DIS Voltage Current Sense Input SI Voltage Current Reset Delay D Voltage Current max. Unit Remarks VDIS IDIS – 42 –2 45 2 V mA – – VSI ISI – 25 –2 18 2 V mA – – VD ID – 0.3 –2 7 2 V mA – – Reset Switching Threshold Adjust RADJ Voltage Current Temperatures Junction temperature Storage temperature VRADJ IRADJ – 0.3 – 7 – V mA – Internally limited Tj Tstg – 50 – 50 150 150 °C °C – – Note: ESD-Protection according to MIL Std. 883: ± 2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 7 1998-11-01 TLE 4470 Operating Range Parameter Stand-by regulator input voltage Main regulator input voltage Stand-by regulator output current Main regulator output current Disable input voltage Sense input voltage Junction temperature Thermal Resistances Junction pin Junction ambient Symbol Limit Values min. max. 45 45 180 350 45 17 150 V V mA mA V V °C – – – – – – – 5.6 VQnom + 0.6 V Unit Remarks VI1 VI2 IQ1 IQ2 VDIS VSI Tj 0 0 – 0.3 – 0.3 – 40 Rthj-pin Rthj-a – – 25 65 K/W K/W Measured to pin 4 – Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 8 1998-11-01 TLE 4470 Electrical Characteristics VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. Stand-by Regulator Output 1 Output voltage Output current limitation Output drop voltage; VDRQ1 = VI1 – VQ1 typ. max. Unit Test Condition VQ1 IQ1 VDRQ1 4.90 180 – 5.0 280 300 5.10 – 500 V mA mV 1 mA < IQ1 < 100 mA see note 1 IQ1 = 100 mA; see note 1 Current Consumption Quiescent current; stand-by Iq = II1 – IQ1 Quiescent current Iq = II1 – IQ1 Iq – – 180 180 4 250 300 6 µA µA mA IQ1 = 300 µA; Tj = 25 °C VDIS > VDISH IQ1 = 300 µA; VDIS > VDISH Iq – IQ1 = 100 mA Regulator Performance Load regulation Load regulation Line regulation ∆VQ1 ∆VQ1 ∆VQ1 – – – – 15 5 5 60 0.3 – – – 50 25 20 – – 5.5 – 10 mV mV mV dB 1 mA < IQ1 < 150 mA; 1 mA < IQ1 < 100 mA; IQ1 = 1 mA; 6 V < VI1 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 VSS Power-Supply-Ripple- PSRR Rejection Temperature output voltage drift dVI1/dt stability Value of output capacitance ESR of output capacitance Semiconductor Group ∆VQ1/∆T – mV/K – V µF Ω no reset occurs; note 3 – at 10 kHz VQ1 CQ1 RESRQ1 4.5 6 – 9 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. Main-Regulator Output 2 Output voltage tracking accuracy Output voltage tracking accuracy Adjust input current Output current limitation Output drop voltage VDRQ2 = VI2 – VQ2 typ. max. Unit Test Condition VQ2 – VQ1 – 25 VQ2 – VQ1 – 25 5 5 25 25 mV mV 5 mA < IQ2 < 100 mA; 6 V < VI2 < 40 V 5 mA < IQ2 < 250 mA; 7 V < VI2 < 28 V see note 2 – see note 1 IADJ2 IQ2 VDRQ2 –1 350 – – 500 300 1 – 600 µA mA mV IQ2 = 200 mA; see note 1 Current Consumption Quiescent current; Iq = II – IQ Quiescent current; Iq = II – IQ Iq Iq – – 7 250 15 500 mA µA Tj = 25 °C IQ2 = 200 mA IQ1 = 300 µA IQ2 = IQ1 = 300 µA; Regulator Performance Load regulation Line regulation ∆VQ2 ∆VQ2 – – – 5 5 60 0.5 – – 25 20 – – 5.5 – mV mV dB 5 mA < IQ2 < 200 mA; IQ2 = 5 mA; 6 V < VI2 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 Vss Power-Supply-Ripple- PSRR Rejection Temperature output voltage drift dVI2/dt stability Value of output capacitance Semiconductor Group ∆VQ2/∆T – mV/K – V µF no reset occurs; note 2 – VQ2 CQ2 4.5 10 10 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter ESR of output capacitance Disable Input DIS H-input voltage threshold L-input voltage threshold H-input current L-input current Symbol Limit Values min. typ. – max. 10 Ω at 10 kHz – Unit Test Condition RESRQ2 VDISH VDISL IDISH IDISL 1.8 1.4 –2 –6 2.0 1.7 –1 –2 2.3 2.0 1 – 0.5 V V µA µA – Output 2 active 2.3 V < VDIS < 7 V 0 V < VDIS < 1.4 V Reset Timing D and Output RQ Reset switching threshold Reset adjust threshold Reset output low voltage Reset high voltage VRT VRADJTH VRQL 4.5 1.25 – 4.65 1.35 0.15 4.8 1.45 0.3 V V V RADJ connected to GND VQ1 > 3.5 V RRQ = 10 kΩ external connected to VQ1; VQ1 ≥ 1 V – Internal connected to VQ1 VRQH Reset pull up resistor RRQ Reset charging Id current 4.5 20 3 1.5 0.3 12 – – 30 5 1.8 0.4 15 0.5 – 45 9 2.2 0.55 20 2.0 V kΩ µA V V ms µs VD = 1 V – – Upper timing threshold Lower timing threshold Reset delay time Reset reaction time VDU VDL td tRR CD = 47 nF CD = 47 nF Semiconductor Group 11 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. Sense Input SI and Output SQ Sense threshold voltage Sense threshold hysteresis Sense output low voltage Sense output high voltage typ. max. Unit Test Condition VSITH VSIHY VSQL 1.28 25 – 1.35 60 0.15 1.45 100 0.4 V mV V VSI decreasing – VSQH 4.5 20 – 30 – 45 V kΩ RSQ = 10 kΩ external connected to VQ1 VSI = 1.1 V; VI1 > 4.5 V VSI > 1.5 V Internal connected to VQ1 Sense pull up resistor RSQ Note 1: Measured when the output voltage VQ has dropped 100 mV from the nominal value. Note 2: VQ2 connected to ADJ2 Note 3: Square wave at VI : 8 V to 18 V; f = 10 kHz; tr = tf ≤ 100 ns Semiconductor Group 12 1998-11-01 TLE 4470 Application Information VBatt D1 1N4004 Ι 1 19 10 Q1 5V C Q1 10 µF ZD1 C Ι 36 V 100 nF Reference Stand-by-Regulator 12, 13 Q2 ( R 1= R 2 ) 10 V C Q2 22 µF Ι 2 18 Control DIS 3 V REF R1 11 ADJ2 Main Regulator R SI1 330 k Ω V REF R2 CD 100 nF Ιd 2D 8 RQ 30 k Ω V Q1 1 = V RADJTH Reset RADJ 30 k Ω 9 SQ 4-7 14-17 GND SI 20 C SI R SI2 100 k Ω 10 nF = Sense V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AES02154 Figure 3 Application Circuit Semiconductor Group 13 1998-11-01 TLE 4470 Input, Output The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors CQ1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF & CQ2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (P-DSO-20-6) the output voltage VQ2 of the main regulator can be adjusted to 5 V ≤ VQ2rated ≤ 20 V by connecting an external voltage divider to the voltage adjust pin VA. For VQ2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating VQ or R1 & R2 respectively the following equations can be used: VQ = Vref × (R1 + R2) / R2 or R1 = R × (VQ / Vref) R2 = R × R1 / (R1 – R) Definitions: R = R1 // R2 ; R ≈ 100 kΩ Vref = Output voltage of stand by regulator, typical 5 V Disable The main regulator of the TLE 4470 can be switched OFF by a voltage of 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor Cd which can be calculated as follows: Cd = (∆td × Id) / ∆V Cd = delay capacitor ∆td = delay time Id = charge current, typical 5 µA ∆V = Vdt, typical 1.8 V Vdt = upper delay switching threshold at Cd for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out Definitions: LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for Cd the reaction time can be estimated using the following equation: trr ≈ 20 s/F × Cd Semiconductor Group 14 1998-11-01 TLE 4470 VΙ < t RR V RT VQ dV Ι d = dt C D VDT VST VD td t RR V RO Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED01542 Figure 4 Reset Timing Reset Switching Threshold The internally set reset threshold is 4.65 V. When using the TLE 4470 G (P-DSO-20-6) this threshold can be adjusted to 3.5 V < VRTH < 4.6 V by connecting an external voltage divider to pin RADJ. If this pin is not needed, it can be left open or even better connected to GND. R1 = R2 × (VRT – Vref) / Vref Definitions: (Reset adjust input current ≈ 50 nA) VRT = Reset threshold Vref = comparator reference voltage, typical 1.35 V The reset output pin is internally connected to the stand-by output Q1 via a 30 kΩ pull-up resistor. The reset LOW signal at pin RQ in guaranteed down to an output voltage VQ1 of 1 V typical. Semiconductor Group 15 1998-11-01 TLE 4470 V I1 30 k Ω Band-Gap Reference 1.35 V Band-Gap Reference 1.35 V _