TLE5226G

TLE 5226 G Smart Quad Channel Low-Side Switch Features • Low ON-resistance 2 x 0.2 Ω , 2 x 0.35 Ω (typ.) • Power - SO 20 - Package with integrated cooling area • Overload shutdown • Selective thermal shutdown • Status monitoring • Overvoltage protection • Shorted circuit protection • Standby mode with low current consumption • µC compatible input • Electostatic discharge (ESD) protection Product Summary Supply voltage Drain source voltage On resistance Output current VS VDS(AZ)max RON(typ) 1,2 RON(typ) 3,4 ID 1,2 ID 3,4 4.8 - 32 60 0.2 0.35 2x5 2x3 V V Ω Ω A A Application • All kinds of resistive and inductive loads (relays,electromagnetic valves) • µC compatible power switch for 12 and 24 V applications • Solenoid control switch in automotive and industrial control systems P-DSO-20-10 General description Quad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) with four seperate inputs and four open drain DMOS output stages. The TLE 5226 is fully protected by embedded protection functions and designed for automotive and industrial applications. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND OUT1 ST1 IN4 VS STBY IN3 ST2 OUT2 GND GND OUT3 ST3 IN2 GND ENA IN1 ST4 OUT4 GND Function Ground Power Output channel 1 Status Output channel 1 Control Input channel 4 Supply Voltage Standby Control Input channel 3 Status Output channel 2 Power Output channel 2 Ground Ground Power Output channel 3 Status Output channel 3 Control Input channel 2 Ground Logic Enable Input for all four channels Control Input channel 1 Status Output channel 4 Power Output channel 4 Ground Pin Configuration (Top view) P - DSO - 20 - 10 Semiconductor Group Page 1 1998-02-04 TLE 5226 G Block Diagram VS STBY internal supply ENA Overtemperature Channel 4 Overtemperature Channel 1 Open Load IN1 LOGIC Overload OUT1 RPD ST1 Open Load IN4 Overload LOGIC OUT4 RPD ST4 Overtemperature Channel 3 Overtemperature Channel 2 Open Load IN2 LOGIC Overload OUT2 RPD ST2 Open Load IN3 Overload LOGIC OUT3 RPD ST3 GND Semiconductor Group Page 2 1998-02-04 TLE 5226 G Block Diagram of Open Load Detection Semiconductor Group Page 3 1998-02-04 TLE 5226 G Maximum Ratings for Tj = – 40°C to 150°C Parameter Supply voltage Supply voltage operational range Continuous drain source voltage (OUT1...OUT4) Input voltage IN1 to IN4, ENA Input voltage STBY Status output voltage Operating temperature range Storage temperature range Output current per channel Output current at reversal supply Status output current Inductive load switch off dissipation energy Thermal resistance junction - case junction - ambient @ min. footprint junction - ambient @ 6 cm2 cooling area T j = 25°C Symbol VS Values -0.3 ... + 40 + 4.8 ... + 32 40 - 0.3 ... + 6 - 0.3 ... + 40 - 0.3 ... + 32 - 40 ... + 150 - 55 ... + 150 self limited -4 -2 - 5 ... + 5 50 4.5 50 40 V °C A A mA mJ K/W Unit V V V V VS VDS VIN , VENA VSTBY VST Tj Tstg ID(lim) ID 1,2 ID 3,4 IST EAS RthJC RthJA Test board for 6 cm2 cooling area min. footprint Semiconductor Group Page 4 1998-02-04 TLE 5226 G Electrical Characteristics Parameter and Conditions VS = 4.8 to 18 V ; T j = - 40 °C to + 150 °C (unless otherwise specified) 1. Power Supply (VS) Supply current (Outputs ON) Supply current (Outputs OFF) VENA = L, VSTBY = H Operating voltage Standby current 2. Power Outputs ON state resistance Channel 1,2 ID = 1A; VS ≥ 9.5 V ON state resistance Channel 3,4 ID = 1A; VS ≥ 9.5 V Z-Diode clamping voltage (OUT1...4) Pull down resistor VSTBY = H, VIN = L Output leakage current Output on delay time Output off delay time 2 Output on fall time 2 Output off rise time 2 Output off status delay time 2 Output on status delay time 3 Overload switch-off delay time 3. Digital Inputs (IN1, IN2, IN3, IN4, ENA) Input low voltage Input high voltage Input voltage hysteresis Input pull down current Enable pull down current 3 2 Symbol Values min Unit typ max IS IS VS IS 4.8 8 4 32 10 mA mA V µA VSTBY = L Tj = 25 ° C Tj = 125°C 1 Tj = 25 ° C 1 Tj = 125°C ID ≥ 100 mA RDS(ON) RDS(ON) VDS(AZ) RPD IDlk ton toff tfall trise t4 t5 tDSO 45 14 10 0.2 0.5 0.35 0.75 60 20 26 40 20 10 5 5 10 50 100 65 80 40 40 60 50 300 Ω Ω V kΩ µA µs Tj = 25 °C T j = -40 °C ...150°C VSTBY = L ID = 1 A ID = 1 A ID = 1 A ID = 1 A ID = 1 A VIN = 5 V; VS ≥ 6.5 V VENA = 5 V; VS ≥ 6.5 V VINL VINH VINHys IIN IENA - 0.3 2.0 50 10 10 100 30 20 1.0 6.0 60 40 V V mV µA µA 4. Digital Status Outputs (ST1 - ST4) open Drain Output voltage low Leakage current high IST = 2 mA VSTL ISTH 0.5 10 V µA 1 2 Measured on P-DSO-20 devices See timing diagram, resitive load condition; VS ≥ 9 V 3 This parameter will not be tested but assured by design Semiconductor Group Page 5 1998-02-04 TLE 5226 G Electrical Characteristics Parameter and Conditions VS = 4.8 to 18 V ; T j = – 40 °C to + 150 °C (unless otherwise specified) 5. Standby Input (STBY) Input low voltage Input high voltage Input current 6. Diagnostic Functions Open load detection voltage VENA = X, VIN = L, VDC = 0 4 Open load compare voltage VENA = X, VIN = L, 18V ≥ VDSC ≥ VDS(OL) 4 Open load detection current channel 1,2 VENA = X, VIN = H Open load detection current channel 3,4 VENA = X, VIN = H Overload threshold current channel 1,2 Overload threshold current channel 3,4 Overtemperature shutdown threshold Hysteresis 5 Symbol Values min Unit typ max VSTBY = 18 V VS ≥ 6.5 V VS ≥ 6.5 V VS ≥ 6.5 V VS ≥ 6.5 V VS ≥ 6.5 V VS ≥ 6.5 V VSTBY VSTBY ISTBY 0 3.5 1 VS 300 V V µA VDS(OL) VDS(OL)C ID(OL) 1,2 ID(OL) 3,4 ID(lim) 1,2 ID(lim) 3,4 Tth Thys 0.52*VS VDSC-1.5 0.57*VS VDSC-1.0 V V mA mA A A 160 160 5 3 170 10 7.5 5 480 480 200 °C K Table 1: Channel VDS(OL) 1 VDS(OL) 2 VDS(OL) 3 VDS(OL) 4 Compared with Channel 4 3 2 1 4 VDSC is the output voltage of the corresponding channel, paired for open load detection Corresponding outputs are channel 1 and 4, channel 2 and 3 (see table 1). 5 This parameter will not be tested but assured by design Semiconductor Group Page 6 1998-02-04 TLE 5226 G Application Description This IC is especially designed to drive inductive loads (relays, electromagnetic valves). Integrated clamp-diodes limit the output voltage when inductive loads are discharged. Four open-drain logic outputs indicate the status of the integrated ciruit. The following conditions are monitored and signalled: - overloading of output (also shorted load to supply) in active mode - open and shorted load to ground in active and inactive mode - overtemperature Circuit Description Input Circuits The control and enable inputs, both active high, consist of schmitt triggers with hysteresis. All inputs are connected with pull-down current sources. Not connected inputs are interpreted as LOW. In standby mode (STBY = LOW ) the current consumption is greatly reduced. The circuit is active when STBY = HIGH. If the standby function is not used, it is allowed to connect the standby pin directly to VS. Switching Stages The four power outputs consist of DMOS-power transistors with open drains. The output stages are shorted loads protected throughout the operating range. Integrated clamp-diodes limit voltage overshoots produced when inductive loads are demagnetized. Parallel to the DMOS transistors there are internal pull down resistors. They are provided to detect an open load condition in the off state. They will be disconnected in the standby mode. Protective Circuits The outputs are protected against current overload and overtemperature. There is no protection against reverse polarity of the supply voltage. Error Detection The status outputs indicate the switching state under normal conditions (LOW = off; HIGH = on). If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. The state of the error detection circuits is directly dependent on the input status. If current overload or overtemperature occurs, the error condition is stored into an internal register and the output is shutdown. The reset is done by switching off the corresponding control input. Semiconductor Group Page 7 1998-02-04 TLE 5226 G Open load is detected for all four channels in on and off mode. In the on mode the load current is monitored. If it drops below the specified threshold value, then an open load condition is detected. In the off mode, the ouput voltage is monitored. An open load condition is detected when the output voltage of a given channel is below 55 % of the supply voltage VS. Also the output voltages of two outputs are compaired against each other in off condition with a fixed offset of typ. 1.25 V to recognize GND bypasses. To suppress fault diagnosis during the flyback phase of the compared output, the diagnostic circuit includes a latch function. Reset of this latch is done at end of the flyback phase, additionally it can be reseted by a low signal on the enable input or a high signal of the input line. See block diagramm of open load detection on page 3. Diagnostic Table In general the status follows the input signal in normal operating conditions. If any error is detected the status is inverted. Operating Condition Standby Normal function Standby Input STBY L H H H H H H H H H H H H H H H H Enable Input ENA X L L H H L L H H H H L X H H L X Control Input IN X L H L H L H L H H H H H→L H H H H→L Power Output OUT OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF Status Output ST H L L L H H H H L L L H L L L H L Open load or short to ground Overload or short to supply latched overload reset latch Overtemperature latched overtemperature reset latch Semiconductor Group Page 8 1998-02-04 TLE 5226 G Diagnostic (continued) The following diagrams show the dynamical behaviour of the status output in case of different errors. The symbol F defines the moment of failure occurence. Output open load or short circuit to GND F IN ST F Output overload F IN ST F Overtemperature of the chip F IN ST F Load Bypass F IN ST F Semiconductor Group Page 9 1998-02-04 TLE 5226 G Test Ciruit Semiconductor Group Page 10 1998-02-04 TLE 5226 G Application Circuit The blocking capacitor C is recommended to avoid critical negative voltage spikes on VS in case of battery interruption during OFF-commutation. Semiconductor Group Page 11 1998-02-04 TLE 5226 G Timing Diagrams Output Slope VIN VI NH V INL t VDS VS 85% ton toff 15% t t fall t rise VST t5 t4 t Overload Switch OFF Delay ID ID(lim) ID(OL) t tdso VST t Semiconductor Group Page 12 1998-02-04 TLE 5226 G Package and ordering code all dimensions in mm P - DSO - 20 - 10 Ordering code Q67006-A9207 15.74 +/- 0.1 13.7 -0.2 9 x 1.27 = 11.43 1.27 0.4 +0.13 0.25 M A 20 11 3.2 +/-0.1 1 1 x 45° 10 PIN 1 INDEX MARKING A 15.9 +/-0.15 1.2 -0.3 0.1 1.3 8° 2.8 8° 8° 6.3 8° 11 +/-0.15 1) 14.2 +/-0.3 Semiconductor Group Page 5.9 +/-0.1 13 1998-02-04