S-1003 Series
www.ablic.com
www.ablicinc.com
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
© ABLIC Inc., 2013
The S-1003 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally with an accuracy of 1.0% (VDET 2.2 V). It operates with current consumption of 500 nA typ.
The release signal can be delayed by setting a capacitor externally. Delay time accuracy is 15%.
Moreover, since the S-1003 Series includes the manual reset function, the reset signal can be also output forcibly.
Two output forms Nch open-drain output and CMOS output are available.
Features
Detection voltage:
Detection voltage accuracy:
Current consumption:
Operation voltage range:
Hysteresis width:
Manual reset function:
Delay time accuracy:
Output form:
Operation temperature range:
Lead-free (Sn 100%), halogen-free
1.2 V to 5.0 V (0.1 V step)
1.0% (2.2 V VDET 5.0 V)
22 mV (1.2 V VDET 2.2 V)
500 nA typ.
0.95 V to 10.0 V
5% 2%
MR pin logic active "L", active "H"
15% (CD = 4.7 nF)
Nch open-drain output (Active "L")
CMOS output (Active "L")
Ta = 40°C to 85°C
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance
Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone
Packages
SOT-23-5
SNT-6A
1
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Block Diagrams
1.
Nch open-drain output product (S-1003NAxxI)
Function
VDD
Status
Output logic Active "L"
*1
Delay
circuit
*1
MR pin logic Active "L"
OUT
*1
VREF
*1
MR
circuit
*1
VSS
CD
MR
*1.
Parasitic diode
Figure 1
2.
Nch open-drain output product (S-1003NBxxI)
Function
VDD
Output logic Active "L"
*1
MR pin logic Active "H"
Delay
circuit
*1
OUT
*1
VREF
*1
MR
circuit
*1
VSS
MR
*1.
CD
Parasitic diode
Figure 2
2
Status
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
3.
CMOS output product (S-1003CAxxI)
Function
VDD
Status
Output logic Active "L"
*1
*1
Delay
circuit
*1
MR pin logic Active "L"
OUT
VREF
*1
MR
circuit
*1
*1
VSS
CD
MR
*1.
Parasitic diode
Figure 3
4.
CMOS output product (S-1003CBxxI)
Function
VDD
Status
Output logic Active "L"
*1
*1
Delay
circuit
*1
MR pin logic Active "H"
OUT
VREF
*1
*1
MR
circuit
*1
VSS
MR
*1.
CD
Parasitic diode
Figure 4
3
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Product Name Structure
Users can select the output form, MR pin logic, detection voltage value, and package type for the S-1003 Series. Refer
to "1. Product name" regarding the contents of product name, "2. Product type list" regarding the product types,
"3. Packages" regarding the package drawings and "4. Product name list" regarding details of product name.
1.
Product name
S-1003
x
x
xx
I
-
xxxx
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Operation temperature
I:
Ta = 40C to 85C
Detection voltage value
12 to 50
(e.g., when the detection voltage is 1.2 V, it is expressed as 12.)
MR pin logic*2
A:
Active "L"
B:
Active "H"
Output form*2
N:
Nch open-drain output (Active "L")*3
C:
CMOS output (Active "L")*3
*1.
*2.
*3.
2.
Refer to the tape drawing.
Refer to "2. Product type list".
If you request the product with output logic active "H", contact our sales office.
Product type list
Table 1
Product Type
NA
NB
CA
CB
3.
Output Form
Nch open-drain output
CMOS output
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Packages
Table 2
Package Name
SOT-23-5
SNT-6A
4
MR Pin Logic
Active "L"
Active "H"
Active "L"
Active "H"
Package Drawing Codes
Dimension
Tape
Reel
Land
MP005-A-P-SD
PG006-A-P-SD
MP005-A-C-SD
PG006-A-C-SD
MP005-A-R-SD
PG006-A-R-SD
PG006-A-L-SD
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
4.
Product name list
4. 1
S-1003 Series NA type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "L"
Table 3
Detection Voltage
1.2 V 22 mV
1.3 V 22 mV
1.4 V 22 mV
1.5 V 22 mV
1.6 V 22 mV
1.7 V 22 mV
1.8 V 22 mV
1.9 V 22 mV
2.0 V 22 mV
2.1 V 22 mV
2.2 V 1.0%
2.3 V 1.0%
2.4 V 1.0%
2.5 V 1.0%
2.6 V 1.0%
2.7 V 1.0%
2.8 V 1.0%
2.9 V 1.0%
3.0 V 1.0%
3.1 V 1.0%
3.2 V 1.0%
3.3 V 1.0%
3.4 V 1.0%
3.5 V 1.0%
3.6 V 1.0%
3.7 V 1.0%
3.8 V 1.0%
3.9 V 1.0%
4.0 V 1.0%
4.1 V 1.0%
4.2 V 1.0%
4.3 V 1.0%
4.4 V 1.0%
4.5 V 1.0%
4.6 V 1.0%
4.7 V 1.0%
4.8 V 1.0%
4.9 V 1.0%
5.0 V 1.0%
SOT-23-5
S-1003NA12I-M5T1U
S-1003NA13I-M5T1U
S-1003NA14I-M5T1U
S-1003NA15I-M5T1U
S-1003NA16I-M5T1U
S-1003NA17I-M5T1U
S-1003NA18I-M5T1U
S-1003NA19I-M5T1U
S-1003NA20I-M5T1U
S-1003NA21I-M5T1U
S-1003NA22I-M5T1U
S-1003NA23I-M5T1U
S-1003NA24I-M5T1U
S-1003NA25I-M5T1U
S-1003NA26I-M5T1U
S-1003NA27I-M5T1U
S-1003NA28I-M5T1U
S-1003NA29I-M5T1U
S-1003NA30I-M5T1U
S-1003NA31I-M5T1U
S-1003NA32I-M5T1U
S-1003NA33I-M5T1U
S-1003NA34I-M5T1U
S-1003NA35I-M5T1U
S-1003NA36I-M5T1U
S-1003NA37I-M5T1U
S-1003NA38I-M5T1U
S-1003NA39I-M5T1U
S-1003NA40I-M5T1U
S-1003NA41I-M5T1U
S-1003NA42I-M5T1U
S-1003NA43I-M5T1U
S-1003NA44I-M5T1U
S-1003NA45I-M5T1U
S-1003NA46I-M5T1U
S-1003NA47I-M5T1U
S-1003NA48I-M5T1U
S-1003NA49I-M5T1U
S-1003NA50I-M5T1U
SNT-6A
S-1003NA12I-I6T1U
S-1003NA13I-I6T1U
S-1003NA14I-I6T1U
S-1003NA15I-I6T1U
S-1003NA16I-I6T1U
S-1003NA17I-I6T1U
S-1003NA18I-I6T1U
S-1003NA19I-I6T1U
S-1003NA20I-I6T1U
S-1003NA21I-I6T1U
S-1003NA22I-I6T1U
S-1003NA23I-I6T1U
S-1003NA24I-I6T1U
S-1003NA25I-I6T1U
S-1003NA26I-I6T1U
S-1003NA27I-I6T1U
S-1003NA28I-I6T1U
S-1003NA29I-I6T1U
S-1003NA30I-I6T1U
S-1003NA31I-I6T1U
S-1003NA32I-I6T1U
S-1003NA33I-I6T1U
S-1003NA34I-I6T1U
S-1003NA35I-I6T1U
S-1003NA36I-I6T1U
S-1003NA37I-I6T1U
S-1003NA38I-I6T1U
S-1003NA39I-I6T1U
S-1003NA40I-I6T1U
S-1003NA41I-I6T1U
S-1003NA42I-I6T1U
S-1003NA43I-I6T1U
S-1003NA44I-I6T1U
S-1003NA45I-I6T1U
S-1003NA46I-I6T1U
S-1003NA47I-I6T1U
S-1003NA48I-I6T1U
S-1003NA49I-I6T1U
S-1003NA50I-I6T1U
5
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
4. 2
S-1003 Series NB type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "H"
Table 4
Detection Voltage
1.2 V 22 mV
1.3 V 22 mV
1.4 V 22 mV
1.5 V 22 mV
1.6 V 22 mV
1.7 V 22 mV
1.8 V 22 mV
1.9 V 22 mV
2.0 V 22 mV
2.1 V 22 mV
2.2 V 1.0%
2.3 V 1.0%
2.4 V 1.0%
2.5 V 1.0%
2.6 V 1.0%
2.7 V 1.0%
2.8 V 1.0%
2.9 V 1.0%
3.0 V 1.0%
3.1 V 1.0%
3.2 V 1.0%
3.3 V 1.0%
3.4 V 1.0%
3.5 V 1.0%
3.6 V 1.0%
3.7 V 1.0%
3.8 V 1.0%
3.9 V 1.0%
4.0 V 1.0%
4.1 V 1.0%
4.2 V 1.0%
4.3 V 1.0%
4.4 V 1.0%
4.5 V 1.0%
4.6 V 1.0%
4.7 V 1.0%
4.8 V 1.0%
4.9 V 1.0%
5.0 V 1.0%
6
SOT-23-5
S-1003NB12I-M5T1U
S-1003NB13I-M5T1U
S-1003NB14I-M5T1U
S-1003NB15I-M5T1U
S-1003NB16I-M5T1U
S-1003NB17I-M5T1U
S-1003NB18I-M5T1U
S-1003NB19I-M5T1U
S-1003NB20I-M5T1U
S-1003NB21I-M5T1U
S-1003NB22I-M5T1U
S-1003NB23I-M5T1U
S-1003NB24I-M5T1U
S-1003NB25I-M5T1U
S-1003NB26I-M5T1U
S-1003NB27I-M5T1U
S-1003NB28I-M5T1U
S-1003NB29I-M5T1U
S-1003NB30I-M5T1U
S-1003NB31I-M5T1U
S-1003NB32I-M5T1U
S-1003NB33I-M5T1U
S-1003NB34I-M5T1U
S-1003NB35I-M5T1U
S-1003NB36I-M5T1U
S-1003NB37I-M5T1U
S-1003NB38I-M5T1U
S-1003NB39I-M5T1U
S-1003NB40I-M5T1U
S-1003NB41I-M5T1U
S-1003NB42I-M5T1U
S-1003NB43I-M5T1U
S-1003NB44I-M5T1U
S-1003NB45I-M5T1U
S-1003NB46I-M5T1U
S-1003NB47I-M5T1U
S-1003NB48I-M5T1U
S-1003NB49I-M5T1U
S-1003NB50I-M5T1U
SNT-6A
S-1003NB12I-I6T1U
S-1003NB13I-I6T1U
S-1003NB14I-I6T1U
S-1003NB15I-I6T1U
S-1003NB16I-I6T1U
S-1003NB17I-I6T1U
S-1003NB18I-I6T1U
S-1003NB19I-I6T1U
S-1003NB20I-I6T1U
S-1003NB21I-I6T1U
S-1003NB22I-I6T1U
S-1003NB23I-I6T1U
S-1003NB24I-I6T1U
S-1003NB25I-I6T1U
S-1003NB26I-I6T1U
S-1003NB27I-I6T1U
S-1003NB28I-I6T1U
S-1003NB29I-I6T1U
S-1003NB30I-I6T1U
S-1003NB31I-I6T1U
S-1003NB32I-I6T1U
S-1003NB33I-I6T1U
S-1003NB34I-I6T1U
S-1003NB35I-I6T1U
S-1003NB36I-I6T1U
S-1003NB37I-I6T1U
S-1003NB38I-I6T1U
S-1003NB39I-I6T1U
S-1003NB40I-I6T1U
S-1003NB41I-I6T1U
S-1003NB42I-I6T1U
S-1003NB43I-I6T1U
S-1003NB44I-I6T1U
S-1003NB45I-I6T1U
S-1003NB46I-I6T1U
S-1003NB47I-I6T1U
S-1003NB48I-I6T1U
S-1003NB49I-I6T1U
S-1003NB50I-I6T1U
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
4. 3
S-1003 Series CA type
Output form: CMOS output (Active "L")
MR pin logic: Active "L"
Table 5
Detection Voltage
1.2 V 22 mV
1.3 V 22 mV
1.4 V 22 mV
1.5 V 22 mV
1.6 V 22 mV
1.7 V 22 mV
1.8 V 22 mV
1.9 V 22 mV
2.0 V 22 mV
2.1 V 22 mV
2.2 V 1.0%
2.3 V 1.0%
2.4 V 1.0%
2.5 V 1.0%
2.6 V 1.0%
2.7 V 1.0%
2.8 V 1.0%
2.9 V 1.0%
3.0 V 1.0%
3.1 V 1.0%
3.2 V 1.0%
3.3 V 1.0%
3.4 V 1.0%
3.5 V 1.0%
3.6 V 1.0%
3.7 V 1.0%
3.8 V 1.0%
3.9 V 1.0%
4.0 V 1.0%
4.1 V 1.0%
4.2 V 1.0%
4.3 V 1.0%
4.4 V 1.0%
4.5 V 1.0%
4.6 V 1.0%
4.7 V 1.0%
4.8 V 1.0%
4.9 V 1.0%
5.0 V 1.0%
SOT-23-5
S-1003CA12I-M5T1U
S-1003CA13I-M5T1U
S-1003CA14I-M5T1U
S-1003CA15I-M5T1U
S-1003CA16I-M5T1U
S-1003CA17I-M5T1U
S-1003CA18I-M5T1U
S-1003CA19I-M5T1U
S-1003CA20I-M5T1U
S-1003CA21I-M5T1U
S-1003CA22I-M5T1U
S-1003CA23I-M5T1U
S-1003CA24I-M5T1U
S-1003CA25I-M5T1U
S-1003CA26I-M5T1U
S-1003CA27I-M5T1U
S-1003CA28I-M5T1U
S-1003CA29I-M5T1U
S-1003CA30I-M5T1U
S-1003CA31I-M5T1U
S-1003CA32I-M5T1U
S-1003CA33I-M5T1U
S-1003CA34I-M5T1U
S-1003CA35I-M5T1U
S-1003CA36I-M5T1U
S-1003CA37I-M5T1U
S-1003CA38I-M5T1U
S-1003CA39I-M5T1U
S-1003CA40I-M5T1U
S-1003CA41I-M5T1U
S-1003CA42I-M5T1U
S-1003CA43I-M5T1U
S-1003CA44I-M5T1U
S-1003CA45I-M5T1U
S-1003CA46I-M5T1U
S-1003CA47I-M5T1U
S-1003CA48I-M5T1U
S-1003CA49I-M5T1U
S-1003CA50I-M5T1U
SNT-6A
S-1003CA12I-I6T1U
S-1003CA13I-I6T1U
S-1003CA14I-I6T1U
S-1003CA15I-I6T1U
S-1003CA16I-I6T1U
S-1003CA17I-I6T1U
S-1003CA18I-I6T1U
S-1003CA19I-I6T1U
S-1003CA20I-I6T1U
S-1003CA21I-I6T1U
S-1003CA22I-I6T1U
S-1003CA23I-I6T1U
S-1003CA24I-I6T1U
S-1003CA25I-I6T1U
S-1003CA26I-I6T1U
S-1003CA27I-I6T1U
S-1003CA28I-I6T1U
S-1003CA29I-I6T1U
S-1003CA30I-I6T1U
S-1003CA31I-I6T1U
S-1003CA32I-I6T1U
S-1003CA33I-I6T1U
S-1003CA34I-I6T1U
S-1003CA35I-I6T1U
S-1003CA36I-I6T1U
S-1003CA37I-I6T1U
S-1003CA38I-I6T1U
S-1003CA39I-I6T1U
S-1003CA40I-I6T1U
S-1003CA41I-I6T1U
S-1003CA42I-I6T1U
S-1003CA43I-I6T1U
S-1003CA44I-I6T1U
S-1003CA45I-I6T1U
S-1003CA46I-I6T1U
S-1003CA47I-I6T1U
S-1003CA48I-I6T1U
S-1003CA49I-I6T1U
S-1003CA50I-I6T1U
7
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
4. 4
S-1003 Series CB type
Output form: CMOS output (Active "L")
MR pin logic: Active "H"
Table 6
Detection Voltage
1.2 V 22 mV
1.3 V 22 mV
1.4 V 22 mV
1.5 V 22 mV
1.6 V 22 mV
1.7 V 22 mV
1.8 V 22 mV
1.9 V 22 mV
2.0 V 22 mV
2.1 V 22 mV
2.2 V 1.0%
2.3 V 1.0%
2.4 V 1.0%
2.5 V 1.0%
2.6 V 1.0%
2.7 V 1.0%
2.8 V 1.0%
2.9 V 1.0%
3.0 V 1.0%
3.1 V 1.0%
3.2 V 1.0%
3.3 V 1.0%
3.4 V 1.0%
3.5 V 1.0%
3.6 V 1.0%
3.7 V 1.0%
3.8 V 1.0%
3.9 V 1.0%
4.0 V 1.0%
4.1 V 1.0%
4.2 V 1.0%
4.3 V 1.0%
4.4 V 1.0%
4.5 V 1.0%
4.6 V 1.0%
4.7 V 1.0%
4.8 V 1.0%
4.9 V 1.0%
5.0 V 1.0%
8
SOT-23-5
S-1003CB12I-M5T1U
S-1003CB13I-M5T1U
S-1003CB14I-M5T1U
S-1003CB15I-M5T1U
S-1003CB16I-M5T1U
S-1003CB17I-M5T1U
S-1003CB18I-M5T1U
S-1003CB19I-M5T1U
S-1003CB20I-M5T1U
S-1003CB21I-M5T1U
S-1003CB22I-M5T1U
S-1003CB23I-M5T1U
S-1003CB24I-M5T1U
S-1003CB25I-M5T1U
S-1003CB26I-M5T1U
S-1003CB27I-M5T1U
S-1003CB28I-M5T1U
S-1003CB29I-M5T1U
S-1003CB30I-M5T1U
S-1003CB31I-M5T1U
S-1003CB32I-M5T1U
S-1003CB33I-M5T1U
S-1003CB34I-M5T1U
S-1003CB35I-M5T1U
S-1003CB36I-M5T1U
S-1003CB37I-M5T1U
S-1003CB38I-M5T1U
S-1003CB39I-M5T1U
S-1003CB40I-M5T1U
S-1003CB41I-M5T1U
S-1003CB42I-M5T1U
S-1003CB43I-M5T1U
S-1003CB44I-M5T1U
S-1003CB45I-M5T1U
S-1003CB46I-M5T1U
S-1003CB47I-M5T1U
S-1003CB48I-M5T1U
S-1003CB49I-M5T1U
S-1003CB50I-M5T1U
SNT-6A
S-1003CB12I-I6T1U
S-1003CB13I-I6T1U
S-1003CB14I-I6T1U
S-1003CB15I-I6T1U
S-1003CB16I-I6T1U
S-1003CB17I-I6T1U
S-1003CB18I-I6T1U
S-1003CB19I-I6T1U
S-1003CB20I-I6T1U
S-1003CB21I-I6T1U
S-1003CB22I-I6T1U
S-1003CB23I-I6T1U
S-1003CB24I-I6T1U
S-1003CB25I-I6T1U
S-1003CB26I-I6T1U
S-1003CB27I-I6T1U
S-1003CB28I-I6T1U
S-1003CB29I-I6T1U
S-1003CB30I-I6T1U
S-1003CB31I-I6T1U
S-1003CB32I-I6T1U
S-1003CB33I-I6T1U
S-1003CB34I-I6T1U
S-1003CB35I-I6T1U
S-1003CB36I-I6T1U
S-1003CB37I-I6T1U
S-1003CB38I-I6T1U
S-1003CB39I-I6T1U
S-1003CB40I-I6T1U
S-1003CB41I-I6T1U
S-1003CB42I-I6T1U
S-1003CB43I-I6T1U
S-1003CB44I-I6T1U
S-1003CB45I-I6T1U
S-1003CB46I-I6T1U
S-1003CB47I-I6T1U
S-1003CB48I-I6T1U
S-1003CB49I-I6T1U
S-1003CB50I-I6T1U
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Pin Configurations
1.
SOT-23-5
Table 7
Top view
5
Pin No.
4
1
2
3
4
5
1 2 3
Symbol
CD
VSS
MR
OUT
VDD
Description
Connection pin for delay capacitor
GND pin
Manual reset pin
Voltage detection output pin
Voltage input pin
Figure 5
2.
SNT-6A
Table 8
Top view
1
2
3
Pin No.
6
5
4
Figure 6
*1.
Symbol
Description
1
CD
Connection pin for delay capacitor
2
VDD
Voltage input pin
3
OUT
Voltage detection output pin
4
MR
Manual reset pin
NC*1
5
No connection
6
VSS
GND pin
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
9
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Absolute Maximum Ratings
Table 9
(Ta = 25°C unless otherwise specified)
Item
Symbol
Power supply voltage
VDDVSS
CD pin input voltage
VCD
MR pin input voltage
VMR
Nch open-drain output product
Output voltage
VOUT
CMOS output product
Output current
IOUT
SOT-23-5
Power dissipation
PD
SNT-6A
Operation ambient temperature
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Name:
JEDEC STANDARD51-7
Caution
Absolute Maximum Rating
Unit
12.0
VSS0.3 to VDD 0.3
VSS0.3 to VDD 0.3
VSS0.3 to 12.0
VSS0.3 to VDD 0.3
50
*1
600
400*1
40 to 85
40 to 125
V
V
V
V
V
mA
mW
mW
°C
°C
The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (PD) [mW]
700
600
500
300
10
SNT-6A
200
100
0
Figure 7
SOT-23-5
400
0
150
100
50
Ambient Temperature (Ta) [C]
Power Dissipation of Package (When Mounted on Board)
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Electrical Characteristics
1.
Nch open-drain output product
Table 10
Item
Symbol
Condition
1.2 V VDET 2.2 V
Detection voltage*1
VDET
2.2 V VDET 5.0 V
Hysteresis width
VHYS
Current consumption
Operation voltage
ISS
VDD
VDD = VDET(S) 1.0 V
IOUT
Output transistor
Nch
VDS*2 = 0.5 V
MR pin active
Output current
Leakage current
ILEAK
Delay time*3
Detection voltage
temperature
coefficient*4
tD
MR pin
input voltage "H"
MR pin
input voltage "L"
VDD = 0.95 V
VDD = 1.2 V
VDD = 2.4 V
VDD = 4.8 V
Output transistor
Nch
VDD = 10.0 V, VOUT = 10.0 V
MR pin non-active
CD = 4.7 nF
VDET
Ta = 40°C to 85°C
Ta VDET
VMRH
VMRL
NA type
(MR pin logic active "L")
NB type
(MR pin logic active "H")
NA type
(MR pin logic active "L")
NB type
(MR pin logic active "H")
(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
VDET(S)
VDET(S)
V
1
VDET(S)
0.022
0.022
VDET(S)
VDET(S)
VDET(S)
V
1
0.99
1.01
VDET
VDET
VDET
V
1
0.03
0.05
0.07
0.50
0.90
A
2
0.95
10.0
V
1
0.59
1.00
mA
3
0.73
1.33
mA
3
1.47
2.39
mA
3
1.86
2.50
mA
3
0.08
A
3
8.5
10.0
11.5
ms
4
100
350
ppm/°C
1
VDD
0.3
V
6
1.2
V
6
VDD
1.2
V
6
0.3
V
6
MR pin
RMR
0.5
1.0
1.6
M
6
input resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3 or Table 4.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V VDET(S)1.0 V is applied to the VDD pin to when VOUT
reaches VDD 0.9, after the output pin is pulled up to VDD by the resistance of 100 k
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
VDET
[mV/°C]*1 = VDET(S) (typ.)[V]*2 Ta V
[ppm/°C]*3 1000
Ta
DET
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
11
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2.
CMOS output product
Table 11
Item
Symbol
Condition
1.2 V VDET 2.2 V
Detection voltage*1
VDET
2.2 V VDET 5.0 V
Hysteresis width
VHYS
Current consumption
Operation voltage
ISS
VDD
Output current
IOUT
VDD = VDET(S) 1.0 V
VDD = 0.95 V
Output transistor
VDD = 1.2 V
Nch
*2
VDS = 0.5 V
VDD = 2.4 V
MR pin active
VDD = 4.8 V
VDD = 4.8 V
Output transistor
S-1003Cx12
to 43
Pch
VDS*2 = 0.5 V
*3
Delay time
Detection voltage
temperature
coefficient*4
MR pin
input voltage "H"
MR pin
input voltage "L"
tD
VDD = 6.0 V
CD = 4.7 nF
VDET
Ta = 40°C to 85°C
Ta VDET
VMRH
VMRL
CA type
(MR pin logic active "L")
CB type
(MR pin logic active "H")
CA type
(MR pin logic active "L")
CB type
(MR pin logic active "H")
(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
VDET(S)
VDET(S)
V
1
VDET(S)
0.022
0.022
VDET(S)
VDET(S)
VDET(S)
V
1
0.99
1.01
VDET
VDET
VDET
V
1
0.03
0.05
0.07
0.50
0.90
A
2
0.95
10.0
V
1
0.59
1.00
mA
3
0.73
1.33
mA
3
1.47
2.39
mA
3
1.86
2.50
mA
3
1.62
2.60
mA
5
1.78
2.86
mA
5
8.5
10.0
11.5
ms
4
100
350
ppm/°C
1
VDD
0.3
V
6
1.2
V
6
VDD
1.2
V
6
0.3
V
6
MR pin
RMR
0.5
1.0
1.6
M
6
input resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V VDET(S)1.0 V is applied to the VDD pin to when VOUT
reaches VDD 0.9.
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
VDET
[mV/°C]*1 = VDET(S) (typ.)[V]*2 Ta V
[ppm/°C]*3 1000
Ta
DET
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
12
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Test Circuits
VDD
MR
*2
*1.
*2.
R*1
100 k
VDD
V
VSS
CD
VDD
VDD
OUT
V
MR
OUT
VSS
CD
*1
R is unnecessary for CMOS output product.
Set to VDD or GND (MR pin non-active).
Figure 8
A
*1.
Set to VDD or GND (MR pin non-active).
Test Circuit 1
Figure 9
Test Circuit 2
Oscilloscope
VDD
VDD
VDD
V
*1
*1
MR
OUT
VSS
CD
A
VDS
P.G.
*2
V
MR
OUT
VSS
CD
R
100 k
VOUT
CD
*1.
Set to VDD or GND.
Figure 10
*1.
*2.
R is unnecessary for CMOS output product.
Set to VDD or GND (MR pin non-active).
Test Circuit 3
Figure 11
Test Circuit 4
VDS
V
VDD
MR
V
*1
*1.
*1
VDD
VSS
OUT
A
A
VMR
MR
OUT
VSS
CD
V
Set to VDD or GND (MR pin non-active).
Figure 12
VDD
VDD
CD
R
100 k
Test Circuit 5
*1.
V
R is unnecessary for CMOS output product.
Figure 13
Test Circuit 6
13
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Timing Charts
1.
Nch open-drain output product
VDD
Release voltage (VDET)
Hysteresis width
(VHYS)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
R
100 k
VDD
VDD
*1
MR OUT
VSS CD
V
Output from OUT pin
VSS
*1.
tD
Set to VDD or GND (MR pin non-active).
Figure 14
2.
CMOS output product
VDD
Release voltage (VDET)
Hysteresis width
(VHYS)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
VDD
*1
VDD
MR OUT
VSS CD
V
Output from OUT pin
VSS
*1.
Set to VDD or GND (MR pin non-active).
tD
Remark
When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 15
14
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Operation
1.
Basic operation: CMOS output (active "L") product
(1)
(2)
(3)
(4)
(5)
When the power supply voltage (VDD) is the release voltage (VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 16 is OFF, the comparator
(RB RC ) VDD
input voltage is
.
RA RB RC
Although VDD decreases to VDET or less, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or less (point A in Figure 17), the Nch transistor is ON and the Pch transistor
is OFF so that VSS ("L") is output. At this time, the Nch transistor N1 in Figure 16 is turned on, and the input
RB VDD
voltage to the comparator is
.
RA RB
The output is indefinite by decreasing VDD to the IC's minimum operation voltage or less. If the output is
pulled up, it will be VDD.
VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds VDET and
VDD is less than VDET, the output is VSS.
When increasing VDD to VDET or more (point B in Figure 17), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
*1
Pch
*1
RA
Delay
circuit
*1
OUT
*1
RB
Nch
VREF
*1
RC
MR
circuit
*1
N1
VSS
MR
*1.
CD
CD
Parasitic diode
Figure 16
(1)
(2)
(3)
Operation 1
(4)
B
A
Hysteresis width
(VHYS)
(5)
VDD
Release voltage (VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
Remark
tD
When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 17 Operation 2
15
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2.
Manual reset function
The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (VMR).
When not using the manual reset function, set VMR = VDD in the S-1003 Series xA type, and VMR = VSS in the
S-1003 Series xB type.
Caution
Perform thorough evaluation in the actual application when using the MR pin in open. Due to the
parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply
fluctuates.
2. 1
S-1003 Series xA type (MR pin logic active "L")
(1) MR pin = "L"
When the VDD pin voltage is the release voltage (VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the
MR pin.
(2) MR pin = "H"
If a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
(1)
(2)
Input from VDD pin
VDD (VDET)
Input from MR pin
MR pin input voltage "H" (VMRH)
MR pin input voltage "L" (VMRL)
VDD
Output from OUT pin
VSS
tD
Figure 18
Remark
Timing Chart of MR Pin Logic Active "L"
Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in
the floating status depending on the VDD pin voltage (Refer to Figure 19).
*1
VDD
RMR
MR
*1
VSS
*1.
Parasitic diode
Figure 19
16
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2. 2
S-1003 Series xB type (MR pin logic active "H")
(1) MR pin = "H"
When the VDD pin voltage is the release voltage (VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the
MR pin.
(2) MR pin = "L"
If a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
(2)
(1)
Input from VDD pin
VDD (VDET)
Input from MR pin
MR pin input voltage "H" (VMRH)
MR pin input voltage "L" (VMRL)
VDD
Output from OUT pin
VSS
tD
Figure 20
Remark
Timing Chart of MR Pin Logic Active "H"
Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or
"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).
*1
VDD
MR
RMR
*1
VSS
*1.
Parasitic diode
Figure 21
17
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2. 3
Cautions of manual reset function
2. 3. 1
Slew rate when switching manual reset function
Although there is a hysteresis width between the MR pin input voltage "L" (VMRL) and the MR pin input voltage "H"
(VMRH), note that the IC may malfunction if the slew rate (Refer to Figure 22, Figure 23) is low when the MR pin
voltage is changed.
The slew rate is calculated by using the following equation.
Slew rate =
VMRH VMRL
t
(1) When MR pin logic is active "L"
The OUT pin voltage may oscillate if the parasitic resistance (RP) between the power supply and the VDD pin is
high.
・In case of RP 8 k
Connect a capacitor of 1 nF or more between the VDD pin and the VSS pin.
・In case of 5 k RP 8 kCapacitors are unnecessary if the slew rate is 100 V/s or higher.
・In case of RP 5 k
Capacitors are unnecessary if the slew rate is 1 V/s or higher.
VMR
VMRH
VMRL
Time
t
Figure 22
(2) When MR pin logic is active "H"
Connect a capacitor of 100 pF or more to the CD pin, and set the slew rate 20 V/s or higher.
VMR
VMRH
VMRL
Time
t
Figure 23
18
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2. 4
When connecting resistance (RA) between power supply voltage (VDD) and VDD pin
When the MR pin voltage (VMR) is an intermediate voltage (especially VMRLVMRVMRH), the current consumption
increases by 25 A max. A voltage drop occurs since this current flows through RA. If the VDD pin voltage (VIN)
becomes the detection voltage (VDET) or less for that reason, the OUT pin changes to the detection status, and the
detection status or the release status are not controlled by VMR. The OUT pin may not be able to change to the
release status unless VDD is raised (Refer to Figure 24).
(1) When MR pin logic is active "L"
In case of VIN VMR, a current also flows through the MR pin input resistance (RMR). For example, when VIN =
10 V, VMR = 1 V, RMR = 0.5 M (min.), a current of 18 A flows from the VDD pin to the MR pin. Therefore, set
RA so as to satisfy the following equation.
RA (VDD (VDET)) / (25 AMR pin current)
(2) When MR pin logic is active "H"
Set RA so as to satisfy the following equation.
RA (VDD (VDET)) / 25 A
VDD
RA
VIN
VDD
OUT
MR
VSS
CD
VMR
(Nch open-drain output product)
GND
Figure 24
19
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
3.
Delay circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (VDD)
exceeds the release voltage (VDET) when VDD is turned on. The output signal is not delayed when VDD decreases
to the detection voltage (VDET) or less (refer to "Figure 17 Operation 2").
The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached delay capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following
equation. When the CD value is sufficiently large, the tD0 value can be disregarded.
tD [ms] = Delay coefficient CD [nF] tD0 [ms]
Table 12
Delay Coefficient
Delay Coefficient
Operation
Temperature
Min.
1.60
1.78
2.01
Ta = 85°C
Ta = 25°C
Ta = 40°C
Table 13
Operation Temperature
Ta = 40°C to 85°C
Caution 1.
Typ.
1.89
2.05
2.31
Max.
2.13
2.30
2.71
Delay Time
Min.
0.021 ms
Delay Time (tD0)
Typ.
0.044 ms
Max.
0.147 ms
When the CD pin is open, a double pulse shown in Figure 25 may appear at release.
To avoid the double pulse, attach a 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
VOUT
Time
Figure 25
2.
3.
20
Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value. Leakage current causes deviation in
delay time. When the leakage current is larger than the built-in constant current, no release
takes place.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
4.
Other characteristics
4. 1
Temperature characteristics of detection voltage
The shaded area in Figure 26 shows the temperature characteristics of detection voltage in the operation
temperature range.
VDET [V]
0.945 mV/°C
VDET25
*1
0.945 mV/°C
40
*1.
Figure 26
4. 2
25
85
Ta [°C]
VDET25 is an actual detection voltage value at Ta = 25°C.
Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
Temperature characteristics of release voltage
The temperature change
VDET
of the release voltage is calculated by using the temperature change
Ta
VDET
of the detection voltage as follows:
Ta
VDET
VDET
VDET
=
Ta
VDET
Ta
The temperature change of the release voltage and the detection voltage has the same sign consequently.
4. 3
Temperature characteristics of hysteresis voltage
The temperature change of the hysteresis voltage is expressed as
VDET
VDET
and is calculated as
Ta
Ta
follows:
VDET
VDET
VHYS
VDET
=
Ta
Ta
VDET
Ta
21
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Standard Circuit
R*1
100 k
VDD
MR
VSS
OUT
CD
CD
*1.
*2.
*2
R is unnecessary for CMOS output product.
The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 27
Caution
22
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Explanation of Terms
1.
Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 30 turns to "L". The detection voltage varies slightly
among products of the same specification. The variation of detection voltage between the specified minimum
(VDET min.) and the maximum (VDET max.) is called the detection voltage range (Refer to Figure 28).
Example:
2.
In the S-1003Cx15, the detection voltage is either one in the range of 1.478 V VDET 1.522 V.
This means that some S-1003Cx15 have VDET = 1.478 V and some have VDET = 1.522 V.
Release voltage (VDET)
The release voltage is a voltage at which the output in Figure 30 turns to "H". The release voltage varies slightly
among products of the same specification. The variation of release voltage between the specified minimum (VDET
min.) and the maximum (VDET max.) is called the release voltage range (Refer to Figure 29). The range is
calculated from the actual detection voltage (VDET) of a product and is in the range of VDET 1.03 VDET VDET
1.07.
Example:
For the S-1003Cx15, the release voltage is either one in the range of 1.522 V VDET 1.629 V.
This means that some S-1003Cx15 have VDET = 1.522 V and some have VDET = 1.629 V.
VDD
VDD
Release voltage
Detection voltage
VDET max.
VDET max.
Detection voltage
range
VDET min.
Release voltage
range
VDET min.
OUT
OUT
tD
Figure 28
Detection Voltage
VDD
Figure 29
R*1
100 k
VDD
V
MR
*2
VSS
Release Voltage
OUT
CD
V
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 30
Test Circuit of Detection Voltage and Release Voltage
23
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
3.
Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 17 Operation 2"). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4.
Delay time (tD)
The delay time in the S-1003 Series is a period from the input voltage to the VDD pin exceeding the release voltage
(VDET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (CD).
VDD
VDET
OUT
tD
Figure 31
5.
Delay Time
Feed-through current
Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage
detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.
6.
Oscillation
In applications where a resistor is connected to the voltage detector input (Figure 32), taking a CMOS active "L"
product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)
causes a voltage drop equal to [feed-through current] [input resistance] across the resistor. When the input
voltage drops below the detection voltage (VDET) as a result, the output voltage goes to "L". In this status, the
feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The
feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces
oscillation.
VDD
RA
VIN
VDD
OUT
MR
VSS CD
RB
(CMOS output product)
GND
Figure 32
24
Example for Bad Implementation Due to Detection Voltage Change
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1003 Series, the feed-through current flows at the detection and the release. If the
input impedance is high, oscillation may occur due to the voltage drop by the feed-through current when releasing.
In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power
supply voltage (VDD) is slow near the detection voltage.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
As seen in Figure 33, when connecting an input resistance (RA) in Nch open-drain output product of the S-1003
Series, RA should be 100 k or less to prevent oscillation. Moreover, note that the hysteresis width may be larger
as the following equation.
Maximum hysteresis width = VHYSRA 20 A
When using the manual reset function, refer to "2. 4 When connecting resistance (RA) between power supply
voltage (VDD) and VDD pin" in " Operation" to set the constant.
VDD
RA
(RA 100 k)
VIN
Set to VIN or GND (MR pin non-active)
VDD
OUT
MR
VSS CD
(Nch open-drain output product)
GND
Figure 33
Caution
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
25
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Characteristics (Typical Data)
1.
Detection voltage (VDET) vs. Temperature (Ta)
S-1003CA12
1.40
S-1003CA24
2.60
1.20
−VDET
1.10
1.00
+VDET
2.50
+VDET
VDET [V]
VDET [V]
1.30
2.40
−VDET
2.30
−40 −25
2.20
0
25
Ta [C]
50
75 85
50
75 85
−40 −25
0
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
S-1003CA50
5.40
+VDET
VDET [V]
5.20
5.00
−VDET
4.80
4.60
2.
−40 −25
0
25
Ta [C]
Hysteresis width (VHYS) vs. Temperature (Ta)
S-1003CA12
7
S-1003CA24
7
6
VHYS [%]
VHYS [%]
6
5
4
3
−40 −25
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
VHYS [%]
6
5
4
26
−40 −25
4
3
0
S-1003CA50
7
3
5
−40 −25
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
3.
Current consumption (ISS) vs. Input voltage (VDD)
Ta = 25°C
1.25
1.25
1.00
1.00
0.75
0.50
Ta = 25°C
S-1003CA24
1.50
ISS [μA]
ISS [μA]
S-1003CA12
1.50
0.25
0.75
0.50
0.25
0
0
0
2
4
6
VDD [V]
8
10
0
2
4
6
VDD [V]
8
10
Ta = 25°C
S-1003CA50
1.50
ISS [μA]
1.25
1.00
0.75
0.50
0.25
0
0
4.
2
4
6
VDD [V]
8
10
Current consumption (ISS) vs. Temperature (Ta)
VDD = VDET(S) 1.0 V
S-1003NA12
1.00
0.75
ISS [μA]
ISS [μA]
0.75
0.50
0.25
0
VDD = VDET(S) 1.0 V
S-1003NA24
1.00
0.50
0.25
−40 −25
0
0
25
Ta [C]
50
75 85
−40 −25
0
25
Ta [C]
50
75 85
VDD = VDET(S) 1.0 V
S-1003NA50
1.00
ISS [μA]
0.75
0.50
0.25
0
−40 −25
0
25
Ta [C]
50
75 85
27
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
IOUT [mA]
S-1003NA12
Ta = 25°C, MR pin active
20.0
VDD = 6.00 V
17.5
15.0
VDD = 4.80 V
12.5
VDD = 3.60 V
10.0
7.5
VDD = 2.40 V
5.0
VDD = 1.20 V
2.5
VDD = 0.95 V
0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0
VDS [V]
7.
Nch transistor output current (IOUT) vs.
Input voltage (VDD)
IOUT [mA]
S-1003NA12
VDS = 0.5 V, MR pin active
4.0
Ta = −40°C
3.0
2.0
Ta = +85°C
1.0
Ta = +25°C
Pch transistor output current (IOUT) vs. VDS
Ta = 25°C
S-1003CA12
40.0
VDD = 8.4 V
30.0
VDD = 7.2 V
VDD = 6.0 V
VDD = 4.8 V
VDD = 3.6 V
VDD = 2.4 V
20.0
10.0
0
0
8.
2.0
S-1003CA12
5.0
2.0
4.0
6.0
VDD [V]
8.0
10.0
Remark VDS: Drain-to-source voltage of the output transistor
8.0
10.0
VDS = 0.5 V
Ta = −40°C
4.0
3.0
2.0
Ta = +25°C
Ta = +85°C
0
0
4.0
6.0
VDS [V]
Pch transistor output current (IOUT) vs.
Input voltage (VDD)
1.0
0
28
6.
IOUT [mA]
Nch transistor output current (IOUT) vs. VDS
IOUT [mA]
5.
0
2.0
4.0
6.0
VDD [V]
8.0
10.0
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Minimum operation voltage (VOUT) vs. Input voltage (VDD)
VOUT [V]
S-1003NA12
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Pull-up to VDD
Pull-up resistance: 100 k
S-1003NA24
Pull-up to VDD
Pull-up resistance: 100 k
3.0
2.5
Ta = −40°C
Ta = +25°C
VOUT [V]
9.
S-1003NA50
1.5
Ta = −40°C
Ta = +25°C
Ta = +85°C
1.0
0.5
Ta = +85°C
0
2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD [V]
0
0.4
0.8
1.2 1.6
VDD [V]
2.0
2.4
2.8
Pull-up to VDD
Pull-up resistance: 100 k
6.0
VOUT [V]
5.0
4.0
3.0
Ta = −40°C
2.0
Ta = +25°C
Ta = +85°C
1.0
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
S-1003NA12
Pull-up to 10 V
Pull-up resistance: 100 k
S-1003NA24
12.0
12.0
Ta = −40°C
8.0
Ta = +25°C
Ta = +85°C
6.0
4.0
2.0
10.0
VOUT [V]
10.0
VOUT [V]
Pull-up to 10 V
Pull-up resistance: 100 k
Ta = −40°C
8.0
Ta = +25°C
Ta = +85°C
6.0
4.0
2.0
0
0
0
S-1003NA50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD [V]
0
0.4
0.8
1.2 1.6
VDD [V]
2.0
2.4
2.8
Pull-up to 10 V
Pull-up resistance: 100 k
12.0
VOUT [V]
10.0
8.0
6.0
4.0
Ta = −40°C
Ta = +25°C
Ta = +85°C
2.0
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]
29
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
10. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)
S-1003CA24
1
0.1
tPLH
0.01
tPHL
0.001
0.00001
Response time [ms]
Response time [ms]
S-1003CA12
1
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
0.1
tPLH
0.01
tPHL
0.001
0.00001
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
Response time [ms]
S-1003CA50
1
0.1
0.01
0.001
0.00001
tPLH
tPHL
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
S-1003NA24
100
Response time [ms]
Response time [ms]
S-1003NA12
100
10
1
tPLH
0.1
0.01
0.001
0.00001
tPHL
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
Response time [ms]
S-1003NA50
100
30
10
1
tPLH
0.1
0.01
0.001
0.00001
tPHL
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
10
1
tPLH
0.1
0.01
0.001
0.00001
tPHL
0.001
0.01
0.0001
Output pin capacitance [μF]
0.1
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
1 s
1 s
VIH*1
Input voltage
R
VDD
VIL*2
tPHL
VDD
MR
OUT
V
VSS CD
tPLH
*3
VDD 90%
*3
VDD
*2
*1
100 k
COUT
Output voltage
V
VDD1
*1
*3
VDD 10%
R and VDD1 are unnecessary for CMOS output
product.
*2. Set to VDD or GND (MR pin non-active).
*1.
*1.
*2.
*3.
VIH = 10 V
VIL = 0.95 V
CMOS output product: VDD
Nch open-drain product: VDD1
Figure 34
Caution
Test Condition of Response Time
Figure 35
Test Circuit of Response Time
1.
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. When the CD pin is open, a double pulse may appear at release.
To avoid the double pulse, attach a 100 pF or more capacitor to the CD pin.
Response time when detecting (tPHL) is not affected by CD pin capacitance. Besides, response
time when releasing (tPLH) can set the delay time by attaching the CD pin.
Refer to "11. Delay time (tD) vs. CD pin capacitance (CD) (Without output pin capacitance)" for
details.
11. Delay time (tD) vs. CD pin capacitance (CD) (Without output pin capacitance)
Ta = 25°C
1000
1000
100
100
10
1
0.1
0.01
0.01
Ta = 25°C
S-1003NA24
10000
tD [ms]
tD [ms]
S-1003NA12
10000
10
1
0.1
0.1
1
10
CD [nF]
100
1000
0.01
0.01
0.1
1
10
CD [nF]
100
1000
Ta = 25°C
S-1003NA50
10000
tD [ms]
1000
100
10
1
0.1
0.01
0.01
0.1
1
10
CD [nF]
100
1000
31
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
12. Delay time (tD) vs. Temperature (Ta)
S-1003NA24
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
12
12
11
11
tD [ms]
tD [ms]
S-1003NA12
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
10
9
8
10
9
−40 −25
8
0
25
Ta [C]
50
75 85
−40 −25
0
25
Ta [C]
50
75 85
S-1003NA50
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
12
tD [ms]
11
10
9
8
−40 −25
0
25
Ta [C]
50
75 85
1 s
VIH
*1
R*1
VDD
Input voltage
VIL*2
tD
VDD
MR
V
VSS
OUT
CD
*2
CD
VDD 90%
100 k
V
Output voltage
VSS
*1.
*2.
VIH = VDET(S)1.0 V
VIL = 0.95 V
Figure 36
Caution
32
Test Condition for Delay Time
*1.
*2.
R is unnecessary for CMOS output product.
Set to VDD or GND (MR pin non-active).
Figure 37
Test Circuit for Delay Time
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
Application Circuit Examples
1.
Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the guaranteed operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1003 Series which has the low operation voltage, a high accuracy detection voltage and hysteresis,
reset circuits can be easily constructed as seen in Figure 38 and Figure 39.
VDD
VDD1
VDD
VDD
VDD
*1
MR OUT
VSS CD
MR
*1
Microcomputer
GND
*1.
Set to VDD or GND (MR pin non-active).
Figure 38 Example of Reset Circuit
(CMOS Output Product)
Caution
OUT
Microcomputer
VSS CD
GND
*1.
Set to VDD or GND (MR pin non-active).
Figure 39 Example of Reset Circuit
(Nch Open-drain Output Product)
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
33
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03
S-1003 Series
2.
Change of detection voltage (Nch open-drain output product only)
If there is not a product with a specified detection voltage value in the S-1003N Series, the detection voltage can be
changed by using a resistance divider or a diode, as seen in Figure 40 and Figure 41.
In Figure 40, hysteresis width also changes.
VDD
VDD
RA
Vf1
R
*1
100 k
(RA 100 k) VIN
VDD
R
100 k
VIN
VDD
OUT
MR
VSS CD
OUT
MR
VSS CD
RB
RA RB
VDET
RB
RA RB
VHYS
Hysteresis width =
RB
Detection voltage =
Detection voltage = Vf1 (VDET)
*1.
Set to VIN or GND (MR pin non-active).
RA should be 100 k or less to prevent oscillation.
Set to VIN or GND (MR pin non-active).
Caution
If RA and RB are large, the hysteresis width
may also be larger than the value given by
the above equation due to the feed-through
current.
Figure 40
Caution
1.
2.
3.
Figure 41
The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Note that the hysteresis width may be larger as the following equation shows when using the
above connections. Perform thorough evaluation using the actual application to set the
constant.
Maximum hysteresis width =
34
(Nch open-drain
output product)
GND
GND
*1.
*2.
*1
(Nch open-drain
output product)
*2
R A RB
VHYSRA 20 A
RB
When using the manual reset function, refer to "2. 4 When connecting resistance (RA)
between power supply voltage (VDD) and VDD pin" in " Operation" to set the constant.
2.9±0.2
1.9±0.2
4
5
1
2
+0.1
0.16 -0.06
3
0.95±0.1
0.4±0.1
No. MP005-A-P-SD-1.3
TITLE
SOT235-A-PKG Dimensions
No.
MP005-A-P-SD-1.3
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
ø1.5 -0
+0.2
ø1.0 -0
2.0±0.05
0.25±0.1
4.0±0.1
1.4±0.2
3.2±0.2
3 2 1
4
5
Feed direction
No. MP005-A-C-SD-2.1
TITLE
SOT235-A-Carrier Tape
No.
MP005-A-C-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP005-A-R-SD-1.1
SOT235-A-Reel
TITLE
No.
MP005-A-R-SD-1.1
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
3,000
1.57±0.03
6
1
5
4
2
3
+0.05
0.08 -0.02
0.5
0.48±0.02
0.2±0.05
No. PG006-A-P-SD-2.1
TITLE
SNT-6A-A-PKG Dimensions
No.
PG006-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
1.85±0.05
ø0.5 -0
4.0±0.1
0.65±0.05
3 2 1
4
5 6
Feed direction
No. PG006-A-C-SD-2.0
TITLE
SNT-6A-A-Carrier Tape
No.
PG006-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PG006-A-R-SD-1.0
SNT-6A-A-Reel
TITLE
No.
PG006-A-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
5,000
0.52
1.36
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
No. PG006-A-L-SD-4.1
TITLE
SNT-6A-A
-Land Recommendation
No.
PG006-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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