S-24C02D/04D/08D/16D
www.ablic.com
www.ablicinc.com
2-WIRE SERIAL E2PROM
© ABLIC Inc., 2012
Rev.3.0_02_U
This IC is a 2-wire, low current consumption and wide range operation serial E2PROM. This IC has the capacity of 2 K-bit,
4 K-bit, 8-K bit and 16 K-bit, and the organization is 256 words 8-bit, 512 words 8-bit, 1024 words 8-bit and 2048 words
8-bit, respectively. Page write and sequential read are available.
Caution
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is
indispensable.
Features
Operation voltage range
Read:
1.7 V to 5.5 V
Write:
1.7 V to 5.5 V
Operation frequency:
1.0 MHz max. (VCC = 2.5 V to 5.5 V)
400 kHz max. (VCC = 1.7 V to 5.5 V)
Write time:
5.0 ms max.
Page write
S-24C02D:
8 bytes / page
S-24C04D: 16 bytes / page
S-24C08D: 16 bytes / page
S-24C16D: 16 bytes / page
Sequential read
Noise suppression:
Schmitt trigger and noise filter on input pins (SCL, SDA)
Write protect function during low power supply voltage
Endurance:
106 cycle / word*1 (Ta = 25C)
Data retention: 100 years (Ta = 25C)
Memory capacity
S-24C02D:
2 K-bit
S-24C04D:
4 K-bit
S-24C08D:
8 K-bit
S-24C16D: 16 K-bit
Write protect:
100%
Initial delivery state:
FFh
Operation temperature range:
Ta = 40°C to 85°C
Lead-free (Sn 100%), halogen-free
*1.
For each address (Word: 8-bit)
Packages
8-Pin SOP (JEDEC)
SOT-23-5
5
4
8
4
5
3
1
1
(5.0 6.0 t1.75 mm)
(2.8 2.9 t1.3 mm)
8-Pin TSSOP
DFN-8(2030)
8
5
5
8
1
4
1
4
(3.0 6.4 t1.1 mm)
(3.0 2.0 t0.5 mm)
TMSOP-8
SNT-8A
8
5
4
5
8
4
1
1
(2.9 4.0 t0.8 mm)
(2.5 2.0 t0.5 mm)
1
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D/16D
Rev.3.0_02_U
Block Diagram
VCC
WP
SCL
GND
Start / Stop
Detector
SDA
Voltage Detector
Serial Clock
Controller
High-Voltage Generator
LOAD
Device Address
Comparator
COMP
Data Register
LOAD INC
A0*1
R/W
A1*2
A2*3
Address
Counter
X Decoder
Memory Cell Array
Y Decoder
Data Output
ACK Output
Controller
DIN
DOUT
*1.
*2.
*3.
This pin is not available for the S-24C04D/08D/16D.
This pin is not available for the S-24C08D/16D.
This pin is not available for the S-24C16D.
Remark
2
Selector
The A0 pin, the A1 pin and the A2 pin are no connection in the product with SOT-23-5 package.
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D/16D
Rev.3.0_02_U
Product Name Structure
1.
Product name
S-24CxxD
I
-
xxxx
U
5
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
K8T3: TMSOP-8, Tape
M5T1: SOT-23-5, Tape
A8T1: DFN-8(2030), Tape
I8T1: SNT-8A, Tape
Operation temperature
I:
Ta = 40°C to 85°C
Product name
S-24C02D: 2 K-bit
S-24C04D: 4 K-bit
S-24C08D: 8 K-bit
S-24C16D: 16 K-bit
*1.
2.
Refer to the tape drawing.
Packages
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SOT-23-5
DFN-8(2030)
SNT-8A
Dimension
FJ008-Z-P-SD
FT008-Z-P-SD
FM008-A-P-SD
MP005-A-P-SD
PP008-A-P-S1
PH008-A-P-SD
Tape
FJ008-Z-C-SD
FT008-Z-C-SD
FM008-A-C-SD
MP005-B-C-SD
PP008-A-C-SD
PH008-A-C-SD
Reel
FJ008-Z-R-SD
FT008-Z-R-SD
FM008-A-R-SD
MP005-B-R-SD
PP008-A-R-SD
PH008-A-R-SD
Land
PP008-A-L-SD
PH008-A-L-SD
3
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D/16D
3.
Product name list
Product Name
S-24C02DI-J8T1U5
S-24C02DI-T8T1U5
S-24C02DI-K8T3U5
S-24C02DI-M5T1U5
S-24C02DI-A8T1U5
S-24C02DI-I8T1U5
S-24C04DI-J8T1U5
S-24C04DI-T8T1U5
S-24C04DI-K8T3U5
S-24C04DI-M5T1U5
S-24C04DI-A8T1U5
S-24C04DI-I8T1U5
S-24C08DI-J8T1U5
S-24C08DI-T8T1U5
S-24C08DI-K8T3U5
S-24C08DI-M5T1U5
S-24C08DI-A8T1U5
S-24C08DI-I8T1U5
S-24C16DI-J8T1U5
S-24C16DI-T8T1U5
S-24C16DI-K8T3U5
S-24C16DI-M5T1U5
S-24C16DI-A8T1U5
S-24C16DI-I8T1U5
4
Rev.3.0_02_U
Capacity
2 K-bit
2 K-bit
2 K-bit
2 K-bit
2 K-bit
2 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
8 K-bit
8 K-bit
8 K-bit
8 K-bit
8 K-bit
8 K-bit
16 K-bit
16 K-bit
16 K-bit
16 K-bit
16 K-bit
16 K-bit
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SOT-23-5
DFN-8(2030)
SNT-8A
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SOT-23-5
DFN-8(2030)
SNT-8A
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SOT-23-5
DFN-8(2030)
SNT-8A
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SOT-23-5
DFN-8(2030)
SNT-8A
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D/16D
Rev.3.0_02_U
Pin Configurations
1.
8-Pin SOP (JEDEC), 8-Pin TSSOP, TMSOP-8, DFN-8(2030), SNT-8A
Top view
1
8
2
7
3
6
4
5
2.
Symbol
S-24C04D S-24C08D
NC*2
NC*2
NC*2
A1
A2
A2
GND
GND
SDA*1
SDA*1
*1
SCL
SCL*1
S-24C16D
NC*2
NC*2
NC*2
GND
SDA*1
SCL*1
7
WP
WP
WP
WP
8
VCC
VCC
VCC
VCC
Description
Slave address input
Slave address input
Slave address input
Ground
Serial data I/O
Serial clock input
Write protect input
Connected to VCC:
Protection valid
Open or connected to GND:
Protection invalid
Power supply
SOT-23-5
Top view
5
4
1 2 3
*1.
*2.
1
2
3
4
5
6
S-24C02D
A0
A1
A2
GND
SDA*1
SCL*1
Pin No.
Pin No.
Symbol
*1
1
2
3
4
SCL
GND
SDA*1
VCC
5
WP
Description
Serial clock input
Ground
Serial data I/O
Power supply
Write protect input
Connected to VCC:
Open or connected to GND:
Protection valid
Protection invalid
Do not use it in "High-Z".
The NC is no connection.
Remark For DFN-8(2030) package, connect the heatsink of back side to the board, and set electric potential open or GND.
However, do not use it as the function of electrode.
5
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
Absolute Maximum Ratings
Table 1
Item
Power supply voltage
Input voltage
Output voltage
Operation ambient temperature
Storage temperature
Symbol
VCC
VIN
VOUT
Topr
Tstg
Absolute Maximum Rating
0.3 to 6.5
0.3 to 6.5
0.3 to 6.5
40 to 85
65 to 150
Unit
V
V
V
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 2
Item
Symbol
Power supply voltage
VCC
High level input voltage
Low level input voltage
VIH
VIL
Condition
Read
Write
VCC = 1.7 V to 5.5 V
VCC = 1.7 V to 5.5 V
Ta = 40°C to 85°C
Min.
Max.
Unit
1.7
1.7
5.5
5.5
0.7 VCC
0.3
5.5
0.3 VCC
V
V
V
V
Pin Capacitance
Table 3
Item
Symbol
Input capacitance
CIN
I/O capacitance
CI/O
Condition
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
VIN = 0 V (S-24C02D: SCL, A0, A1, A2, WP)
VIN = 0 V (S-24C04D: SCL, A1, A2, WP)
VIN = 0 V (S-24C08D: SCL, A2, WP)
VIN = 0 V (S-24C16D: SCL, WP)
VI/O = 0 V (SDA)
8
8
8
8
8
pF
pF
pF
pF
pF
Endurance
Table 4
Item
Symbol
Operation Ambient Temperature
Endurance
NW
Ta = 25°C
*1. For each address (Word: 8-bit)
Min.
106
Max.
Unit
cycle / word*1
Min.
100
Max.
Unit
year
Data Retention
Table 5
Item
Data retention
6
Symbol
Operation Ambient Temperature
Ta = 25°C
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
DC Electrical Characteristics
Table 6
Item
Current consumption
(READ)
Symbol
Ta = 40°C to 85°C
VCC = 2.5 V to 5.5 V
VCC = 1.7 V to 5.5 V
fSCL = 1.0 MHz
fSCL = 400 kHz
Min.
Max.
Min.
Max.
Condition
ICC1
1.0
0.8
Unit
mA
Table 7
Item
Current consumption
(WRITE)
Symbol
Ta = 40°C to 85°C
VCC = 2.5 V to 5.5 V
VCC = 1.7 V to 5.5 V
fSCL = 1.0 MHz
fSCL = 400 kHz
Min.
Max.
Min.
Max.
Condition
ICC2
2.0
2.0
Unit
mA
Table 8
Ta = 40°C to 85°C
Item
Symbol
Standby current
consumption
ISB
Input leakage current 1
ILI1
Input leakage current 2
ILI2
Output leakage current
ILO
Input current 1
IIL
Input current 2
IIH
Input Impedance 1
ZIL
Input Impedance 2
ZIH
Low level output voltage
VOL
Condition
VIN = VCC or GND
SCL, SDA
VIN = GND to VCC
A0, A1, A2
VIN > 0.7 VCC
SDA
VOUT = GND to VCC
WP
VIN < 0.3 VCC
WP
VIN > 0.7 VCC
WP
VIN = 0.3 VCC
WP
VIN = 0.7 VCC
IOL = 3.2 mA
IOL = 1.5 mA
IOL = 0.7 mA
VCC = 2.5 V to 5.5 V
VCC = 1.7 V to 2.5 V
Unit
Min.
Max.
Min.
Max.
1.0
1.0
A
1.0
1.0
A
1.0
1.0
A
1.0
1.0
A
50.0
50.0
A
2.0
2.0
A
30
30
k
500
500
k
0.4
0.3
0.2
0.3
0.2
V
V
V
7
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
AC Electrical Characteristics
Table 9 Measurement Conditions
Input pulse voltage
Input pulse rising / falling time
Output reference voltage
Output load
Input pulse voltage
0.2 VCC to 0.8 VCC
20 ns or less
0.3 VCC to 0.7 VCC
100 pF
Output reference voltage
0.8 VCC
0.7 VCC
0.3 VCC
0.2 VCC
Figure 1 Input / Output Waveform during AC Measurement
Table 10
Item
SCL clock frequency
SCL clock time "L"
SCL clock time "H"
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rising time
SCL, SDA falling time
WP setup time
WP hold time
WP release setup time
WP release hold time
Bus release time
Noise suppression time
Write time
8
Symbol
fSCL
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tWS1
tWH1
tWS2
tWH2
tBUF
tI
tWR
Ta = 40°C to 85°C
VCC = 2.5 V to 5.5 V
VCC = 1.7 V to 5.5 V
Min.
Max.
Min.
Max.
0
1000
0
400
0.4
1.3
0.3
0.6
0.1
0.5
0.1
0.9
50
50
0.25
0.6
0.25
0.6
80
100
0
0
0.25
0.6
0.3
0.3
0.3
0.3
0
0
0
0
0
0
0
0
0.5
1.3
50
50
5.0
5.0
Unit
kHz
s
s
s
ns
s
s
ns
ns
s
s
s
s
s
s
s
s
ns
ms
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
tHIGH
tF
tLOW
tR
SCL
tHD.STA
tHD.DAT
tSU.STA
tSU.DAT
tSU.STO
SDA
input
tAA
tDH
tBUF
SDA
output
Figure 2 Bus Timing
Start Condition
Acknowledge
Write Data
Stop Condition
tWR
Start Condition
SCL
D0
SDA
tWS1
tWH1
tWS2
tWH2
WP
(valid)
WP
(invalid)
Figure 3 Write Cycle Timing
9
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
Pin Functions
1. VCC (Power supply) pin
The VCC pin is used to apply positive supply voltage. Regarding the applied voltage value, refer to "
Recommended Operating Conditions". Set a bypass capacitor of about 0.1 F between the VCC pin and the GND
pin to make the power supply voltage stable.
2. A0, A1 and A2 (Slave address input) pins
In the S-24C02D, to set the slave address, connect each of A0 pin, A1 pin and A2 pin to the GND pin or the VCC pin.
Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins.
In the S-24C04D, to set the slave address, connect each of A1 pin and A2 pin to the GND pin or the VCC pin.
Therefore the users can set 4 types of slave address by a combination of A1, A2 pins.
In the S-24C08D, to set the slave address, connect A2 pin to the GND pin or the VCC pin. Therefore the users can
set 2 types of slave address.
In the S-24C16D, the slave address can not be assigned.
Comparing the slave address transmitted from the master device and one that you set, makes possible to select one
slave address from other devices connected onto the bus.
Each of A0 pin, A1 pin and A2 pin has a built-in pull-down resistor. In open, the pin is set to the same status as it
connected to the GND pin.
In the case of the products with SOT-23-5, set the slave address transmitting from the master device to "0".
3. SDA (Serial data I/O) pin
The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch opendrain output pin.
In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with
Wired-OR connection by pulling up to VCC by a resistor. Figure 4 shows the relation with an output load.
4. SCL (Serial clock input) pin
The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL
clock, pay attention to the rising and falling time and comply with the specification.
5. WP (Write protect input) pin
The write protect is enabled by connecting the WP pin to VCC. When not using the write protect, connect this pin to
the GND pin or set in open.
Maximum value of pull-up resistor
[k]
20
18
16
14
12
10
8
6
4
2
0
fSCL= 400 kHz
fSCL= 1000 kHz
10
100
Value of load capacity
[pF]
Figure 4 Output Load
10
200
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
Initial Delivery State
Initial delivery state of all addresses is "FFh".
Operation
1. Initialization operation after power-on
By a power-on-clear circuit, this IC initializes the internal circuit at the time of power-on. Perform the beginning (start
condition) of the instruction transmission to this IC after the initialization by the power-on-clear circuit. Regarding the
datails of power-on-clear, refer to "5. Power-on-clear circuit" in " Usage".
2. Start condition
Start is identified by a "H" to "L" transition of the SDA line while the SCL line is stable at "H".
Every operation begins from a start condition.
3. Stop condition
Stop is identified by a "L" to "H" transition of the SDA line while the SCL line is stable at "H".
When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device
enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is halted, and this IC
initiates a write cycle.
tINIT
VCC
tSU.STA
tHD.STA
tSU.STO
SCL
SDA
Start condition
Stop condition
Figure 5 Start / Stop Conditions after Power-on
11
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
4. Data transmission
Changing the SDA line while the SCL line is "L", data is transmitted.
Changing the SDA line while the SCL line is "H", a start or stop condition is recognized.
tSU.DAT
tHD.DAT
SCL
SDA
Figure 6 Data Transmission Timing
5. Acknowledge
The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA
line to acknowledge the receipt of the 8-bit data.
When an internal write cycle is in progress, the device does not generate an acknowledge.
SCL
(E2PROM input)
1
8
9
SDA
(Master output)
Acknowledge
output
SDA
(E PROM output)
2
Start condition
tAA
Figure 7 Acknowledge Output Timing
12
tDH
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
6. Device addressing
To start communication, the master device on the system generates a start condition to the bus line. Next, the master
device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The higher 4 bits of the device address are the "Device Code", and are fixed to "1010".
In the S-24C02D, successive 3 bits are the "Slave Address". These 3 bits are used to identify a device on the system
bus and are compared with the predetermined value which is defined by the address input pins (A2, A1, A0). When
the comparison result matches, the slave device responds with an acknowledge during the 9th clock cycle.
In the S-24C04D, successive 2 bits are the "Slave Address". These 2 bits are used to identify a device on the system
bus and are compared with the predetermined value which is defined by the address input pins (A2, A1). When the
comparison result matches, the slave device responds with an acknowledge during the 9th clock cycle.
The successive 1 bit (P0) is used to define a page address and choose the two 256-byte memory blocks (Address
000h to 0FFh, 100h to 1FFh).
In the S-24C08D, successive 1 bit is called the "Slave Addrdess". This 1 bit is used to identify a device on the system
bus and is compared with the predetermined value which is defined by the address input pin (A2). When the
comparison result matches, the slave device responds with an acknowledge during the 9th clocks cycle.
The successive 2 bits (P1, P0) are used to define a page address and choose the four 256-byte memory blocks
(Address 000h to 0FFh, 100h to 1FFh, 200h to 2FFh , 300h to 3FFh).
In the S-24C16D, successive 3 bits (P2, P1, P0) are "Page Address". Choose the 8 memory blocks of 256-byte
(Adress 000h to 0FFh, 100h to 1FFh, 200h to 2FFh, 300h to 3FFh, 400h to 4FFh, 500h to 5FFh, 600h to 6FFh, 700h
to 7FFh).
In the case of the product with SOT-23-5, set the slave address transmitting from the master device to "0".
Slave / Page
Address
Device Code
S-24C02D
1
0
1
0
A2
A1
A0
R/W
S-24C04D
1
0
1
0
A2
A1
P0
R/W
S-24C08D
1
0
1
0
A2
P1
P0
R/W
S-24C16D
1
0
1
0
P2
P1
P0
R/W
MSB
LSB
Figure 8 Device Address
13
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
7. Write
7. 1 Byte write
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start
condition, this IC acknowledges it.
This IC then receives an 8-bit word address and responds with an acknowledge. After this IC receives 8-bit write
data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the
addressed memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
M
S
B
W
R
I
T
E
0 1 0 A2 A1 A0 0
WORD ADDRESS
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
Remark A0 is P0 in the S-24C04D/08D/16D.
A1 is P1 in the S-24C08D/16D.
A2 is P2 in the S-24C16D.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 9 Byte Write
14
A
A
C
C
K
K
S
T
O
P
A
C
K
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
7. 2 Page write
The page write mode allows up to 8 bytes to be written in a single write operation in the S-24C02D.
The page write mode allows up to 16 bytes to be written in a single write operation in the S-24C04D/08D/16D.
Its basic process to transmit data is as same as byte write, but it operates page write by sequentially receiving
8-bit write data as much data as the page size has.
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start
condition, it generates an acknowledge. Then this IC receives an 8-bit word address, and responds with an
acknowledge. After this IC receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data
corresponding to the next word address, and generates an acknowledge. This IC repeats reception of 8-bit write
data and generation of acknowledge in succession. This IC can receive as many write data as the maximum page
size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and
having the page size equal to the received write data.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
WORD ADDRESS (n)
DATA (n)
1 0 1 0 A2 A1 A0 0
W7W6 W5W4 W3 W2 W1W0
D7 D6 D5 D4 D3 D2 D1 D0
DEVICE
ADDRESS
M
S
B
L R A
S / C
BWK
A
C
K
DATA (n 1)
D7
A
C
K
S
T
O
P
DATA (n x)
D0
D7
A
C
K
D0
A
C
K
Remark A0 is P0 in the S-24C04D/08D/16D.
A1 is P1 in the S-24C08D/16D.
A2 is P2 in the S-24C16D.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 10 Page Write
In the S-24C02D, the lower 3 bits of the word address are automatically incremented every time when the
S-24C02D receives 8-bit write data. If the size of the write data exceeds 8 bytes, the higher 5 bits (W7 to W3) of
the word address remain unchanged, and the lower 3 bits are rolled over and the last 8-byte data that the
S-24C02D received will be overwritten.
In the S-24C04D, the lower 4 bits of the word address are automatically incremented every time when the
S-24C04D receives 8-bit write data. If the size of the write data exceeds 16 bytes, the higher 4 bits (W7 to W4) of
the word address and page address (P0) remain unchanged, and the lower 4 bits are rolled over and the last 16byte data that the S-24C04D received will be overwritten.
In the S-24C08D, the lower 4 bits of the word address are automatically incremented every time when the
S-24C08D receives 8-bit write data. If the size of the write data exceeds 16 bytes, the higher 4 bits (W7 to W4) of
the word address and page address (P1, P0) remain unchanged, and the lower 4 bits are rolled over and the last
16-byte data that the S-24C08D received will be overwritten.
In the S-24C16D, the lower 4 bits of the word address are automatically incremented every time when the
S-24C16D receives 8-bit write data. If the size of the write data exceeds 16 bytes, the higher 4 bits (W7 to W4) of
the word address and page address (P2, P1, P0) remain unchanged, and the lower 4 bits are rolled over and the
last 16-byte data that the S-24C16D received will be overwritten.
15
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
7. 3 Write protect
Write protect is available in this IC. When the WP pin is connected to the VCC pin, write operation to memory area
is forbidden at all.
When the WP pin is connected to the GND pin or set in open, the write protect is invalid, and write operation in all
memory area is available.
Fix the level of the WP pin from start condition in the write operation (byte write, page write) until stop condition. If
the WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding the
timing of write protect, refer to "Figure 3 Write Cycle Timing".
When not using the write protect, connect the WP pin to the GND pin or set in open. The write protect is valid in
the range of operation power supply voltage.
As seen in Figure 11 when the write protect is valid, this IC does not generate an acknowledgel after data input.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
M
S
B
W
R
I
T
E
0 1 0 A2 A1 A0 0
WORD ADDRESS
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
A
A
C
C
K
K
WP
Remark A0 is P0 in the S-24C04D/08D/16D.
A1 is P1 in the S-24C08D/16D.
A2 is P2 in the S-24C16D.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 11 Write Protect
16
S
T
O
P
N
A
C
K
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
7. 4 Acknowledge polling
Acknowledge polling is used to know the completion of the write cycle in this IC.
After this IC receives a stop condition and once starts the write cycle, all operations are forbidden and no
response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in this IC by detecting a response
from the slave device after transmitting the start condition, the device address and the read / write instruction
code to this IC, namely to the slave devices.
That is, if this IC does not generate an acknowledge, the write cycle is in progress and if this IC generates an
acknowledge, the write cycle has been completed.
It is recommended to use the read instruction "1" as the read / write instruction code transmitted by the master
device.
Acknowledge polling during read
DATA
SDA
LINE
S
T
O
P
S
T
A
R
T
R
E
A
D
S
T
A
R
T
DEVICE
ADDRESS 1
DEVICE
ADDRESS 1
D2 D1 D0
NO ACK from
R Master Device
E
A
D
R N
/ A
W C
K
S
T
O
P
S
T
A
R
T
DEVICE
ADDRESS
DATA
R A
/ C
WK
R A
/ C
WK
tWR
Acknowledge polling during write
DATA
SDA
LINE
D2 D1 D0
S
T
O
P
W
R
I
T
E
S
T
A
R
T
DEVICE
ADDRESS 0
R N
/ A
W C
K
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS 0
WORD
ADDRESS
R A
/ C
WK
A
C
K
tWR
Remark
Users are able to read data after acknowledge output in acknowledge polling during read.
Users are able to input word address and data after acknowledge output in acknowledge polling during write.
However, after that users input the write instruction, a start condition may not be input during data output. Input a
stop condition and the next instruction after data output and acknowledge output.
Figure 12 Usage Example of Acknowledge Polling
17
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
8. Read
8. 1 Current address read
Either in writing or in reading this IC holds the last accessed memory address. The memory address is maintained
when the instruction transmission is not interrupted, and the memory address is maintained as long as the power
voltage does not decrease less than the operating voltage.
The master device can read the data at the memory address of the current address pointer without assigning the
word address as a result, when it recognizes the position of the address pointer in this IC. This is called "Current
Address Read".
In the following the address counter in this IC is assumed to be "n".
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition, it responds with an acknowledge.
Next an 8-bit data at the address "n" is sent from this IC synchronous to the SCL clock. The address counter is
incremented and the content of the address counter becomes n 1. The master device outputs stop condition not
an acknowledge, the reading of this IC is ended.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
M
S
B
0
1
NO ACK from
Master Device
R
E
A
D
S
T
O
P
DATA
0 A2 A1 A0 1
L R
S /
B W
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
Remark In the S-24C04D/08D/16D, A0 = Don't care.
In the S-24C08D/16D, A1 = Don't care.
In the S-24C16D, A2 = Don't care.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 13 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in this IC.
In Read, the memory address counter in this IC is automatically incremented after output of the 8th bit of the data.
In Write, on the other hand, the higher bits of the memory address (the higher bits of the word address and the
page address*1) are left unchanged and are not incremented.
18
1. In the S-24C02D, the higher 5 bits (W7 to W3) of the word address.
In the S-24C04D, the higher 4 bits (W7 to W4) of the word address and the page address (P0).
In the S-24C08D, the higher 4 bits (W7 to W4) of the word address and the page address (P1, P0).
In the S-24C16D, the higher 4bits (W7 to W4) of the word address and the page address (P2, P1, P0).
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
8. 2 Random read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "0" following a start
condition, it responds with an acknowledge.
This IC then receives an 8-bit word address and responds with an acknowledge. The memory address is loaded
to the address counter in this IC by these operations. Reception of write data does not follow in a dummy write
whereas reception of write data follows in byte write and in page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device can
read the data starting from the arbitrary memory address by transmitting a new start condition and performing the
same operation in the current address read.
That is, when this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1", following a
start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from this IC in synchronous
to the SCL clock. The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
S-24C02D
SDA
LINE
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
S
T
A
R
T
WORD ADDRESS (n)
DEVICE
ADDRESS
R
E
A
D
NO ACK from
Master Device
S
T
O
P
DATA
1 0 1 0 A2 A1 A0 0
W7 W6 W5 W4 W3 W2 W1 W0
1 0 1 0 A2 A1 A0 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 A2 A1 P0 0
W7 W6 W5 W4 W3 W2 W1 W0
1 0 1 0 A2 A1 X 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 A2 P1 P0 0
W7 W6 W5 W4 W3 W2 W1 W0
1 0 1 0 A2 X X 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 P2 P1 P0 0
W7 W6 W5 W4 W3 W2 W1 W0
1 0 1 0 X X X 1
D7 D6 D5 D4 D3 D2 D1 D0
S-24C04D
SDA
LINE
S-24C08D
SDA
LINE
S-24C16D
SDA
LINE
M
S
B
L R A
S / C
B W K
A
C
K
M
S
B
L R A
S / C
B W K
DUMMY WRITE
Remark 1. X = Don't care
2. Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 14 Random Read
19
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
8. 3 Sequential read
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition both in current address read and random read, it responds with an acknowledge.
When an 8-bit data is output from this IC synchronous to the SCL clock, the address counter is automatically
incremented.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in this IC incremented and
makes it possible to read data in succession. This is called sequential read.
The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first word address.
NO ACK from
Master Device
R
E
DEVICE A
ADDRESS D
SDA
LINE
1
R A
/ C
W K
A
C
K
D7
D0
DATA (n)
A
C
K
D7
D0
DATA (n 1)
D7
D0
DATA (n 2)
Figure 15 Sequential Read
20
S
T
O
P
A
C
K
D7
D0
DATA (n x)
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
Usage
1. A pull-up resistor to SDA I/O pin and SCL input pin
In consideration of I2C-bus protocol function, the SDA I/O pin should be connected with a pull-up resistor. This IC
cannot transmit normally without using a pull-up resistor.
In case that the SCL input pin of this IC is connected to the Nch open-drain output pin of the master device, connect
the SCL pin with a pull-up resistor. As well, in case the SCL input pin of this IC is connected to the tri-state output pin
of the master device, connect the SCL pin with a pull-up resistor in order not to set it in "High-Z". This prevents this IC
from error caused by an uncertain output (High-Z) from the tri-state pin when resetting the master device during the
voltage drop.
2. Equivalent circuits of input pin and I/O pin
The SCL pin and the SDA pin of this IC does not have a built-in pull-down or pull-up resistor. Each of A0 pin, A1 pin,
A2 pin and WP pin has a built-in pull-down resistor. The SDA pin is an open-drain output. The followings are
equivalent circuits of the pins.
SDA
SCL
Figure 16 SCL Pin
Figure 17 SDA Pin
A0, A1, A2
WP
Figure 18 WP Pin
Figure 19 A0, A1, A2 Pin
Remark In the S-24C04D/08D/16D, A0 pin is not available.
In the S-24C08D/16D, A1 pin is not available.
In the S-24C16D, A2 pin is not available.
The A0 pin, the A1 pin and the A2 pin are no connection in the product with SOT-23-5 package.
21
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
3. Phase adjustment of the I2C-bus product
The I2C-bus product does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If
the communication interrupted, the users need to handle it as you do for software.
In this IC, users are able to reset the internal circuit by inputting a start condition and a stop condition.
Although the reset signal is input to the master device, this IC’s internal circuit does not go in reset, but it does by
inputting a stop condition to this IC. This IC keeps the same status thus cannot do the next operation. Especially, this
case corresponds to that only the master device is reset when the power supply voltage drops.
If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with the
master device) this IC. How to reset is shown below.
[How to reset this IC]
This IC is able to be reset by a start and stop instructions. When this IC is reading data "0" or is outputting the
acknowledgment signal, outputs "0" to the SDA line. In this status, the master device cannot output an instruction to
the SDA line. In this case, terminate the acknowledgment output operation or the Read operation, and then input a
start condition.
Figure 20 shows this procedure.
First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets
the SDA line to "H". By this operation, this IC interrupts the acknowledgment output operation or data output, so
input a start condition*1. When a start condition is input, this IC is reset. To make doubly sure, input the stop
condition to this IC. The normal operation is then possible.
Start
Condition
Start
Condition
Dummy Clock
1
2
8
Stop
Condition
9
SCL
SDA
Figure 20 Resetting Method
*1. After 9 clocks (dummy clock), if the SCL clock continues to being output without inputting a start condition, this
IC may go in the write operation when it receives a stop condition. To prevent this, input a start condition after 9
clocks (dummy clock).
Remark
22
Regarding this reset procedure with dummy clock, it is recommended to perform at the system
initialization after applying the power supply voltage.
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
4. Acknowledge check
The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication
error. This function allows detection of a communication failure during data communication between the master
device and this IC. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge
check with the master device.
5. Power-on-clear circuit
By power-on-clear circuit, this IC initializes at the same time when the power supply voltage is raised. After the
initialization by the power-on-clear circuit is completed, this IC becomes standby state.
In order to use this IC safely, raise the power supply voltage depending on the following conditions.
5. 1 Initialization time
This IC initializes at the same time when the power supply voltage is raised. Input instructions to this IC after
initialization. This IC does not accept any instruction during initialization.
Figure 21 shows the initialization time of this IC.
100 m
10 m
Initialization time
(tINIT) max.
[s]
1.0 m
100
10
1.0
1.0
10 100 1.0 m 10 m 100 m
Rise time (tRISE)
[s]
Figure 21 Initialization Time
23
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
5. 2 Caution when raising the power supply voltage
The internal circuit of this IC is reset by the power-on-clear circuit. In order for the power-on-clear circuit to
operate normally, the condition showed in Table 11 must be obeyed for raising the power supply voltage.
Due to the voltage drop, this IC may not perform normal communication if the power-on-clear operation condition
is not fulfilled, even when the master device is reset.
However, the interface of this IC is reset normally and the master device can make normal communication if
phase adjustment is performed, even when the power-on-clear operation condition of this IC is not fulfilled.
Table 11
Item
Power-off time
Power-off voltage
Symbol
tOFF
VBOT
Min.
Max.
Unit
100
0.6
s
V
VCC min.
Power supply
voltage
0V
VBOT
*1
tINIT
*2
tOFF
tINIT
*2
*1. 0 V means that there is no potential difference between the VCC pin and the GND pin of this IC.
*2. tINIT is the time to initialize the internal IC. This IC does not accept any instruction during the initialization time.
Figure 22 Caution When Raising the Power Supply Voltage
6. Write protect function during the low power supply voltage
This IC has a built-in detection circuit which operates with the low power supply voltage, cancels Write when the power
supply voltage drops and power-on. Its detection and release voltages are 1.3 V typ. (refer to Figure 23).
This IC cancels Write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission
and the Write operation, data in the address written during the low power supply voltage is not assurable.
Power supply voltage
Detection voltage (VDET)
1.3 V typ.
Release voltage (VDET)
1.3 V typ.
Write instruction cancel
Figure 23 Operation during Low Power Supply Voltage
24
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
7. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of this IC are changed at the same time, it is necessary to prevent a start / stop condition from being
mistakenly recognized due to the effect of noise.
This IC may error if it does not recognize a start / stop condition correctly during transmission.
In this IC, it is recommended to set the delay time of 0.3 s minimum from a falling edge of SCL for the SDA.
This is to prevent this IC from going in a start / stop condition due to the time lag caused by the load of the bus line.
tHD.DAT = 0.3 s min.
SCL
SDA
Figure 24 Data Hold Time
8. SDA pin and SCL pin noise suppression time
This IC includes a built-in low-pass filter at the SDA pin and the SCL pin to suppress noise. If the power supply
voltage is 5.0 V, this suppression time can be suppressed noise with a pulse width of approx. 80 ns.
For details of the assurable value, refer to noise suppression time (tl) in Table 10 in " AC Electrical
Characteristics".
300
Noise suppression time
(tI) max.
200
[ns]
100
2
3
4
5
Power supply voltage (VCC)
[V]
Figure 25 Noise Suppression Time for SDA Pin and SCL Pin
25
2-WIRE SERIAL E2PROM
S-24C02D/04D/08D16D
Rev.3.0_02_U
9. Operation when input stop condition during input write data
This IC does the write operation only when it receives data of 1 byte or more and receives a stop condition
immediately after acknowledge output.
Refer to Figure 26 regarding details.
Write valid
by stop condition
Write invalid
by stop condition
S
T
A
R
T
SDA
LINE
Write invalid
by stop condition
W
R
I
T
E
WORD ADDRESS (n)
DATA (n)
1 0 1 0 A2 A1 A0 0
W7W6 W5W4 W3 W2 W1W0
D7 D6 D5 D4 D3 D2 D1 D0
DEVICE
ADDRESS
M
S
B
L R A
S / C
BWK
A
C
K
Write valid
by stop condition
Write invalid
by stop condition
DATA (n 1)
D7
A
C
K
Write valid
by stop condition
S
T
O
P
DATA (n x)
D0
D7
A
C
K
D0
A
C
K
Remark A0 is P0 in the S-24C04D/08D/16D.
A1 is P1 in the S-24C08D/16D.
A2 is P2 in the S-24C16D.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 26 Write Operation by Inputting Stop Condition during Write
10. Command cancel by start condition
By a start condition, users are able to cancel command which is being input. However, adjust the phase while this IC
is outputting "L" because users are not able to input a start condition. When users cancel the command, there may be
a case that the address will not be identified. Use random read for the read operation, not current address read.
Precautions
Do not operate these ICs in excess of the absolute maximum ratings. Attention should be paid to the power supply
voltage, especially. The surge voltage which exceeds the absolute maximum ratings can cause latch-up and
malfunction. Perform operations after confirming the detailed operation condition in the data sheet.
Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
26
+0.20
5.02 -0.35
8
5
1
4
1.27
0.20±0.05
+0.11
0.4 -0.07
No. FJ008-Z-P-SD-2.1
TITLE
SOP8J-Z-PKG Dimensions
FJ008-Z-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø1.5 min.
8.0±0.1
2.1±0.1
+0.30
6.5 -0.25
1
8
4
5
Feed direction
No. FJ008-Z-C-SD-1.0
TITLE
SOP8J-Z-Carrier Tape
No.
FJ008-Z-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
17.5±1.5
13.4±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-Z-R-SD-1.0
TITLE
SOP8J-Z-Reel
No.
FJ008-Z-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
+0.3
3.00 -0.2
8
5
1
4
0.15±0.07
0.2±0.1
0.65
No. FT008-Z-P-SD-1.2
TITLE
TSSOP8-Z-PKG Dimensions
FT008-Z-P-SD-1.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
0.3±0.05
ø1.55±0.05
+0.2
8.0±0.1
ø1.55 -0.05
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-Z-C-SD-1.0
TITLE
TSSOP8-Z-Carrier Tape
No.
FT008-Z-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT008-Z-R-SD-1.0
TSSOP8-Z-Reel
TITLE
FT008-Z-R-SD-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
4.00±0.1
4.00±0.1
1.00±0.1
+0.1
1.5 -0
1.05±0.05
0.30±0.05
3.25±0.05
4
1
5
8
Feed direction
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
16.5max.
13.0±0.3
Enlarged drawing in the central part
13±0.2
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
2.9±0.2
1.9±0.2
4
5
1
2
+0.1
0.16 -0.06
3
0.95±0.1
0.4±0.1
No. MP005-A-P-SD-1.3
TITLE
SOT235-B-PKG Dimensions
No.
MP005-A-P-SD-1.3
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
ø1.5 -0
+0.25
ø1.0 -0
2.0±0.05
0.25±0.1
4.0±0.1
1.4±0.2
3.2±0.2
3 2 1
4
5
Feed direction
No. MP005-B-C-SD-1.0
TITLE
SOT235-B-Carrier Tape
No.
MP005-B-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.2±0.5
Enlarged drawing in the central part
ø13±0.2
No. MP005-B-R-SD-1.0
TITLE
SOT235-B-Reel
No.
MP005-B-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
3,000
2.0±0.1
(1.70)
+0.05
0.08 -0.02
0.5
0.23±0.1
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
No. PP008-A-P-S1-2.0
TITLE
DFN-8/HSNT-8-A-PKG Dimensions
No.
PP008-A-P-S1-2.0
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.0±0.05
4.0±0.1
0.25±0.05
+0.1
ø1.0 -0
0.60±0.05
4.0±0.1
2.3±0.05
4 321
5 6 78
Feed direction
No. PP008-A-C-SD-1.0
TITLE
DFN-8/HSNT-8-A-Carrier Tape
No.
PP008-A-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
+1.0
9.0 - 0.0
11.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PP008-A-R-SD-1.0
TITLE
DFN-8/HSNT-8-A-Reel
No.
PP008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
1.6
0.30
0.50
No. PP008-A-L-SD-1.0
TITLE
No.
DFN-8/HSNT-8-A
-Land Recommendation
PP008-A-L-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.25±0.05
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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