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S-24C128CI-J8T1U3

S-24C128CI-J8T1U3

  • 厂商:

    SII(精工半导体)

  • 封装:

    SOIC8_150MIL

  • 描述:

    ICEEPROM128KBIT400KHZ8SOP

  • 数据手册
  • 价格&库存
S-24C128CI-J8T1U3 数据手册
S-24C128C 2-WIRE SERIAL E2PROM www.ablic.com www.ablicinc.com Rev.4.0_03_H © ABLIC Inc., 2009-2013 The S-24C128C is a 2-wire, low current consumption and wide range operation serial E2PROM. The S-24C128C has the capacity of 128K-bit, and the organization is 16384 words  8-bit. Page write and sequential read are available.  Features  Operating voltage range Read: 1.6 V to 5.5 V Write: 1.7 V to 5.5 V 64 bytes / page  Page write:  Sequential read  Operation frequency: 400 kHz (VCC = 1.6 V to 5.5 V)  Write time: 5.0 ms max.  Noise suppression: Schmitt trigger and noise filter on input pins (SCL, SDA)  Write protect function during the low power supply voltage  Endurance: 106cycles / word*1 (Ta = 25°C)  Data retention: 100 years (Ta = 25°C)  Memory capacity: 128 K-bit  Write protect: 100%  Initial shipment data: FFh  Lead-free (Sn 100%), halogen-free*2 *1. For each address (Word: 8-bit) *2. Refer to “ Product Name Structure” for details.  Packages  8-Pin SOP (JEDEC)  8-Pin TSSOP Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is indispensable. 1 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Pin Configurations 1. 8-Pin SOP (JEDEC) 8-Pin SOP (JEDEC) Top view Table 1 1 8 2 7 3 6 4 5 Figure 1 S-24C128CI-J8T1U3 Pin No Symbol 1 2 3 4 5 6 A0 A1 A2 GND SDA*1 SCL*1 Description Slave address input Slave address input Slave address input Ground Serial data I/O Serial clock input Write protect input 7 WP Connected to VCC: Protection valid Open or connected to GND: Protection invalid 8 VCC Power supply *1. Do not use it in high impedance. 2. 8-Pin TSSOP 8-Pin TSSOP Top view 1 2 3 4 Table 2 8 7 6 5 Figure 2 S-24C128CI-T8T1U3 Pin No Symbol 1 2 3 4 5 6 A0 A1 A2 GND SDA*1 SCL*1 Slave address input Slave address input Slave address input Ground Serial data I/O Serial clock input Write protect input 7 WP Connected to VCC: Protection valid Open or connected to GND: Protection invalid 8 VCC Power supply *1. Do not use it in high impedance. Remark Refer to the “Package drawings” for the details. 2 Description 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Block Diagram VCC WP SCL GND Start / Stop Detector SDA Voltage Detector Serial Clock Controller High-Voltage Generator LOAD Device Address Comparator COMP Data Register LOAD INC A2 R/W A1 Address Counter X Decoder Memory Cell Array A0 Y Decoder Selector Data Output ACK Output Controller DIN DOUT Figure 3 3 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Absolute Maximum Ratings Table 3 Item Power supply voltage Input voltage Output voltage Operation ambient temperature Storage temperature Symbol VCC VIN VOUT Topr Tstg Absolute Maximum Ratings 0.3 to 6.5 0.3 to 6.5 0.3 to 6.5 40 to 85 65 to 150 Unit V V V °C °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operating Conditions Table 4 Item Symbol Power supply voltage VCC High level input voltage Low level input voltage VIH VIL Condition Read Operation Write Operation VCC = 1.6 V to 5.5 V VCC = 1.6 V to 5.5 V Ta = 40°C to 85°C Min. Max. 1.6 1.7 5.5 5.5 0.7  VCC 0.3 5.5 0.3  VCC Unit V V V V  Pin Capacitance Table 5 Item Input capacitance I/O capacitance Symbol Condition CIN VIN = 0 V (SCL, A0, A1, A2, WP) CI / O VI / O = 0 V (SDA) (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Min. Max. Unit  10 pF  10 pF  Endurance Table 6 Item Symbol Endurance NW *1. For each address (Word: 8-bit) Operation Ambient Temperature Ta = 25°C Min. 106 Max.  Unit cycles / word*1 Min. 100 Max.  Unit year  Data Retention Table 7 Item Data retention 4 Symbol  Operation Ambient Temperature Ta = 25°C 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  DC Electrical Characteristics Table 8 Item Ta = 40°C to 85°C VCC = 1.6 V to 5.5 V fSCL = 400 kHz Min. Max.  0.8 Symbol Condition Current consumption (READ)  ICC1 Unit mA Table 9 Item Ta = 40°C to 85°C VCC = 1.7 V to 5.5 V fSCL = 400 kHz Min. Max.  4.0 Symbol Condition Current consumption (WRITE)  ICC2 Unit mA Table 10 Ta = 40°C to 85°C Item Symbol Standby current consumption ISB Input leakage current 1 ILI1 Input leakage current 2 ILI2 Output leakage current ILO Input current 1 IIL Input current 2 IIH Input Impedance 1 ZIL Input Impedance 2 ZIH Low level output voltage VOL Condition VIN = VCC or GND SCL, SDA, VIN = GND to VCC A0, A1, A2 VIN > 0.7  VCC At standby mode SDA VOUT = GND to VCC WP VIN < 0.3  VCC WP VIN > 0.7  VCC WP VIN = 0.3  VCC WP VIN = 0.7  VCC IOL = 3.2 mA IOL = 1.5 mA IOL = 0.7 mA VCC = 2.5 V to 5.5 V VCC = 1.8 V to 5.5 V VCC = 1.6 V to 1.8 V Unit Min. Max. Min. Max. Min. Max.  4.5  4.5  2.0 A  1.0  1.0  1.0 A  1.0  1.0  1.0 A  1.0  1.0  1.0 A  50.0  50.0  50.0 A  2.0  2.0  2.0 A 30  30  30  k 500  500  500  k    0.4 0.3 0.2     0.3 0.2     0.3 0.2 V V V 5 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  AC Electrical Characteristics Table 11 Measurement Conditions Input pulse voltage Input pulse rising / falling time Output reference voltage Output load Input pulse voltage 0.2  VCC to 0.8  VCC 20 ns or less 0.3  VCC to 0.7  VCC 100 pF Output reference voltage 0.8  VCC 0.7  VCC 0.3  VCC 0.2  VCC Figure 4 I/O Waveform during AC Measurement Table 12 Item Ta = 40°C to 85°C VCC = 1.6 V to 5.5 V Min. Max. 0 400 1.3  0.6  0.1 0.9 50  0.6  0.6  100  0  0.6   0.3  0.3 0  0  0  0  1.3   50 Symbol SCL clock frequency SCL clock time “L” SCL clock time “H” SDA output delay time SDA output hold time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time SCL, SDA rising time SCL, SDA falling time WP setup time WP hold time WP release setup time WP release hold time Bus release time Noise suppression time fSCL tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tWS1 tWH1 tWS2 tWH2 tBUF tI tHIGH tF tLOW Unit kHz s s s ns s s ns ns s s s s s s s s ns tR SCL tHD.STA tHD.DAT tSU.STA tSU.DAT tSU.STO SDA (input) tAA tDH SDA (output) Figure 5 Bus Timing 6 tBUF 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H Table 13 Item Write time Start Condition Symbol tWR Ta = 40°C to 85°C VCC = 1.7 V to 5.5 V Min. Max.  5.0 Acknowledgment Signal Write data Stop Condition Unit ms tWR Start Condition SCL D0 SDA tWS1 tWH1 tWS2 tWH2 WP (valid) WP (invalid) Figure 6 Write Cycle Timing 7 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Pin Functions 1. A0, A1 and A2 (Slave Address Input) Pins In the S-24C128C, to set the slave address, connect each pin of A0, A1, A2 to GND or VCC. Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins. Comparing the slave address transmitted from the master device and one that you set, makes possible to select the S-24C128C from other devices connected onto the bus. Each A0, A1 and A2 pin has a pull-down resistor. In open, these pins are set to the same status as they are connected to GND. 2. SDA (Serial Data Input / Output) Pin The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch open drain output pin. In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with Wired-OR connection by pulling up to VCC by a resistor (Figure 7 shows the relation with an output load). 3. SCL (Serial Clock Input) Pin The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. 4. WP (Write Protect Input) Pin The write protect is enabled by connecting the WP pin to VCC. When not using the write protect, connect this pin to GND or set in open. 20 18 16 14 Maximum value of 12 pull-up resistor 10 [k] 8 fSCL = 400 kHz 6 4 2 0 100 10 Value of load capacity [pF] Figure 7 Output Load  Initial Shipment Data Initial shipment data of all addresses is “FFh”. 8 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Operation 1. Start Condition Start is identified by a high to low transition of the SDA line while the SCL line is stable at high. Every operation begins from a start condition. 2. Stop Condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device enters standby mode. When a device receives a stop condition during a write sequence, the reception of the write data is halted, and the S-24C128C initiates a write cycle. tSU.STA tHD.STA tSU.STO SCL SDA Start Condition Stop Condition Figure 8 Start / Stop Conditions 9 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 3. Data Transmission Changing the SDA line while the SCL line is low, data is transmitted. Changing the SDA line while the SCL line is high, a start or stop condition is recognized. tSU.DAT tHD.DAT SCL SDA Figure 9 Data Transmission Timing 4. Acknowledge The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA line to acknowledge the receipt of the 8-bit data. When an internal write cycle is in progress, the device does not generate an acknowledge. SCL (E2PROM Input) 1 8 9 SDA (Master Output) Acknowledge Output SDA (E PROM Output) 2 Start Condition tAA Figure 10 Acknowledge Output Timing 10 tDH 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 5. Device Addressing To start communication, the master device on the system generates a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus. The upper 4 bits of the device address are the “Device Code”, and are fixed to “1010”. In the S-24C128C, successive 3 bits are the “Slave Address”. These 3 bits are used to identify a device on the system bus and is compared with the predetermined value which is defined by the address input pins (A2, A1, A0). When the comparison result matches, the slave device responds with an acknowlede during the 9th clocks cycle. Slave Address Device Code 1 0 1 0 A2 A1 MSB A0 R/W LSB Figure 11 Device Address 11 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 6. Write 6. 1 Byte write When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, the S-24C128C acknowledges it. The S-24C128C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C128C receives a lower 8-bit word address and responds with an acknowledge. After the S-24C128C receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory. During the write cycle all operations are forbidden and no acknowledge is generated. S T A R T SDA LINE DEVICE ADDRESS W R I T E 1 0 1 0 A2 A1 A0 0 M S B L R A S / C B W K UPPER WORD ADDRESS LOWER WORD ADDRESS DATA X X W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0 A C K Figure 12 Byte Write 12 A C K S T O P A C K 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 6. 2 Page write The page write mode allows up to 64 bytes to be written in a single write operation in the S-24C128C. Its basic process to transmit data is as same as byte write, but it operates page write by sequentially receiving 8bit write data as much data as the page size has. When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, it generates an acknowledge. And the S-24C128C receives a upper 8-bit word address, and responds with an acknowledge. Then the S-24C128C receives a lower 8-bit word address, and responds with an acknowledge. After the S-24C128C receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. The S-24C128C repeats reception of 8-bit write data and generation of acknowledge in succession. The S-24C128C can receive as many write data as the maximum page size. Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data. W R I T E UPPER WORD ADDRESS (n) 1 0 1 0 A2 A1 A0 0 X X W13 W12 W11 W10 W9 W8 S T A R T SDA LINE DEVICE ADDRESS M S B L R A S / C B W K LOWER WORD ADDRESS (n) DATA (n) W7 W6 W5 W4 W3 W2 W1 W0 A C K D7 S T O P DATA (n+x) D0 D7 D0 A C K Figure 13 Page Write In the S-24C128C, the lower 6 bits of the word address are automatically incremented every time when the S-24C128C receives 8-bit write data. If the size of the write data exceeds 64 bytes, the upper 8 bits of the word address remain unchanged, and the lower 6 bits are rolled over and the last 64-byte data that the S-24C128C received will be overwritten. 13 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 6. 3 Write protect Write protect is available in the S-24C128C. When the WP pin is connected to the VCC, write operation to memory area is inhibited. When the WP pin is connected to GND or set in open, the write protect is invalid, and write operation in all memory area is available. Fix the level of the WP pin from start condition in the write operation (byte write, page write) until stop condition. If the WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding the timing of write protect, refer to Figure 6. In not using the write protect, connect the WP pin to GND or set it open. The write protect is valid in the range of operation power supply voltage. As seen in Figure 14 when the write protect is valid, the S-24C128C does not generate an acknowledgment signal after data input. S T A R T SDA LINE DEVICE ADDRESS W R I T E 1 0 1 0 A2 A1 A0 0 M S B L R A S / C B W K UPPER WORD ADDRESS LOWER WORD ADDRESS DATA X X W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0 A C K WP Figure 14 Write Protect 14 A C K S T O P N A C K 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 6. 4 Acknowledge polling Acknowledge polling is used to know the completion of the write cycle in the S-24C128C. After the S-24C128C receives a stop condition and once starts the write cycle, all operations are inhibited and no response is made to the signal transmitted by the master device. Accordingly the master device can recognize the completion of the write cycle in the S-24C128C by detecting a response from the slave device after transmitting the start condition, the device address and the read / write instruction code to the S-24C128C (slave device). That is, if the S-24C128C does not generate an acknowledgment signal, the write cycle is in progress and if the S-24C128C generates an acknowledgment signal, the write cycle has been completed. It is recommended to use the read instruction “1” as the read / write instruction code transmitted by the master device. Acknowledge polling during write DATA SDA LINE D2 D1 D0 S T O P W R I T E S T A R T S T A R T DEVICE ADDRESS 0 W R I T E DEVICE ADDRESS 0 R N / A W C K WORD ADDRESS A C K R A / C WK tWR Acknowledge polling during read S S T T A O R P DATA T SDA DEVICE D2 D1 D0 ADDRESS LINE R E A D 1 R N / A W C K S T A R T NO ACK from R Master Device E A D DEVICE ADDRESS 1 DATA R A / C WK S T O P S T A R T DEVICE ADDRESS R A / C WK tWR Remark Users are able to input word address and data after ACK output in acknowledge polling during write. Users are able to read data after ACK output in acknowledge polling during read. However, after that users input the write instruction, a start condition may not be input during data output. Input a stop condition and the next instruction after data output and ACK output. Figure 15 Usage Example of Acknowledge Polling 15 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 7. Read 7. 1 Current address read Either in writing or in reading the S-24C128C holds the last accessed memory address. The memory address is maintained as long as the power voltage does not decrease less than the operating voltage. The master device can read the data at the memory address of the current address pointer without assigning the word address as a result, when it recognizes the position of the address pointer in the S-24C128C. This is called “Current Address Read”. In the following the address counter in the S-24C128C is assumed to be “n”. When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition, it responds with an acknowledge. Next, an 8-bit data at the address “n” is sent from the S-24C128C synchronous to the SCL clock. The address counter is incremented and the content of the address counter becomes n1. The master device outputs stop condition not an acknowledge, the reading of S-24C128C is ended. S T A R T SDA LINE DEVICE ADDRESS R E A D 1 0 1 0 A2 A1 A0 1 M S B L R A S / C B W K NO ACK from Master Device S T O P D7 D6 D5 D4 D3 D2 D1 D0 DATA Figure 16 Current Address Read Attention should be paid to the following point on the recognition of the address pointer in the S-24C128C. In Read, the memory address counter in the S-24C128C is automatically incremented after output of the 8th bit of the data. In Write, on the other hand, the upper bits of the memory address (the upper bits of the word address*1) are left unchanged and are not incremented.  16 1. The upper 8 bits of the word address 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 7. 2 Random read Random read is used to read the data at an arbitrary memory address. A dummy write is performed to load the memory address into the address counter. When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following a start condition, it responds with an acknowledge. The S-24C128C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C128C receives a lower 8-bit word address and responds with an acknowledge. The memory address is loaded to the address counter in the S-24C128C by these operations. Reception of write data does not follow in a dummy write whereas reception of write data follows in byte write and in page write. Since the memory address is loaded into the memory address counter by dummy write, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition and performing the same operation in the current address read. That is, when the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the S-24C128C in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge, the reading of S-24C128C is ended. S T A R T SDA LINE DEVICE ADDRESS W R I T E 1 0 1 0 A2 A1 A0 0 M S B LOWER WORD ADDRESS UPPER WORD ADDRESS X X X W13W12W11W10 W9W8 L R A S / C B W K S T A R T 1 0 1 0 A2 A1 A0 1 W7 W6 W5 W4 W3 W2 W1 W0 A C K DEVICE ADDRESS R E A D A C K M S B NO ACK from Master Device DATA 下図へ続く D7 D6 D5 D4 D3 D2 D1 D0 L R A S / C B W K DUMMY WRITE Figure 17 Random Read 17 S T O P 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 7. 3 Sequential read When the S-24C128C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current address read and random read, it responds with an acknowledge. When an 8-bit data is output from the S-24C128C synchronous to the SCL clock, the address counter is automatically incremented. When the master device responds with an acknowledge, the data at the next memory address is transmitted. Response with an acknowledge by the master device has the memory address counter in the S-24C128C incremented and makes it possible to read data in succession. This is called “Sequential Read”. The master device outputs stop condition not an acknowledge, the reading of S-24C128C is ended. Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first word address. DEVICE ADDRESS SDA LINE NO ACK from Master Device R E A D 1 R A / C W K A C K D7 D0 DATA (n) A C K D7 D0 D7 DATA (n+1) Figure 18 Sequential Read 18 S T O P A C K D0 DATA (n+2) D7 D0 DATA (n+x) 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Write Protect Function during the Low Power Supply Voltage The S-24C128C has a built-in detection circuit which operates with the low power supply voltage, cancels Write when the power supply voltage drops and power-on. Its detection and release voltages are 1.20 V typ. (Refer to Figure 19). The S-24C128C cancels Write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not assurable. Power Supply Voltage Detection Voltage (VDET) 1.20 V typ. Release Voltage (VDET) 1.20 V typ. Write Instruction cancel Figure 19 Operation during Low Power Supply Voltage 19 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Using S-24C128C 1. Adding a pull-up resistor to SDA I/O pin and SCL input pin In consideration of I2C-bus protocol function, the SDA I/O pins should be connected with a pull-up resistor. The S-24C128C cannot transmit normally without using a pull-up resistor. In case that the SCL input pin of the S-24C128C is connected to the Nch open drain output pin of the master device, connect the SCL pin with a pull-up resistor. As well, in case the SCL input pin of the S-24C128C is connected to the tri-state output pin of the master device, connect the SCL pin with a pull-up resistor in order not to set it in high impedance. This prevents the S-24C128C from error caused by an uncertain output (high impedance) from the tri-state pin when resetting the master device during the voltage drop. 2. Equivalent circuit of input and I/O pin The S-24C128C does not have a built-in pull-down or pull-up resistor for the SCL and SDA pins. The WP, A2, A1 and A0 pins have a pull-down resistor. The SDA pin has an open-drain output. The followings are equivalent circuits of the pins. SCL Figure 20 SCL Pin SDA Figure 21 SDA Pin 20 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H WP Figure 22 WP Pin A0, A1, A2 Figure 23 A0, A1, A2 Pins 21 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 3. Phase adjustment during S-24C128C access The S-24C128C does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If the communication to the S-24C128C interrupted, the users need to handle it as you do for software. In the S-24C128C, users are able to reset the internal circuit by inputting a start condition and a stop condition. Although the reset signal is input to the master device, the S-24C128C’s internal circuit does not go in reset, but it does by inputting a stop condition to the S-24C128C. The S-24C128C keeps the same status thus cannot do the next operation. Especially, this case corresponds to that only the master device is reset when the power supply voltage drops. If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with the master device) the S-24C128C. How to reset is shown below. [How to reset S-24C128C] The S-24C128C is able to be reset by a start and stop instructions. When the S-24C128C is reading data “0” or is outputting the acknowledgment signal, outputs “0” to the SDA line. In this status, the master device cannot output an instruction to the SDA line. In this case, terminate the acknowledgment output operation or the Read operation, and then input a start instruction. Figure 24 shows this procedure. First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets the SDA line to “H”. By this operation, the S-24C128C interrupts the acknowledgment output operation or data output, so input a start condition*1. When a start condition is input, the S-24C128C is reset. To make doubly sure, input the stop condition to the S-24C128C. The normal operation is then possible. Start Condition Start Condition Dummy Clock 1 2 8 Stop Condition 9 SCL SDA Figure 24 Resetting S-24C128C *1. After 9 clocks (dummy clock), if the SCL clock continues to being output without inputting a start condition, S-24C128C may go in the write operation when it receives a stop condition. To prevent this, input a start condition after 9 clocks (dummy clock). Remark 22 Regarding this reset procedure with dummy clock, it is recommended to perform at the system initialization after applying the power supply voltage. 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 4. Acknowledge check The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication error. This function allows detection of a communication failure during data communication between the master device and S-24C128C. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge check with the master device. 5. Built-in power-on-clear circuit The S-24C128C has a built-in power-on-clear circuit that initializes itself at the same time during power-on. Unsuccessful initialization may cause a malfunction. To operate the power-on-clear circuit normally, the following conditions must be satisfied to raise the power supply voltage. 5. 1 Raising power supply voltage Shown in Figure 25, raise the power supply voltage from 0.2 V max., within the time defined as tRISE which is the time required to reach the power supply voltage to be set. For example, if the power supply voltage is 5.0 V, tRISE = 200 ms seen in Figure 26. The power supply voltage must be raised within 200 ms. tRISE max. Power Supply Voltage (VCC) VINIT max. 0.2 V 0V *1 *2 tINIT max. *1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-24C128C. *2. tINIT is the time required to initialize the S-24C128C. No instructions are accepted during this time. Figure 25 Raising Power Supply Voltage 23 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 5.0 4.0 Power Supply Voltage (VCC) [V] 3.0 2.0 50 100 150 200 Power Supply Voltage Rise Time (tRISE) max. [ms] For example: If the power supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms. Figure 26 Power Supply Voltage Rise Time When initialization is successfully completed by the power-on-clear circuit, the S-24C128C enters the standby status. If the power-on-clear circuit does not operate; The S-24C128C has not completed initialization, an instruction previously input is still valid or an instruction may be inappropriately recognized. In this case, S-24C128C may perform the Write operation. The voltage drops due to power off while the S-24C128C is being accessed. Even if the master device is reset due to the low power voltage, the S-24C128C may malfunction unless the power-on-clear operation conditions of S-24C128C are satisfied. When not keeping to the power supply voltage rise time seen in Figure 26, adjust the phase (reset) to reset the internal circuit in the S-24C128C normally. 24 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 5. 2 Initialization time The S-24C128C initializes at the same time when the power supply voltage is raised. Input instructions to the S-24C128C after initialization. S-24C128C does not accept any instruction during initialization. Figure 27 shows the initialization time of the S-24C128C. 100 m 10 m Initialization Time (tINIT) max. [s] 1.0 m 100  10  1.0  1.0  10  100  1.0 m 10 m 100 m Power Supply Voltage Rise Time (tRISE) [s] Figure 27 Initialization Time of S-24C128C 25 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 6. Data hold time (tHD.DAT = 0 ns) If SCL and SDA of the S-24C128C are changed at the same time, it is necessary to prevent a start / stop condition from being mistakenly recognized due to the effect of noise. The S-24C128C may error if it does not recognize a start / stop condition correctly during transmission. It is recommended to set the delay time of 0.3 s minimum from a falling edge of SCL for the SDA. This is to prevent S-24C128C from going in a start / stop condition due to the time lag caused by the load of the bus line. tHD.DAT = 0.3 s min. SCL SDA Figure 28 S-24C128C Data Hold Time 7. SDA pin and SCL pin noise suppression time The S-24C128C includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if the power supply voltage is 5.0 V, noise with a pulse width of 130 ns or less can be suppressed. For details of the assurable value, refer to noise suppression time (tl) in Table 12. 300 Noise Suppression Time (tI) max. [ns] 200 100 2 3 4 5 Power supply voltage (VCC) [V] Figure 29 Noise Suppression Time for SDA and SCL Pins 26 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H 8. Operation when input stop condition during input write data The S-24C128C does the write operation only when it receives data of 1 byte or more and receives a stop condition immediately after ACK output. Refer to Figure 30 regarding details. Write Enable by stop condition Write Inhibition by stop condition S T A R T SDA LINE DEVICE ADDRESS W R I T E 1 0 1 0 A2 A1 A0 0 M S B LOWER WORD ADDRESS (n) UPPER WORD ADDRESS (n) x x W13 L R A S / C BWK W7 W8 A C K Write Inhibition by stop condition D7 D6 D5 D4 D3 D2 D1 D0 A C K D7 Write Enable by stop condition Write Inhibition by stop condition DATA (n+1) DATA (n) W0 Write Enable by stop condition S T O P DATA (n+x) D0 A C K D7 A C K D0 A C K Figure 30 Write Operation by Inputting Stop Condition during Write 9. Command cancel by start condition By a start condition, users are able to cancel command which is being input. However, adjust the phase while the S-24C128C is outputting “L” because users are not able to input a start condition. When users cancel the command, there may be a case that the address will not be identified. Use random read for the read operation, not current address read. 10. Precaution for use Do not operate these ICs in excess of the absolute maximum ratings. Attention should be paid to the power supply voltage, especially. The surge voltage which exceeds the maximum absolute ratings can cause latch-up and malfunction. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on the S-24C128C pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking the S-24C128C up from low temperature tank during the evaluation. Be sure that not remain frost on the S-24C128C’s pins to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason. 27 2-WIRE SERIAL E2PROM S-24C128C Rev.4.0_03_H  Precautions ● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ● ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.  Product Name Structure 1. Product name S-24C128C I  xxxx U 3 Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specification J8T1: 8-Pin SOP (JEDEC), Tape T8T1: 8-Pin TSSOP, Tape Fixed Product name S-24C128C : 128 K-bit 2. Packages Package name 8-Pin SOP (JEDEC) 8-Pin TSSOP 28 Package FJ008-Z-P-SD FT008-Z-P-SD Drawing code Tape FJ008-Z-C-SD FT008-Z-C-SD Reel FJ008-Z-R-SD FT008-Z-R-SD +0.20 5.02 -0.35 8 5 1 4 1.27 0.20±0.05 +0.11 0.4 -0.07 No. FJ008-Z-P-SD-2.1 TITLE SOP8J-Z-PKG Dimensions FJ008-Z-P-SD-2.1 No. ANGLE UNIT mm ABLIC Inc. 4.0±0.1(10 pitches:40.0±0.2) 2.0±0.05 ø1.55±0.05 0.3±0.05 ø1.5 min. 8.0±0.1 2.1±0.1 +0.30 6.5 -0.25 1 8 4 5 Feed direction No. FJ008-Z-C-SD-1.0 TITLE SOP8J-Z-Carrier Tape No. FJ008-Z-C-SD-1.0 ANGLE UNIT mm ABLIC Inc. 17.5±1.5 13.4±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 No. FJ008-Z-R-SD-1.0 TITLE SOP8J-Z-Reel No. FJ008-Z-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 4,000 +0.3 3.00 -0.2 8 5 1 4 0.15±0.07 0.2±0.1 0.65 No. FT008-Z-P-SD-1.2 TITLE TSSOP8-Z-PKG Dimensions FT008-Z-P-SD-1.2 No. ANGLE UNIT mm ABLIC Inc. 4.0±0.1 2.0±0.05 0.3±0.05 ø1.55±0.05 +0.2 8.0±0.1 ø1.55 -0.05 +0.4 6.6 -0.2 1 8 4 5 Feed direction No. FT008-Z-C-SD-1.0 TITLE TSSOP8-Z-Carrier Tape No. FT008-Z-C-SD-1.0 ANGLE UNIT mm ABLIC Inc. 13.4±1.0 17.5±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 No. FT008-Z-R-SD-1.0 TSSOP8-Z-Reel TITLE FT008-Z-R-SD-1.0 No. QTY. ANGLE UNIT mm ABLIC Inc. 4,000 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com
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