S-25C080A01-I8T1G

Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A The S-25C080A is a SPI serial E2PROM which operates at high speed, with low current consumption and the wide range operation. The S-25C080A has the capacity of 8K-bit and the organization of 1024 words × 8-bit, is able to Page Write and sequential read. Features • Wide range operation Read ：1.6 to 5.5 V (at −40 to +85°C) Write ：1.7 to 5.5 V (at −40 to +85°C) 5 MHz (2.5 to 5.5 V), 2.0 MHz (1.6 to 5.5 V) • Operation frequency • SPI mode (0, 0) and (1, 1) • Page Write 32 bytes / page • Sequential read • Write protect: Software, Hardware Protect area: 25%, 50%, 100% • Monitors Write to the memory by a status register • Write protect function during the low power supply • CMOS schmitt input（ CS , SCK, SI, WP , HOLD ） • Endurance: 106cycles/word*1 (at +25°C), *1. For each address (Word: 8-bit) • Data retention: 100 years (at +25°C) • Memory capacitance: 8K-bit • Data before shipment: Memory array FFh, SRWD = 0, BP1 = 0, BP0 = 0 • Lead-free product Packages Package name 8-Pin SOP (JEDEC) 8-Pin TSSOP SNT-8A WLP-8H Drawing code Package FJ008-A FT008-A PH008-A HH008-A Tape FJ008-D FT008-E PH008-A HH008-A Reel FJ008-D FT008-E PH008-A HH008-A Land − − PH008-A − Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable. Seiko Instruments Inc. 1 CMOS SPI 8K SERIAL E2PROM S-25C080A Pin Configurations 8-Pin SOP (JEDEC) Top view Pin No. Symbol CS *1 Rev.1.1_00 Table 1 Description Chip select input Serial data output *1 CS SO WP GND 1 2 3 4 8 7 6 5 Figure 1 VCC HOLD SCK SI 1 2 3 4 5 6 7 SO WP GND *1 SI *1 SCK Write protect input Ground Serial data input Serial clock input Hold input HOLD *1 S-25C080A0I-J8T1G 8 VCC Power supply *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation. Remark See Dimensions for details of the package drawings. 8-Pin TSSOP Top view Pin No. CS SO WP GND 1 2 3 4 8 7 6 5 Table 2 Symbol CS *1 Description Chip select input Serial data output Write protect input Ground Serial data input Serial clock input Hold input VCC 1 2 3 4 5 6 7 HOLD SCK SI SO WP GND *1 SI *1 SCK *1 Figure 2 S-25C080A0I-T8T1G HOLD *1 8 VCC Power supply *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation. Remark See Dimensions for details of the package drawings. 2 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A SNT-8A Top view Pin No. CS SO WP GND Table 3 Symbol CS *1 Description Chip select input Serial data output Write protect input Ground Serial data input Serial clock input Hold input Power supply 1 2 3 4 8 7 6 5 VCC 1 2 3 4 5 6 7 8 HOLD SCK SI SO WP GND *1 SI *1 SCK *1 Figure 3 S-25C080A0I-I8T1G HOLD *1 VCC *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation. Remark See Dimensions for details of the package drawings. WLP-8H Bottom view Pin No. A1 A1 VCC B2 HOLD A3 CS C3 SO C1 SCK D2 WP E3 GND E1 SI Table 4 Symbol VCC CS *1 HOLD SCK SO *1 *1 Description Power supply Chip select input Hold input Serial clock input Serial data output A3 B2 C1 C3 D2 Figure 4 S-25C080A0I-H8T3 *1 Write protect input WP *1 E1 SI Serial data input E3 GND Ground *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation. Remark See Dimensions for details of the package drawings. Seiko Instruments Inc. 3 CMOS SPI 8K SERIAL E2PROM S-25C080A Block Diagram Voltage Detector Rev.1.1_00 Step-up Circuit Page Latch Clock Counter Mode Decoder Data Register X Decoder Input Control Circuit CS SCK SI HOLD WP Memory Cell Array Status Memory Cell Array Y Decoder Address Register Output Control Circuit Status Register SO Read Circuit VCC GND Figure 5 4 Seiko Instruments Inc. Rev.1.1_00 Absolute Maximum Ratings Table 5 Item Power supply voltage Input voltage Output voltage Operation ambient temperature Storage temperature Symbol VCC VIN VOUT Topr Tstg CMOS SPI 8K SERIAL E2PROM S-25C080A Absolute Maximum Rating −0.3 to +7.0 −0.3 to +7.0 −0.3 to VCC + 0.3 −40 to +85 −65 to +150 Unit V V V °C °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 6 Item Power supply voltage High level input voltage Low level input voltage Symbol VCC VIH VIL Condition Read Operation Write Operation VCC = 1.6 to 5.5 V VCC = 1.6 to 5.5 V Min. 1.6 1.7 0.7 × VCC −0.3 Max. 5.5 5.5 VCC + 1.0 0.3 × VCC Unit V V V V Pin Capacitance Table 7 Item Input capacitance Output capacitance Symbol CIN COUT Condition VIN = 0 V ( CS , SCK, SI, WP , HOLD ) VOUT = 0 V (SO) (Ta = 25 °C, f = 1.0 MHz, VCC = 5 V) Min. Max. Unit − − 8 10 pF pF Endurance Table 8 Item Symbol Operation Ambient Temperature Endurance NW +25°C *1. For each address (Word: 8 bits) Min. 106 Max. − Unit cycles / word*1 Data Retention Table 9 Item Data retention Symbol − Operation Ambient Temperature +25°C Min. 100 Max. − Unit year Seiko Instruments Inc. 5 CMOS SPI 8K SERIAL E2PROM S-25C080A DC Electrical Characteristics Table 10 Item Symbol Condition No load at SO pin VCC = 1.6 to 2.5 V fSCK = 2.0 MHz Min. Max. − 1.5 VCC = 2.5 to 4.5 V fSCK = 5.0 MHz Min. Max. − 2.0 Rev.1.1_00 VCC = 4.5 to 5.5 V fSCK = 5.0 MHz Min. Max. − 2.5 Unit Current consumption (READ) ICC1 mA Table 11 Item Symbol Condition No load at SO pin VCC = 1.7 to 2.5 V fSCK = 2.0 MHz Min. Max. − 2.0 VCC = 2.5 to 4.5 V fSCK = 5.0 MHz Min. Max. − 2.5 VCC = 4.5 to 5.5 V fSCK = 5.0 MHz Min. Max. − 3.0 Unit Current consumption (WRITE) ICC2 mA Table 12 Item Symbol Condition VCC = 1.6 to 2.5 V Min. Max. VCC = 2.5 to 4.5 V Min. Max. VCC = 4.5 to 5.5 V Min. Max. Unit Standby current consumption Input leakage current Output leakage current Low level output voltage High level output voltage ISB ILI ILO VOL1 VOL2 VOH1 VOL2 CS = Vcc, SO = Open − Other inputs are VCC or GND VIN = GND to VCC − VOUT = GND to VCC − IOL = 2.0 mA − IOL = 1.5 mA − IOH = −2.0 mA − IOH = −0.4 mA 0.8 × VCC 1.5 1.0 1.0 − 0.4 − − − − − − − 0.8 × VCC 0.8 × VCC 1.5 1.0 1.0 0.4 0.4 − − − − − − − 0.8 × VCC 0.8 × VCC 1.5 1.0 1.0 0.4 0.4 − − µA µA µA V V V V 6 Seiko Instruments Inc. Rev.1.1_00 AC Electrical Characteristics CMOS SPI 8K SERIAL E2PROM S-25C080A Table 13 Measurement Conditions Input pulse voltage Output reference voltage Output load 0.2 × VCC to 0.8 × VCC 0.5 × VCC 100 pF Item SCK clock frequency CS setup time during CS falling CS setup time during CS rising CS deselect time CS hold time during CS falling CS hold time during CS rising SCK clock time “H” *1 SCK clock time “L” *1 Rising time of SCK clock *2 Falling time of SCK clock *2 SI data input setup time SI data input hold time SCK “L” hold time during HOLD rising SCL “L” hold time during HOLD falling SCK “H” setup time during HOLD falling SCK “H” setup time during HOLD rising Disable time of SO output *2 Delay time of SO output Hold time of SO output Rising time of SO output *2 Falling time of SO output *2 Disable time of SO output during HOLD falling *2 Delay time of SO output during HOLD rising *2 WP setup time WP hold time WP release / setup time WP release / hold time Symbol fSCK tCSS.CL tCSS.CH tCDS tCSH.CL tCSH.CH tHIGH tLOW tRSK tFSK tDS tDH tSKH.HH tSKH.HL tSKS.HL tSKS.HH tOZ tOD tOH tRO tFO tOZ.HL tOD.HH tWS1 tWH1 tWS2 tWH2 Table 14 VCC = 1.6 to 2.5 V Min. − 150 150 200 200 150 200 200 − − 50 60 150 100 150 150 − − 0 − − − − 0 0 0 60 Max. 2.0 − − − − − − − 1 1 − − − − − − 200 150 − 100 100 200 150 − − − − VCC = 2.5 to 4.5 V Min. − 90 90 90 90 90 90 90 − − 20 30 70 40 60 60 − − 0 − − − − 0 0 0 30 Max. 5.0 − − − − − − − 1 1 − − − − − − 100 70 − 40 40 100 50 − − − − VCC = 4.5 to 5.5 V Min. − 90 90 90 90 90 90 90 − − 20 30 70 40 60 60 − − 0 − − − − 0 0 0 30 Max. 5.0 − − − − − − − 1 1 − − − − − − 100 70 − 40 40 100 50 − − − − Unit MHz ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK µs. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. Seiko Instruments Inc. 7 CMOS SPI 8K SERIAL E2PROM S-25C080A Rev.1.1_00 Table 15 Item Write time Symbol tPR VCC = 1.7 to 5.5 V Min. Max. − 4.0 Unit ms tCDS CS tCSH.CL tCSS.CL SCK tDS tDH MSB IN tRSK LSB IN tFSK tCSH.CH tCSS.CH SI SO High-Z Figure 6 Serial input timing CS tSKS.HL tSKH.HL tSKH.HH SCK tSKS.HH SI tOZ.HL SO tOD.HH HOLD Figure 7 Hold timing 8 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A CS tSCK tHIGH tOZ SCK tLOW ADDR SI LSB IN tOD SO tRO tFO Figure 8 Serial output timing tOH tOD tOH LSB OUT tWS1 tWH1 CS WP Figure 9 Valid timing in Write protect tWS2 tWH2 CS WP Figure 10 Invalid timing in Write protect Seiko Instruments Inc. 9 CMOS SPI 8K SERIAL E2PROM S-25C080A Pin Functions 1. CS (Chip select input) Pin Rev.1.1_00 This is an input pin to set a chip in the select status. In the “H” input level, the device is in the non-select status and its output is high impedance. The device is in standby as long as it is not in Write inside. The device goes in active by setting the chip select to “L”. Input any instruction code after power-on and a falling of chip select. 2. SI (Serial data input) pin This pin is to input serial data. This pin receives an instruction code, an address and Write data. This pin latches data at rising edge of serial clock. 3. SO (Serial data output) pin This pin is to output serial data. The data output changes according to falling edge of serial clock. 4. SCK (Serial clock input) pin This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at a rising edge of clock. Data is output during falling edge of clock. 5. WP (Write protect input) pin Write protect is purposed to protect the area size against the Write instruction (BP1, BP0 in the status register). Fix this pin “H” or “L” not to set it in the floating state. Refer to “ Protect Operation” for details. 6. HOLD (HOLD input) pin This pin is used to pause serial communications without setting the device in the non-select status. In the hold status, the serial output goes in high impedance, the serial input and the serial clock go in “Don’t care”. During the hold operation, be sure to set the device in active by setting the chip select ( CS pin) to “L”. Refer to “ Hold Operation” for details. 10 Seiko Instruments Inc. Rev.1.1_00 Instruction Setting CMOS SPI 8K SERIAL E2PROM S-25C080A Table 16 is the list of instruction for the S-25C080A. The instruction is able to be input by changing the CS pin “H” to “L”. Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If the S25C080A receives any invalid instruction code, the device goes in the non-select status. Table 16 Instruction Operation Instruction code SCK input clock 1 to 8 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Address Data SCK input clock SCK input clock SCK input clock 9 to 16 17 to 24 25 to 32 − − − − − − b7 to b0 output *1 − − b7 to b0 input − − A15 to A8 *2 D7 to D0 output *3 A7 to A0 A15 to A8 *2 A7 to A0 D7 to D0 input WREN Write enable WRDI Write disable RDSR Read the status register WRSR Write in the status register READ Read memory data WRITE Write memory data *1. Sequential data reading is possible. *2. The higher addresses A15 to A10 = Don’t care. *3. After outputting data in the specified address, data in the following address is output. Seiko Instruments Inc. 11 CMOS SPI 8K SERIAL E2PROM S-25C080A Operation 1. Status register The status register’s organization is below. The status register can Write and Read by a specific instruction. b7 SRWD b6 0 b5 0 b4 0 b3 BP1 b2 BP0 b1 WEL b0 WIP Rev.1.1_00 Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress Figure 11 Organization of status register The status / control bits of the status register as follows. 1. 1 SRWD (b7) : Status Register Write Disable Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal WP (SRWD = ”1”, WP = ”L”), this device goes in Hardware Protect status. In this case, the bits composed of the nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be performed. 1. 2 BP1, BP0 (b3, b2) : Block Protect Bit BP1 and BP0 are composed of the nonvolatile bit. The area size of Software Protect against WRITE instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”. 1. 3 WEL (b1) : Write Enable Latch Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is “1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the device does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations; • • • • • the power supply voltage is dropping power-on after performing WRDI after the Write operation by the WRSR instruction has completed after the Write operation by the WRITE instruction has completed 1. 4 WIP (b0) : Write In Progress Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or WRSR instruction. Bit WIP is “1” during the Write operation but “0” during any other status. 12 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A 2. Write enable (WREN) Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit WEL. Its operation is below. After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”. CS WP High / Low SCK 1 2 3 4 5 6 7 8 Instruction SI SO High-Z Figure 12 WREN operation Seiko Instruments Inc. 13 CMOS SPI 8K SERIAL E2PROM S-25C080A Rev.1.1_00 3. Write disable (WRDI) The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”. Bit WEL is reset after the operations shown below. • • • • The power supply voltage is dropping and power-on After performing WRDI After the completion of Write operation by the WRSR instruction After the completion of Write operation by the WRITE instruction CS WP High / Low SCK 1 2 3 4 5 6 7 8 Instruction SI SO High-Z Figure 13 WRDI operation 14 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A 4. Read the status register (RDSR) Reading data in the status register is possible by the RDSR instruction. During the Write operation, it is possible to confirm the progress by checking bit WIP. Set the chip select ( CS ) “L” first. After that, input the instruction code from serial data input (SI). The status of bit in the status register is output from serial data output (SO). Sequential Read is available for the status register. To stop the Read cycle, set CS to “H”. It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write cycle. However, during the Write cycle in progress, the nonvolatile bits SRWD, BP1, BP0 are fixed in a certain value. These updated values of bit can be obtained by inputting another new RDSR instruction after the Write cycle has completed. Contrarily, two of Read Only bits WEL and WIP are being updated while the Write cycle is in progress. CS WP High / Low SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Instruction SI Outputs Data in the Status Register SO High-Z b7 b6 b5 b4 b3 b2 b1 b0 b7 Figure 14 RDSR operation Seiko Instruments Inc. 15 CMOS SPI 8K SERIAL E2PROM S-25C080A Rev.1.1_00 5. Write in the status register (WRSR) The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4, b1, b0 of status register cannot be rewritten. b6 to 4 are always data “0” when reading the status register. Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below. Set the chip select ( CS ) “L” first. After that, input the instruction code and data from serial data input (SI). To start WRSR Write (tPR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR Write. Bit WIP is “1” during Write, “0” during any other status. Bit WEL is reset when Write is completed. With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the Read Only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on the status of Write protect WP . With a combination of bit SRWD and Write protect WP , the device can be set in Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to “ Protect Operation”). Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly updated value is changed when the WRSR instruction has completed. To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in “L”. CS WP High / Low SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Instruction SI b7 Inputs Data in the Status Register b6 b5 b4 b3 b2 b1 b0 SO High-Z Figure 15 WRSR operation 16 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A 6. Read memory data (Read) The Read operation is shown below. Input the instruction code and the address from serial data input (SI) after inputting “L” to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the address is output from the serial data output (SO). Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in “L”, the address is automatically incremented so that data in the following address is sequentially output. The address counter rolls over to the first address by increment in the last address. To finish the Read cycle, set CS to “H”. It is possible to raise the chip select always during the cycle. During Write, the read instruction code is not be accepted or operated. CS WP High / Low SCK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 32 Instruction SI 16-bit Address A15 A14 A13 A3 A2 A1 A0 Outputs the First Byte Outputs the Second D7 SO High-Z D7 D6 D5 D4 D3 D2 D1 D0 Remark The higher addresses A15 to A10 = Don’t care. Figure 16 Read operation Seiko Instruments Inc. 17 CMOS SPI 8K SERIAL E2PROM S-25C080A Rev.1.1_00 7. Write memory data (Write) Figure 17 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data from serial data input (SI) after inputting “L” to the chip select ( CS ). To start Write (tPR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to “0” when Write has completed. The S-25C080A can Page Write of 32 bytes. Its function to transmit data is as same as Byte Write basically, but it operates Page Write by receiving sequential 8-bit Write data as much data as page size has. Input the instruction code, the address and data from serial data input (SI) after inputting “L” in CS , as the Write operation (page) shown in Figure 18. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit sequentially. At the end, by setting CS to “H”, the Write operation starts (tPR). 5 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus, even if Write data exceeds 32 bytes, the higher bits in the address do not change. And 5 of lower bits in the address roll over so that Write data which is previously input is overwritten. These are cases when the Write instruction is not accepted or operated. • Bit WEL is not set to “1” (not set to “1” beforehand immediately before the Write instruction) • During Write • The address to be written is in the protect area by BP1 and BP0. To cancel the Write instruction, input the clock different from a specified value (n = 24+m × 8clock) while CS is in “L”. CS WP High / Low SCK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 32 Instruction SI 16-bit Address A15 A14 A13 Data Byte 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SO High-Z Remark The higher addresses A15 to A10 = Don’t care. Figure 17 Write operation (1 byte) 18 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A CS WP 1 SCK Instruction SI 2 3 4 5 6 7 8 9 10 11 High / Low 22 23 24 25 26 27 28 29 30 31 32 16-bit Address (n) A15 A14 A13 Data Byte (n) Data Byte (n + x) D4 D3 D2 D1 D0 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SO High-Z Remark The higher addresses A15 to A10 = Don’t care. Figure 18 Write operation (Page) Seiko Instruments Inc. 19 CMOS SPI 8K SERIAL E2PROM S-25C080A Protect Operation Rev.1.1_00 Table 17 shows the block settings of Write protect. Table 18 shows the protect operation for the device. As long as bit SRWD, the Status Register Write Disable bit, in the status register is reset to “0” (it is in reset before the shipment), the value of status register can be changed. These are two statues when bit SRWD is set to “1”. • Write in the status register is possible; Write protect ( WP ) is in “H”. • Write in the status register is impossible; Write protect ( WP ) is in “L”. Therefore the Write protect area which is set by protect bit (BP1, BP0) in the status register cannot be changed. These operations are to set Hardware Protect (HPM). • After setting bit SRWD, set Write protect ( WP ) to “L”. • Set bit SRWD completed setting Write protect ( WP ) to “L”. Figure 9 and 10 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the status register. By inputting “H” to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is “H”, Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status register (BP1, BP0) only works. Table 17 The block settings of Write protect Status register BP1 0 0 1 1 BP0 0 1 0 1 The area of Write protect 0% 25 % 50 % 100 % Table 18 Protect operation Mode WP pin Address of Write protect block None 300h to 3FFh 200h to 3FFh 000h to 3FFh Bit SRWD X X 0 0 1 1 Bit WEL 0 1 0 1 0 1 Write protect block Write disable Write disable Write disable Write disable Write disable Write disable General block Write disable Write enable Write disable Write enable Write disable Write enable Status register Write disable Write enable Write disable Write enable Write disable Write disable Software Protect (SPM) Hardware Protect (HPM) Remark X = Don’t care 1 1 X X 0 0 20 Seiko Instruments Inc. Rev.1.1_00 Hold Operation CMOS SPI 8K SERIAL E2PROM S-25C080A The hold operation is used to pause serial communications without setting the device in the non-select status. In the hold status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in “Don’t care”. Be sure to set the chip select ( CS ) to “L” to set the device in the select status during the hold status. Generally, during the hold status, the device holds the select status. But if setting the device in the non-select status, the users can finish the operation even in progress. Figure 19 shows the hold operation. Set Hold ( HOLD ) to “L” when the serial clock (SCK) is in “L”, Hold ( HOLD ) is switched at the same time the hold status starts. If setting Hold ( HOLD ) to “H”, Hold ( HOLD ) is switched at the same time the hold status ends. Set Hold ( HOLD ) to “L” when the serial clock (SCK) is in “H”; the hold status starts when the serial clock goes in “L” after Hold ( HOLD ) is switched. If setting Hold ( HOLD ) to “H”, the hold status ends when the serial clock goes in “L” after Hold ( HOLD ) is switched. Hold status Hold status SCK HOLD Figure 19 Hold operation Seiko Instruments Inc. 21 CMOS SPI 8K SERIAL E2PROM S-25C080A Write Protect Function during the Low Power Supply Voltage Rev.1.1_00 The S-25C080A has a built-in detection circuit which operates with the low power supply voltage. The S-25C080A cancels the Write operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time, goes in the Write protect status (WRDI) automatically to reset bit WEL. Its detection and release voltages are 1.20 V typ. (Refer to Figure 20). To operate Write, after the power supply voltage dropped once but rose to the voltage level which allows Write again, be sure to set the Write Enable Latch bit (WEL) before operating Write (WRITE, WRSR). In the Write operation, data in the address written during the low power supply voltage is not assured. Power supply voltage Detection voltage (−VDET) 1.20 V Typ. Release voltage (+VDET) 1.20 V Typ. Cancel the Write instruction Set in Write protect (WRDI) automatically Figure 20 Operation during low power supply voltage I/O Pin 1. Connection of input pin All input pins in S-25C080A have the CMOS structure. Do not set these pins in high impedance during operation when you design. Especially, set the CS input in the non-select status “H” during power-on/off and standby. The error Write does not occur as long as the CS pin is in the non-select status “H”. Set the CS pin to VCC via a resistor (the pull-up resistor of 10 to 100 kΩ. To prevent the error for sure, it is recommended to set other input pins than the CS pin via a pull-up resistor. 2. Equivalent circuit of I/O pin Figure 21 and 22 show the equivalent circuits of input pins in S-25C080A. A pull-up and pull-down elements are not included in each input pin, pay attention not to set it in the floating state when you design. Figure 23 shows the equivalent circuit of the output pin. This pin has the tri-state output of “H” level/“L” level/high impedance. 22 Seiko Instruments Inc. Rev.1.1_00 CMOS SPI 8K SERIAL E2PROM S-25C080A 2. 1 Input pin CS, SCK Figure 21 CS , SCK Pin SI, WP, HOLD Figure 22 SI, WP , HOLD Pin 2. 2 Output pin VCC SO Figure 23 SO Pin 3. Precaution for use ● Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the data sheet). Exceeding the supply voltage rating can cause latch-up. Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking the E2PROM up from low temperature tank during the evaluation. Be sure that not remain frost on the E2PROM pin to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason. ● Seiko Instruments Inc. 23 CMOS SPI 8K SERIAL E2PROM S-25C080A Precautions Rev.1.1_00 ● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ● SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party. Precautions for WLP package ● The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of the handing of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, and needs to be kept out of contact with the external potential. ● In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it may affect the characteristic of a device when exposed a device in the bottom of a high light source. 24 Seiko Instruments Inc. Rev.1.1_00 Product Name Structure 1. 8-Pin SOP(JEDEC), 8-Pin TSSOP, SNT-8A Packages S-25C080A 0I − xxxx G CMOS SPI 8K SERIAL E2PROM S-25C080A Package name (abbreviation) and IC packing specification I8T1: SNT-8A, Tape J8T1: 8-Pin SOP (JEDEC) , Tape T8T1: 8-Pin TSSOP, Tape Fixed Product name S-25C080A : 8K-bit 2. WLP-8H Package S-25C080A 0I − xxxx Package name (abbreviation) and IC packing specification H8T3: WLP-8H, Tape Fixed Product name S-25C080A : 8K-bit Seiko Instruments Inc. 25 5.02±0.2 8 5 1 4 0.20±0.05 1.27 0.4±0.05 No. FJ008-A-P-SD-2.1 TITLE No. SCALE UNIT SOP8J-D-PKG Dimensions FJ008-A-P-SD-2.1 mm Seiko Instruments Inc. 2.0±0.05 ø1.55±0.05 4.0±0.1(10 pitches:40.0±0.2) 0.3±0.05 ø2.0±0.05 5°max. 8.0±0.1 2.1±0.1 6.7±0.1 1 8 4 5 Feed direction No. FJ008-D-C-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Carrier Tape FJ008-D-C-SD-1.1 mm Seiko Instruments Inc. 60° 2±0.5 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 13.5±0.5 No. FJ008-D-R-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Reel FJ008-D-R-SD-1.1 QTY. mm 2,000 Seiko Instruments Inc. 3.00 -0.2 8 5 +0.3 1 4 0.17±0.05 0.2±0.1 0.65 No. FT008-A-P-SD-1.1 TITLE No. SCALE UNIT TSSOP8-E-PKG Dimensions FT008-A-P-SD-1.1 mm Seiko Instruments Inc. 4.0±0.1 2.0±0.05 ø1.55±0.05 0.3±0.05 8.0±0.1 ø1.55 -0.05 +0.1 (4.4) 6.6 -0.2 +0.4 1 8 4 5 Feed direction No. FT008-E-C-SD-1.0 TITLE No. SCALE UNIT TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0 mm Seiko Instruments Inc. 13.4±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.5 17.5±1.0 No. FT008-E-R-SD-1.0 TITLE No. SCALE UNIT mm TSSOP8-E-Reel FT008-E-R-SD-1.0 QTY. 3,000 Seiko Instruments Inc. 1 .97±0.03 8 7 6 5 1 0.5 2 3 4 0.08 -0.02 +0.05 0.48±0.02 0.2±0.05 No. PH008-A-P-SD-2.0 TITLE No. SCALE UNIT SNT-8A-A-PKG Dimensions PH008-A-P-SD-2.0 mm Seiko Instruments Inc. ø1.5 -0 +0.1 2.0±0.05 4.0±0.1 0.25±0.05 5° 2.25±0.05 ø0.5±0.1 4.0±0.1 0.65±0.05 4 321 5 6 78 Feed direction No. PH008-A-C-SD-1.0 TITLE No. SCALE UNIT SNT-8A-A-Carrier Tape PH008-A-C-SD-1.0 mm Seiko Instruments Inc. 12.5max. Enlarged drawing in the central part ø13±0.2 9.0±0.3 (60°) (60°) No. PH008-A-R-SD-1.0 TITLE No. SCALE UNIT mm SNT-8A-A-Reel PH008-A-R-SD-1.0 QTY. 5,000 Seiko Instruments Inc. 0.52 2.01 0.52 0.3 0.2 0.3 0.2 0.3 0.2 0.3 Caution Making the wire pattern under the package is possible. However, note that the package may be upraised due to the thickness made by the silk screen printing and of a solder resist on the pattern because this package does not have the standoff. No. PH008-A-L-SD-3.0 TITLE No. SCALE UNIT SNT-8A-A-Land Recommendation PH008-A-L-SD-3.0 mm Seiko Instruments Inc. 1 .67±0.02 0.39max. 0.265±0.025 S 0.04 S ø0.25±0.02 0.08±0.02 A B B C D E 8-(ø0.25) 1 2 0.8 3 0.6 No. HH008-A-P-SD-1.0 WLP-8H-A-PKG Dimensions HH008-A-P-SD-1.0 mm TITLE No. SCALE UNIT Seiko Instruments Inc. ø1.5 -0 +0.1 2.0±0.05 4.0±0.1 0.18±0.05 ø0.50±0.05 2.0±0.1 4.0±0.1 0.55±0.05 2.06 0.82 0.22 0.62 1.76±0.05 E1 C1 A1 E3 C3 A3 Feed direction No. HH008-A-C-SD-1.0 TITLE No. SCALE UNIT WLP-8H-A-C a r r i e r T a p e HH008-A-C-SD-1.0 Seiko Instruments Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 No. HH008-A-R-SD-1.0 TITLE No. SCALE UNIT WLP-8H-A-Reel HH008-A-R-SD-1.0 QTY. mm 3,000 Seiko Instruments Inc. • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.