S-25CM01A
SPI SERIAL E2PROM
www.ablic.com
ww.ablicinc.com
Rev.2.2_03_S
© ABLIC Inc., 2010-2015
The S-25CM01A is a SPI serial E2PROM which operates at high speed, with low current consumption and the wide range
operation. The S-25CM01A has the capacity of 1 M-bit and the organization of 131072 words 8-bit. Page write and
sequential read are available.
Features
Operating voltage range:
Read
1.6 V to 5.5 V
Write
1.7 V to 5.5 V
10.0 MHz (VCC = 2.5 V to 5.5 V)
5.0 ms max.
Operation frequency:
Write time:
SPI mode (0, 0) and (1, 1)
Page write:
256 bytes / page
Sequential read
Write protect:
Software, Hardware
Protect area:
25%, 50%, 100%
Monitors write to the memory by a status register
Function to prevent malfunction by monitoring clock pulse
Write protect function during the low power supply voltage
CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
Endurance:
106cycles / unit*1 (Ta = 25°C)
Data retention:
100 years (Ta = 25°C)
Memory capacity:
1 M-bit
Initial delivery state:
FFh, SRWD = 0, BP1 = 0, BP0 = 0
Operation temperature range:
Ta = 40°C to 85C
Lead-free (Sn 100%), halogen-free*2
*1. For each unit (unit: the 4 bytes with the same address of A16 to A2)
*2. Refer to " Product Name Structure" for details.
Package
8-Pin SOP (JEDEC)
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to
ABLIC Inc. is indispensable.
1
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Pin Configuration
1. 8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC)
Top view
Table 1
Pin No.
1
8
2
7
3
6
4
5
Figure 1
S-25CM01A0I-J8T1U4
1
CS
*1
Description
Chip select input
2
SO
Serial data output
3
4
5
6
WP *1
GND
*1
SI
*1
SCK
Ground
Serial data input
Serial clock input
7
HOLD *1
Write protect input
Hold input
8
VCC
Power supply
*1. Do not use it in high impedance.
Remark Refer to "Package drawings" for details.
2
Symbol
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Block Diagram
Step-up Circuit
Voltage Detector
SCK
SI
HOLD
WP
Clock Counter
Mode
Decoder
Data Register
Address Register
Output
Control
Circuit
SO
Status Register
X Decoder
Input Control Circuit
CS
Page Latch
Memory
Cell
Array
Status
Memory Cell Array
Y Decoder
Read Circuit
VCC
GND
Figure 2
3
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Absolute Maximum Ratings
Table 2
Item
Symbol
Absolute Maximum Rating
Unit
Power supply voltage
VCC
0.3 to 6.5
V
Input voltage
VIN
0.3 to 6.5
V
Output voltage
VOUT
0.3 to VCC 0.3
V
Operation ambient temperature
Topr
40 to 85
°C
Storage temperature
Tstg
65 to 150
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 3
Item
Symbol
Power supply voltage
VCC
High level input voltage
VIH
Low level input voltage
VIL
Condition
Read Operation
Write Operation
VCC = 1.8 V to 5.5 V
VCC = 1.6 V to 1.8 V
VCC = 1.8 V to 5.5 V
VCC = 1.6 V to 1.8 V
Ta = 40C to 85C
Min.
Max.
Unit
1.6
1.7
5.5
5.5
0.7 VCC
0.8 VCC
0.3
0.3
VCC 1.0
VCC 1.0
0.3 VCC
0.2 VCC
V
V
V
V
V
V
Pin Capacitance
Table 4
Item
Input capacitance
Output capacitance
Symbol
Condition
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
CIN
VIN = 0 V ( CS , SCK, SI, WP , HOLD )
8
pF
COUT
VOUT = 0 V (SO)
10
pF
Endurance
Table 5
Item
Symbol
Operation Ambient Temperature
Endurance
NW
Ta = 25°C
*1. For each unit (unit: the 4 bytes with the same address of A16 to A2)
Min.
106
Max.
Unit
cycles / unit*1
Min.
100
Max.
Unit
year
Data Retention
Table 6
Item
Data retention
4
Symbol
Operation Ambient Temperature
Ta = 25°C
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
DC Electrical Characteristics
Table 7
Item
Current consumption (READ)
Ta = 40C to 85C
VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V
Symbol Condition
Unit
fSCK = 2.0 MHz
fSCK = 5.0 MHz
fSCK = 10.0 MHz
Min.
Max.
Min.
Max.
Min.
Max.
No load at
2.5
2.5
4.0
mA
ICC1
SO pin
Table 8
Item
Current consumption (WRITE)
Ta = 40C to 85C
VCC = 1.7 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V
Symbol Condition
Unit
fSCK = 2.0 MHz
fSCK = 5.0 MHz
fSCK = 10.0 MHz
Min.
Max.
Min.
Max.
Min.
Max.
No load at
4.0
4.0
4.0
mA
ICC2
SO pin
Table 9
Ta = 40C to 85C
Item
Symbol
Condition
VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V Unit
Min.
Standby current
consumption
Input leakage current
Output leakage current
Low level
output voltage
High level
output voltage
ISB
ILI
ILO
VOL1
VOL2
VOH1
VOH2
CS = VCC,
SO = Open
Other inputs are
VCC or GND
VIN = GND to VCC
VOUT = GND to VCC
IOL = 2.0 mA
IOL = 1.5 mA
IOH = 2.0 mA
IOH = 0.4 mA
0.8 VCC
Max.
Min.
Max.
Min.
Max.
3.0
4.0
10.0
A
1.0
1.0
0.4
0.8 VCC
0.8 VCC
1.0
1.0
0.4
0.4
0.8 VCC
0.8 VCC
1.0
1.0
0.4
0.4
A
A
V
V
V
V
5
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
AC Electrical Characteristics
Table 10 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 VCC to 0.8 VCC
0.5 VCC
100 pF
Table 11
Item
Symbol
SCK clock frequency
fSCK
VCC = 1.6 V to 1.8 V
Min.
Max.
2.0
Ta = 40C to 85C
VCC = 1.8 V to 2.5 V
Min.
Max.
5.0
VCC = 2.5 V to 5.5 V
Min.
Max.
10.0
Unit
MHz
CS setup time during CS falling tCSS.CL
150
90
30
ns
CS setup time during CS rising
tCSS.CH
150
90
30
ns
CS deselect time
tCDS
200
90
40
ns
CS hold time during CS falling
tCSH.CL
200
90
30
ns
CS hold time during CS rising
tCSH.CH
150
90
30
ns
tHIGH
tLOW
tRSK
tFSK
tDS
tDH
200
200
50
60
1
1
90
90
20
30
1
1
40
40
10
10
1
1
ns
ns
s
s
ns
ns
tSKH.HH
150
70
30
ns
tSKH.HL
100
40
30
ns
tSKS.HL
0
0
0
ns
tSKS.HH
0
0
0
ns
tOZ
tOD
tOH
tRO
tFO
0
200
150
100
100
0
100
70
40
40
0
40
40
40
40
ns
ns
ns
ns
ns
tOZ.HL
200
100
40
ns
tOD.HH
150
50
40
ns
WP setup time
tWS1
0
0
0
ns
WP hold time
tWH1
0
0
0
ns
WP release / setup time
tWS2
0
0
0
ns
*1
SCK clock time "H"
SCK clock time "L" *1
Rising time of SCK clock *2
Falling time of SCK clock *2
SI data input setup time
SI data input hold time
SCK "L" hold time
during HOLD rising
SCK "L" hold time
during HOLD falling
SCK "L" setup time
during HOLD falling
SCK "L" setup time
during HOLD rising
Disable time of SO output *2
Delay time of SO output
Hold time of SO output
Rising time of SO output *2
Falling time of SO output *2
Disable time of SO output
during HOLD falling *2
Delay time of SO output
during HOLD rising *2
60
30
30
ns
tWH2
WP release / hold time
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
6
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Table 12
Item
Write time
Symbol
tPR
Ta = 40C to 85C
VCC = 1.7 V to 5.5 V
Min.
Max.
5.0
Unit
ms
tCDS
CS
tCSH.CL
tCSS.CH
tCSH.CH
tCSS.CL
SCK
tDS
SI
SO
tDH
tRSK
MSB IN
tFSK
LSB IN
High-Z
Figure 3 Serial Input Timing
CS
tSKS.HL
tSKH.HL
tSKH.HH
SCK
tSKS.HH
SI
tOZ.HL
tOD.HH
SO
HOLD
Figure 4 Hold Timing
7
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
tSCK
CS
tOZ
tHIGH
SCK
tLOW
ADDR
SI LSB IN
tOD
tOH
tOD
tOH
SO
LSB OUT
tRO
tFO
Figure 5 Serial Output Timing
tWS1
tWH1
CS
WP
Figure 6 Valid Timing in Write Protect
tWS2
tWH2
CS
WP
Figure 7 Invalid Timing in Write Protect
8
Rev.2.2_03_S
SPI SERIAL E2PROM
S-25CM01A
Pin Functions
1. CS (Chip select input) pin
This is an input pin to set a chip in the select status. In the "H" input level, the device is in the non-select status and its
output is high impedance. The device is in standby as long as it is not in Write inside. The device goes in active by
setting the chip select to "L". Input any instruction code after power-on and a falling of chip select.
2. SI (Serial data input) pin
This pin is to input serial data. This pin receives an instruction code, an address and Write data. This pin latches data
at rising edge of serial clock.
3. SO (Serial data output) pin
This pin is to output serial data. The data output changes according to falling edge of serial clock.
4. SCK (Serial clock input) pin
This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at
a rising edge of clock. Data is output during falling edge of clock.
5. WP (Write protect input) pin
Write protect is purposed to protect the area size against the Write instruction (BP1, BP0 in the status register). Fix
this pin "H" or "L" not to set it in the floating state.
Refer to " Protect Operation" for details.
6. HOLD (HOLD input) pin
This pin is used to pause serial communications without setting the device in the non-select status.
In the hold status, the serial output goes in high impedance, the serial input and the serial clock go in "Don’t care".
During the hold operation, be sure to set the device in active by setting the chip select ( CS pin) to "L".
Refer to " Hold Operation" for details.
Initial Delivery State
Initial delivery state of all addresses is "FFh".
Moreover, initial delivery state of the status register nonvolatile memory is as follows.
SRWD = 0
BP1 = 0
BP0 = 0
ECC Function (Error correction function)
S-25CM01A Series adds 6 ECC bits for error correction to each 4 bytes with the same address of A16 to A2. The ECC
function can make correction and output correct data even if wrong data of 1 bit is in the 4 bytes when reading.
In addition, the S-25CM01A Series rewrites the 4 bytes used as the rewriting minimum unit and 6 ECC bits if only 1 byte
data is input.
Therefore, it is recommended to rewrite data of each 4 bytes with the same address of A16 to A2 in order to get the
maximum endurance in the application in which the data is rewrote frequently.
9
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Instruction Set
Table 13 is the list of instruction for the S-25CM01A. The instruction is able to be input by changing the CS pin "H" to
"L". Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If the S25CM01A receives any invalid instruction code, the device goes in the non-select status.
Table 13 Instruction Set
Instruction
Operation
Instruction Code
Address
Data
SCK Input Clock SCK Input Clock SCK Input Clock SCK Input Clock SCK Input Clock
1 to 8
9 to 16
17 to 24
25 to 32
33 to 40
Write enable
0000 0110
Write disable
0000 0100
Read the status
*1
b7 to b0 output
0000 0101
RDSR
register
Write in the status
0000 0001
b7 to b0 input
WRSR
register
A23 to A16 *2
READ
Read memory data
0000 0011
A15 to A8
A23 to A16 *2
WRITE
Write memory data
0000 0010
A15 to A8
*1. Sequential data reading is possible.
*2. The higher addresses A23 to A17 = Don’t care.
*3. After outputting data in the specified address, data in the following address is output.
WREN
WRDI
10
A7 to A0
A7 to A0
D7 to D0 output *3
D7 to D0 input
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect
Write Enable Latch
Write In Progress
Figure 8 Organization of Status Register
The status / control bits of the status register as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = "1", WP = "L"), this device goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be
performed.
1. 2 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area
against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1 and BP0 is possible
unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of "Block Protect".
1. 3 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
"1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that the
device does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
The power supply voltage is dropping
Power-on
After performing WRDI
After the Write operation by the WRSR instruction has completed
After the Write operation by the WRITE instruction has completed
11
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
1. 4 WIP (b0) : Write In Progress
Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or
WRSR instruction. Bit WIP is "1" during the Write operation but "0" during any other status. Figure 9 shows the
usage example.
CS
WRITE or WRSR instruction
RDSR instruction
SI
D2 D1 D0
RDSR
RDSR instruction
RDSR
S
R
W
D
SO
RDSR instruction
S
R
W
D
BB
PP
1 0
000
RDSR
000
11
S
R
W
D
BB
PP
1 0
11
WEL, WIP
WEL, WIP
tPR
Figure 9 Usage Example of WEL, WIP Bits during Write
12
BB
PP
1 0
000
WEL, WIP
00
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
2. Write enable (WREN)
Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit WEL.
Its operation is below.
After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL,
set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN
instruction, input the clock different from a specified value (n = 8 clocks) while CS is in "L".
CS
WP
SCK
High / Low
1
2
3
4
5
6
7
8
Instruction
SI
SO
High-Z
Figure 10 WREN Operation
13
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
3. Write disable (WRDI)
The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select
( CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock.
To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clocks) while CS is in "L". Bit
WEL is reset after the operations shown below.
The power supply voltage is dropping
Power-on
After performing WRDI
After the completion of Write operation by the WRSR instruction
After the completion of Write operation by the WRITE instruction
CS
WP
SCK
High / Low
1
2
3
4
5
Instruction
SI
SO
High-Z
Figure 11 WRDI Operation
14
6
7
8
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
4. Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the Write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit in the
status register is output from serial data output (SO). Sequential Read is available for the status register. To stop the
Read cycle, set CS to "H".
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits SRWD, BP1 and BP0 can be
acquired by performing a new RDSR instruction after verifying the completion of the write cycle.
CS
WP
SCK
High / Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Instruction
SI
Outputs Data in the Status Register
SO
High-Z
b7
b6
b5
b4
b3
b2
b1
b0
b7
Figure 12 RDSR Operation
15
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
5. Write in the status register (WRSR)
The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4, b1,
b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below.
Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start
WRSR Write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial clock.
It is possible to confirm the operation status by reading the value of bit WIP during WRSR Write. Bit WIP is "1" during
Write, "0" during any other status. Bit WEL is reset when Write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the
Read Only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on
the status of Write protect WP . With a combination of bit SRWD and Write protect WP , the device can be set in
Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to " Protect
Operation").
Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction.
The newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clocks) while CS is in "L".
CS
WP
SCK
High / Low
1
2
3
4
5
6
7
8
9
Instruction
SO
b6
High-Z
Figure 13 WRSR Operation
16
11
12
13
14
15
16
Inputs Data in the Status Register
b7
SI
10
b5
b4
b3
b2
b1
b0
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
6. Read memory data (READ)
The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after
inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the
address is output from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in "L", the address is automatically incremented
so that data in the following address is sequentially output. The address counter rolls over to the first address by
increment in the last address.
To finish the Read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During Write, the
READ instruction code is not be accepted or operated.
CS
WP
SCK
High / Low
1
2
3
4
5
6
Instruction
7
8
9
10
11
30
31
32
33
34
35
36
37
38
39
40
24-bit Address
A23 A22 A21
SI
29
A3 A2 A1 A0
Outputs the First Byte
SO
High-Z
D7
D6 D5 D4 D3 D2 D1 D0
Outputs
the Second
D7
Remark The higher addresses A23 to A17 = Don’t care.
Figure 14 READ Operation
17
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
7. Write memory data (WRITE)
Figure 15 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data from
serial data input (SI) after inputting "L" to the chip select ( CS ). To start WRITE (tPR), set the chip select ( CS ) to "H"
after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to "0" when Write has
completed.
The S-25CM01A can Page Write of 256 bytes. Its function to transmit data is as same as Byte Write basically, but it
operates Page Write by receiving sequential 8-bit Write data as much data as page size has. Input the instruction
code, the address and data from serial data input (SI) after inputting "L" in CS , as the WRITE operation (page) shown
in Figure 16. Input the next data while keeping CS in "L". After that, repeat inputting data of 8-bit sequentially. At the
end, by setting CS to "H", the WRITE operation starts (tPR).
8 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus,
even if Write data exceeds 256 bytes, the higher bits in the address do not change. And 8 of lower bits in the address
roll over so that Write data which is previously input is overwritten.
These are cases when the WRITE instruction is not accepted or operated.
Bit WEL is not set to "1" (not set to "1" beforehand immediately before the WRITE instruction)
During Write
The address to be written is in the protect area by BP1 and BP0.
To cancel the WRITE instruction, input the clock different from a specified value (n = 32+m 8 clocks) while CS is in "L".
CS
WP
SCK
High / Low
1
2
3
4
5
6
Instruction
8
9
10
11
29
30
31
32
24-bit Address
A23 A22 A21
SI
SO
7
34
35
36
37
38
39
40
Data Byte 1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
High-Z
Remark The higher addresses A23 to A17 = Don’t care.
Figure 15 WRITE Operation (1 Byte)
18
33
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
CS
WP
High / Low
1
2
3
4
5
6
7
8
9
10 11
30 31 32 33 34 35 36 37 38 39 40
SCK
Instruction
SI
SO
Data Byte (n)
24-bit Address (n)
A23 A22 A21
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte (n + x)
D4 D3 D2 D1 D0
High-Z
Remark The higher addresses A23 to A17 = Don’t care.
Figure 16 WRITE Operation (Page)
19
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Protect Operation
Table 14 shows the block settings of Write protect. Table 15 shows the protect operation for the device. As long as bit
SRWD, the Status Register Write Disable bit, in the status register is reset to "0" (it is in reset before the shipment), the
value of status register can be changed.
These are two statues when bit SRWD is set to "1".
Write in the status register is possible; Write protect ( WP ) is in "H".
Write in the status register is impossible; Write protect ( WP ) is in "L". Therefore the Write protect area which is set
by protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
After setting bit SRWD, set Write protect ( WP ) to "L".
Set bit SRWD completed setting Write protect ( WP ) to "L".
Figure 6 and 7 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the
status register.
By inputting "H" to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is "H",
Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status
register (BP1, BP0) only works.
Table 14 Block Settings of Write Protect
Status Register
BP1
0
0
1
1
BP0
0
1
0
1
Area of Write Protect
Address of Write Protect Block
0%
25%
50%
100%
None
18000h to 1FFFFh
10000h to 1FFFFh
00000h to 1FFFFh
Table 15 Protect Operation
Mode
Software Protect
(SPM)
Hardware Protect
(HPM)
Remark X = Don’t care
20
WP Pin
Bit SRWD
Bit WEL
Write Protect Block
General Block
Status Register
1
1
X
X
0
0
X
X
0
0
1
1
0
1
0
1
0
1
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write disable
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Hold Operation
The hold operation is used to pause serial communications without setting the device in the non-select status. In the
hold status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in
"Don’t care". Be sure to set the chip select ( CS ) to "L" to set the device in the select status during the hold status.
Generally, during the hold status, the device holds the select status. But if setting the device in the non-select status,
the users can finish the operation even in progress.
Figure 17 shows the hold operation. Set Hold ( HOLD ) to "L" when the serial clock (SCK) is in "L", Hold ( HOLD ) is
switched at the same time the hold status starts. If setting Hold ( HOLD ) to "H", Hold ( HOLD ) is switched at the same
time the hold status ends.
Set Hold ( HOLD ) to "L" when the serial clock (SCK) is in "H"; the hold status starts when the serial clock goes in "L"
after Hold ( HOLD ) is switched. If setting Hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L"
after Hold ( HOLD ) is switched.
Hold status
Hold status
SCK
HOLD
Figure 17 Hold Operation
21
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Write Protect Function during the Low Power Supply Voltage
The S-25CM01A has a built-in detection circuit which operates with the low power supply voltage. The S-25CM01A
cancels the Write operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time,
goes in the Write protect status (WRDI) automatically to reset bit WEL. Its detection and release voltages are 1.50 V
typ. (Refer to Figure 18).
To operate Write, after the power supply voltage dropped once but rose to the voltage level which allows Write again,
be sure to set the Write Enable Latch bit (WEL) before operating Write (WRITE, WRSR).
In the Write operation, data in the address written during the low power supply voltage is not assured.
Power supply voltage
Detection voltage (−VDET)
1.50 V typ.
Release voltage (+VDET)
1.50 V typ.
Cancel the Write instruction
Set in Write protect (WRDI) automatically
Figure 18 Operation during Low Power Supply Voltage
Input Pin and Output Pin
1. Connection of input pin
All input pins in the S-25CM01A have the CMOS structure. Do not set these pins in high impedance during operation
when you design. Especially, set the CS input in the non-select status "H" during power-on/off and standby. The error
Write does not occur as long as the CS pin is in the non-select status "H". Set the CS pin to VCC via a resistor (the
pull-up resistor of 10 k to 100 k).
If the CS pin and the SCK pin change from "L" to "H" simultaneously, data may be input from the SI pin.
To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to
pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting the
WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.
2. Equivalent circuit of input pin and output pin
Figure 19 and 20 show the equivalent circuits of input pins in the S-25CM01A. A pull-up and pull-down elements are
not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 21 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" level / "L" level / high
impedance.
22
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
2. 1 Input pin
CS, SCK
Figure 19 CS , SCK Pin
SI, WP, HOLD
Figure 20 SI, WP , HOLD Pin
2. 2 Output pin
VCC
SO
Figure 21 SO Pin
3. Precautions for use
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the
detailed operation condition in the data sheet.
Operations with moisture on the S-25CM01A pins may occur malfunction by short-circuit between pins. Especially,
in occasions like picking the S-25CM01A up from low temperature tank during the evaluation. Be sure that not
remain frost on the S-25CM01A’s pins to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
23
SPI SERIAL E2PROM
S-25CM01A
Rev.2.2_03_S
Precautions
Set a by-pass capacitor of about 0.1 F between the VCC and GND pin for stabilization.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
Product Name Structure
1. Product name
S-25CM01A 0I
-
J8T1
U
4
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification
J8T1: 8-Pin SOP (JEDEC), Tape
Fixed
Product name
S-25CM01A : 1 M-bit
2. Package
Package Name
8-Pin SOP (JEDEC)
24
Package
FJ008-Z-P-SD
Drawing Code
Tape
FJ008-Z-C-SD
Reel
FJ008-Z-R-SD
+0.20
5.02 -0.35
8
5
1
4
1.27
0.20±0.05
+0.11
0.4 -0.07
No. FJ008-Z-P-SD-2.1
TITLE
SOP8J-Z-PKG Dimensions
FJ008-Z-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø1.5 min.
8.0±0.1
2.1±0.1
+0.30
6.5 -0.25
1
8
4
5
Feed direction
No. FJ008-Z-C-SD-1.0
TITLE
SOP8J-Z-Carrier Tape
No.
FJ008-Z-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
17.5±1.5
13.4±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-Z-R-SD-1.0
TITLE
SOP8J-Z-Reel
No.
FJ008-Z-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
工商网监
湘ICP备2023018690号
