S-35390A
www.ablic.com
2-WIRE REAL-TIME CLOCK
© ABLIC Inc., 2004-2018
Rev.4.2_04
The S-35390A is a CMOS 2-wire real-time clock IC which operates with the very low current consumption in the wide range of
operation voltage. The operation voltage is 1.3 V to 5.5 V so that the S-35390A can be used for various power supplies from
main supply to backup battery. Due to the 0.25 A current consumption and wide range of power supply voltage at time
keeping, the S-35390A makes the battery life longer. In the system which operates with a backup battery, the included free
registers can be used as the function for user's backup memory. Users always can take back the information in the registers
which is stored before power-off the main power supply, after the voltage is restored.
The S-35390A has the function to correct advance / delay of the clock data speed, in the wide range, which is caused by the
crystal oscillation circuit's frequency deviation. Correcting according to the temperature change by combining this function
and a temperature sensor, it is possible to make a high precise clock function which is not affected by the ambient
temperature.
Features
Low current consumption:
0.25 A typ. (VDD = 3.0 V, Ta = 25C)
Wide range of operating voltage:
1.3 V to 5.5 V
Built-in clock correction function
Built-in free user register
2-wire (I2C-bus) CPU interface
Built-in alarm interrupter
Built-in flag generator during detection of low power voltage or at power-on
Auto calendar up to the year 2099, automatic leap year calculation function
Built-in constant voltage circuit
Built-in 32.768 kHz crystal oscillation circuit (built-in Cd, external Cg)
*1
Lead-free, Sn 100%, halogen-free
*1. Refer to " Product Name Structure" for details.
Applications
Mobile game device
Mobile AV device
Digital still camera
Digital video camera
Electronic power meter
DVD recorder
TV, VCR
Mobile phone, PHS
Packages
8-Pin SOP (JEDEC)
8-Pin TSSOP
SNT-8A
1
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Block Diagram
XIN
XOUT
Oscillation
circuit
Divider,
timing generator
INT1
INT1 register
controller
Comparator 1
Clock correction register
Status register 1
INT1
Real-time data register
Day of
Second Minute Hour
Day Month Year
the week
Status register 2
Comparator 2
Free register
VDD
Low power supply
voltage detector
Power-on
detection circuit
INT2 register
INT2
controller
Shift register
Constant-voltage
circuit
VSS
Figure 1
2
INT2
Serial
interface
SDA
SCL
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Product Name Structure
1. Product name
1. 1
8-Pin SOP (JEDEC), 8-Pin TSSOP
S-35390A -
xxxx
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office)
Package name (abbreviation) and IC packing specification*1
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
Product name
*1.
1. 2
Refer to the tape drawing.
SNT-8A
S-35390A -
I8T1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
I8T1: SNT-8A, Tape
Product name
*1.
Refer to the tape drawing.
2. Packages
Table 1
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
SNT-8A
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
Package Drawing Codes
Dimension
Tape
Reel
Land
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
PH008-A-P-SD
FJ008-D-C-SD
FJ008-D-C-SD
FT008-E-C-SD
FT008-E-C-SD
PH008-A-C-SD
FJ008-D-R-SD
FJ008-D-R-S1
FT008-E-R-SD
FT008-E-R-S1
PH008-A-R-SD
PH008-A-L-SD
3
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Pin Configurations
Table 2
1. 8-Pin SOP (JEDEC)
Pin No
Top view
1
8
2
7
3
6
4
5
Figure 2
S-35390A-J8T1x
2. 8-Pin TSSOP
Top view
1
2
3
4
Symbol
Description
List of Pins
I/O
Output pin for
interrupt signal 1
Output
Connection pins
for quartz crystal
1
INT 1
2
XOUT
3
XIN
4
VSS
5
INT2
6
SCL
7
SDA
I/O pin for serial
data
8
VDD
Pin for positive
power supply
GND pin
Output pin for
interrupt signal 2
Input pin for
serial clock
Configuration
Nch open-drain output
(no protective diode at VDD)
Nch open-drain output
Output
(no protective diode at VDD)
CMOS input
Input
(no protective diode at VDD)
Nch open-drain output
Bi-directional (no protective diode at VDD)
CMOS input
8
7
6
5
Figure 3
S-35390A-T8T1x
3. SNT-8A
Top view
1
2
3
4
Figure 4
8
7
6
5
S-35390A-I8T1U
Remark 1. x: G or U
2. Please select products of environmental code = U for Sn 100%, halogen-free products.
4
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Pin Functions
1. SDA (I/O for serial data) pin
This is a data input / output pin of I2C-bus interface. This pin inputs / outputs data by synchronizing with a clock pulse
from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, pull up this pin to the VDD
potential via a resistor, and connect it to any other device having open drain or open collector output with wired-OR
connection.
2. SCL (input for serial clock) pin
This pin is to input a clock pulse for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with the
clock pulse.
3. XIN, XOUT (quartz crystal connect) pins
Connect a quartz crystal between XIN and XOUT.
4. INT1 (output for interrupt signal 1) pin
This pin outputs a signal of interrupt, or a clock pulse. By using the status register 2, users can select either of; alarm 1
interrupt, output of user-set frequency, minute-periodical interrupt 1, minute-periodical interrupt 2, or 32.768 kHz output.
This pin has Nch open-drain output.
5. INT2 (output for interrupt signal 2) pin
This pin outputs a signal of interrupt, or a clock pulse. By using the status register 2, users can select either of; alarm 2
interrupt, output of user-set frequency, or minute-periodical interrupt 1. This pin has Nch open-drain output.
6. VDD (positive power supply) pin
Connect this VDD pin with a positive power supply. Regarding the values of voltage to be applied, refer to
" Recommended Operation Conditions".
7. VSS pin
Connect this VSS pin to GND.
Equivalent Circuits of Pins
SCL
SDA
Figure 5
Figure 6
SDA Pin
SCL Pin
INT1, INT2
Figure 7
INT1 Pin, INT2 Pin
5
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Absolute Maximum Ratings
Table 3
Item
Symbol
Applied Pin
Absolute Maximum Rating
Unit
Power supply voltage
VDD
VSS 0.3 to VSS 6.5
V
Input voltage
VIN
SCL, SDA
VSS 0.3 to VSS 6.5
V
Output voltage
VOUT
SDA, INT1, INT2
VSS 0.3 to VSS 6.5
V
Operating ambient
40 to 85
C
Topr
temperature*1
Storage temperature
Tstg
55 to 125
C
*1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a
malfunction.
Caution
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operation Conditions
Table 4
(VSS = 0 V)
Unit
V
Item
Symbol
Condition
Min.
Typ.
Max.
Power supply voltage*1
VDD
Ta = 40C to 85C
1.3
3.0
5.5
Time keeping power
Ta = 40C to 85C
VDET 0.15
5.5
V
VDDT
supply voltage*2
Quartz crystal CL value
CL
6
7
pF
*1. The power supply voltage that allows communication under the conditions shown in Table 9 of " AC Electrical
Characteristics".
*2. The power supply voltage that allows time keeping. For the relationship with VDET (low power supply voltage detection
voltage), refer to " Characteristics (Typical Data)".
Oscillation Characteristics
Table 5
(Ta = 25C, VDD = 3.0 V, VSS = 0 V, VT-200 quartz crystal (CL = 6 pF, 32.768 kHz) manufactured by Seiko Instruments Inc.)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation start voltage VSTA
Within 10 seconds
1.1
5.5
V
Oscillation start time
tSTA
1
s
IC-to-IC frequency
IC
10
10
ppm
deviation*1
Frequency voltage
V
VDD = 1.3 V to 5.5 V
3
3
ppm/V
deviation
External capacitance
Cg
Applied to XIN pin
9.1
pF
Internal oscillation
Applied to XOUT pin
8
pF
Cd
capacitance
*1. Reference value
6
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
DC Electrical Characteristics
Table 6
DC Characteristics (VDD = 3.0 V)
(Ta 40C to 85C, VSS = 0 V, VT-200 quartz crystal (CL = 6 pF, 32.768 kHz, Cg = 9.1 pF) manufactured by Seiko Instruments Inc.)
Item
Symbol
Applied Pin
Condition
Min.
Typ.
Max.
Unit
Current consumption 1
IDD1
Out of communication
0.25
0.93
A
During communication
Current consumption 2
IDD2
6
14
A
(SCL = 100 kHz)
Input current leakage 1 IIZH
SCL, SDA
VIN = VDD
0.5
0.5
A
Input current leakage 2 IIZL
SCL, SDA
VIN = VSS
0.5
0.5
A
Output current leakage 1 IOZH
Output current leakage 2 IOZL
SDA, INT 1 ,
INT2
SDA, INT1 ,
INT2
SCL, SDA
SCL, SDA
VOUT = VDD
0.5
0.5
A
VOUT = VSS
0.5
0.5
A
0.8 VDD
VSS 0.3
VSS 5.5
0.2 VDD
V
V
Input voltage 1
Input voltage 2
VIH
VIL
Output current 1
IOL1
INT 1 , INT2
VOUT = 0.4 V
3
5
mA
Output current 2
Power supply voltage
detection voltage
IOL2
SDA
VOUT = 0.4 V
5
10
mA
0.65
1
1.35
V
VDET
Table 7
DC Characteristics (VDD = 5.0 V)
(Ta 40C to 85C, VSS = 0 V, VT-200 quartz crystal (CL = 6 pF, 32.768 kHz, Cg = 9.1 pF) manufactured by Seiko Instruments Inc.)
Item
Symbol
Applied Pin
Condition
Min.
Typ.
Max.
Unit
Current consumption 1
IDD1
Out of communication
0.3
1.1
A
During communication
Current consumption 2
IDD2
14
30
A
(SCL = 100 kHz)
Input current leakage 1 IIZH
SCL, SDA
VIN = VDD
0.5
0.5
A
Input current leakage 2 IIZL
SCL, SDA
VIN = VSS
0.5
0.5
A
Output current leakage 1 IOZH
SDA, INT 1 ,
INT2
VOUT = VDD
0.5
0.5
A
VOUT = VSS
0.5
0.5
A
0.8 VDD
VSS 0.3
VSS 5.5
0.2 VDD
V
V
Input voltage 1
Input voltage 2
VIH
VIL
SDA, INT 1 ,
INT2
SCL, SDA
SCL, SDA
Output current 1
IOL1
INT 1 , INT2
VOUT = 0.4 V
5
8
mA
Output current 2
Power supply voltage
detection voltage
IOL2
SDA
VOUT = 0.4 V
6
13
mA
0.65
1
1.35
V
Output current leakage 2 IOZL
VDET
7
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
AC Electrical Characteristics
Table 8
VDD
Measurement Conditions
VIH = 0.9 VDD, VIL = 0.1 VDD
20 ns
VOH = 0.5 VDD, VOL = 0.5 VDD
100 pF pull-up resistor 1 k
Input pulse voltage
Input pulse rise / fall time
Output determination voltage
Output load
R = 1 k
SDA
C = 100 pF
Remark
The power supplies of the IC
and load have the same
electrical potential.
Figure 8
Table 9
Output Load Circuit
AC Electrical Characteristics
(Ta = 40C to 85C)
VDD*2 1.3 V
VDD*2 3.0 V
Item
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL clock frequency
fSCL
0
100
0
400
kHz
SCL clock low time
tLOW
4.7
1.3
s
SCL clock high time
tHIGH
4
0.6
s
SDA output delay time*1
tPD
3.5
0.9
s
Start condition setup time
tSU.STA
4.7
0.6
s
Start condition hold time
tHD.STA
4
0.6
s
Data input setup time
tSU.DAT
250
100
ns
Data input hold time
tHD.DAT
0
0
s
Stop condition setup time
tSU.STO
4.7
0.6
s
SCL, SDA rise time
tR
1
0.3
s
SCL, SDA fall time
tF
0.3
0.3
s
Bus release time
tBUF
4.7
1.3
s
Noise suppression time
tI
100
50
ns
*1. Since the output format of the SDA pin is Nch open-drain output, SDA output delay time is determined by the values of
the load resistance (RL) and load capacity (CL) outside the IC. Therefore, use this value only as a reference value.
*2. Regarding the power supply voltage, refer to " Recommended Operation Conditions".
tF
tHIGH
tLOW
tR
SCL
tSU.STA
tHD.DAT
tHD.STA
tSU.DAT
tSU.STO
SDA
(S-35390A input)
tBUF
tPD
SDA
(S-35390A output)
Figure 9
8
Bus Timing
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Configuration of Data Communication
1. Data communication
For data communication, the master device in the system generates a start condition for the S-35390A. Next, the
master device transmits 4-bit device code "0110", 3-bit command and 1-bit read / write command to the SDA line. After
that, output or input is performed from B7 of data. If data I/O has been completed, finish communication by inputting a
stop condition to the S-35390A. The master device generates an acknowledgment signal for every 1-byte. Regarding
details, refer to " Serial Interface".
Read / write bit
Acknowledgment bit
Start condition
Device code
0
STA
1
Command
1
0
C2
C1
C0
R/W
ACK
Stop condition
1-byte data
B7
B6
B5
B4
Figure 10
B3
B2
B1
B0
ACK
STP
Data Communication
9
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
2. Configuration of command
8 types of command are available for the S-35390A. The S-35390A reads / writes the various registers by inputting
these codes and commands. The S-35390A does not perform any operation with any codes and commands other than
those below.
Table 10
Device
Code C2 C1 C0
Command
Description
0
0
0
Status register 1 access
0
0
1
Status register 2 access
0
0
1
1
List of Commands
Data
B7
B6
B5
RESET*1 12 / 24 SC0*2
INT1FE INT1ME INT1AE
0
Real-time data 1 access
(year data to)
Y1
M1
D1
W1
H1
m1
s1
1
Real-time data 2 access
(hour data to)
H1
m1
s1
B4
SC1*2
32kE
Y2
M2
D2
W2
H2
m2
s2
Y4
M4
D4
W4
H4
m4
s4
Y8
M8
D8
*6
H8
m8
s8
H2
m2
s2
H4
m4
s4
H8
m8
s8
B3
B2
B1
B0
INT1*3 INT2*3 BLD*4 POC*4
INT2FE INT2ME INT2AE TEST*5
Y40
Y10
Y20
Y80
*6
*6
*6
M10
*6
*6
D10
D20
*6
*6
*6
*6
*6
H10
H20 AM / PM
*6
m10
m20
m40
*6
s10
s20
s40
H10
m10
s10
H20
m20
s20
AM / PM
m40
s40
*6
*6
*6
INT1 register access
*6
*6
*6
*6
A1WE
W1
W2
W4
(alarm
time
1:
week
/
hour
/
minute)
0110
H8
H10
H20 AM / PM A1HE
H1
H2
H4
(INT1AE = 1, INT1ME = 0,
m8
m10
m20
A1mE
m1
m2
m4
m40
1 0 0 INT1FE = 0)
INT1 register access
*2
SC3*2 SC4*2
(output of user-set frequency)
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz SC2
(INT1ME = 0, INT1FE = 1)
INT2 register access
*6
*6
*6
*6
W4
W2
A2WE
W1
(alarm time 2: week / hour / minute)
H4
H2
H1
H8
H10
H20 AM / PM A2HE
(INT2AE = 1, INT2ME = 0,
m4
m2
A2mE
m1
m8
m10
m20
m40
1 0 1 INT2FE = 0)
INT2 register access
*2
SC6*2 SC7*2
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz SC5
(output of user-set frequency)
(INT2ME = 0, INT2FE = 1)
1 1 0 Clock correction register access
V0
V1
V2
V3
V4
V5
V6
V7
F0
F1
F2
F3
F4
F5
F6
F7
1 1 1 Free register access
*1. Write-only flag. The S-35390A initializes by writing "1" in this register.
*2. Scratch bit. This is a register which is available for read / write operations and can be used by users freely.
*3. Read-only flag. Valid only when using the alarm function. When the alarm time matches, this flag is set to "1", and it is
cleared to "0" when reading.
*4. Read-only flag. "POC" is set to "1" when power is applied. It is cleared to "0" when reading. Regarding "BLD", refer to
" Low Power Supply Voltage Detection Circuit".
*5. Test bit for ABLIC Inc. Be sure to set to "0" in use.
*6. No effect when writing. It is "0" when reading.
10
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Configuration of Registers
1. Real-time data register
The real-time data register is a 7-byte register that stores the data of year, month, day, day of the week, hour, minute,
and second in the BCD code. To write / read real-time data 1 access, transmit / receive the data of year in B7, month,
day, day of the week, hour, minute, second in B0, in 7-byte. When you skip the procedure to access the data of year,
month, day, day of the week, read / write real-time data 2 accesses. In this case, transmit / receive the data of hour in B7,
minute, second in B0, in 3-byte.
The S-35390A transfers a set of data of time to the real-time data register when it recognizes a reading instruction.
Therefore, the S-35390A keeps precise time even if time-carry occurs during the reading operation of the real-time data
register.
Year data (00 to 99)
Start bit of real-time data 1 data access
Y1
Y2
Y4
Y8
Y10
Y20
Y40
Y80
B7
B0
Month data (01 to 12)
M1
M2
M4
M8
M10
0
0
B7
0
B0
Day data (01 to 31)
D1
D2
D4
D8
D10
D20
0
B7
0
B0
Day of the week data (00 to 06)
W1
W2
W4
0
0
0
0
B7
0
B0
Hour data (00 to 23 or 00 to 11)
Start bit of real-time data 2 data access
H1
H2
H4
H8
H10
H20 AM / PM
B7
0
B0
Minute data (00 to 59)
m1
m2
m4
m8
m10
m20
m40
B7
0
B0
Second data (00 to 59)
s1
s2
s4
s8
s10
s20
s40
B7
0
B0
Figure 11
Real-Time Data Register
11
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Year data (00 to 99): Y1, Y2, Y4, Y8, Y10, Y20, Y40, Y80
Sets the lower two digits of the Western calendar year (00 to 99) and links together with the auto calendar
function until 2099.
Example: 2053 (Y1, Y2, Y4, Y8, Y10, Y20, Y40, Y80) = (1, 1, 0, 0, 1, 0, 1, 0)
Month data (01 to 12): M1, M2, M4, M8, M10
Example: December (M1, M2, M4, M8, M10, 0, 0, 0) = (0, 1, 0, 0, 1, 0 ,0 ,0)
Day data (01 to 31): D1, D2, D4, D8, D10, D20
The count value is automatically changed by the auto calendar function.
1 to 31: Jan., Mar., May, July, Aug., Oct., Dec., 1 to 30: April, June, Sep., Nov.
1 to 29: Feb. (leap year), 1 to 28: Feb. (non-leap year)
Example: 29 (D1, D2, D4, D8, D10, D20, 0, 0) = (1, 0, 0, 1, 0, 1, 0, 0)
Day of the week data (00 to 06): W1, W2, W4
A septenary up counter. Day of the week is counted in the order of 00, 01, 02, …, 06, and 00. Set up day of the
week and the count value.
Hour data (00 to 23 or 00 to 11): H1, H2, H4, H8, H10, H20, AM / PM
In 12-hour mode, write 0; AM, 1; PM in the AM / PM bit. In 24-hour mode, users can write either 0 or 1. 0 is
read when the hour data is from 00 to 11, and 1 is read when from 12 to 23.
Example (12-hour mode): 11 p.m.
(H1, H2, H4, H8, H10, H20, AM / PM , 0) = (1, 0, 0, 0, 1, 0, 1, 0)
Example (24-hour mode): 22
(H1, H2, H4, H8, H10, H20, AM / PM , 0) = (0, 1, 0, 0, 0, 1, 1, 0)
Minute data (00 to 59): m1, m2, m4, m8, m10, m20, m40
Example: 32 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (0, 1, 0, 0, 1, 1, 0, 0)
Example: 55 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (1, 0, 1, 0, 1, 0, 1, 0)
Second data (00 to 59): s1, s2, s4, s8, s10, s20, s40
Example: 19 seconds (s1, s2, s4, s8, s10, s20, s40, 0) = (1, 0, 0, 1, 1, 0, 0, 0)
12
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
2. Status register 1
Status register 1 is a 1-byte register that is used to display and set various modes. The bit configuration is shown below.
B7
B6
B5
B4
B3
B2
B1
B0
RESET
12 / 24
SC0
SC1
INT1
INT2
BLD
POC
W
R/W
R/W
R/W
R
R
R
R
R:
W:
R / W:
Figure 12
Read
Write
Read / write
Status Register 1
B0: POC
This flag is used to confirm whether the power is on. The power-on detection circuit operates at power-on and B0 is
set to "1". This flag is read-only. Once it is read, it is automatically set to "0". When this flag is "1", be sure to initialize.
Regarding the operation after power-on, refer to " Power-on Detection Circuit and Register Status".
B1: BLD
This flag is set to "1" when the power supply voltage decreases to the level of detection voltage (VDET) or less. Users
can detect a drop in the power supply voltage. Once this flag is set to "1", it is not set to "0" again even if the power
supply increases to the level of detection voltage (VDET) or more. This flag is read-only. When this flag is "1", be sure
to initialize. Regarding the operation of the power supply voltage detection circuit, refer to " Low Power Supply
Voltage Detection Circuit".
B2: INT2, B3: INT1
This flag indicates the time set by alarm and when the time has reached it. This flag is set to "1" when the time that
users set by using the alarm interrupt function has come. The INT1 flag at alarm 1 interrupt mode and the INT2 flag
at alarm 2 interrupt mode are set to "1". Set "0" in INT1AE (B5 in the status register 2) or in INT2AE (B1 in the status
register 2) after reading "1" in the INT1 flag or in the INT2 flag. This flag is read-only. Once this flag is read, it is set to
"0" automatically.
B4: SC1, B5: SC0
These flags are SRAM type registers, they are 2 bits as a whole, can be freely set by users.
B6: 12 / 24
This flag is used to set 12-hour or 24-hour mode. Set the flag ahead of write operation of the real-time data register in
case of 24-hour mode.
0: 12-hour mode
1: 24-hour mode
B7: RESET
The internal IC is initialized by setting this bit to "1". This bit is write-only. It is always "0" when reading. When
applying the power supply voltage to the IC, be sure to write "1" to this bit to initialize the circuit. Regarding each
status of registers after initialization, refer to " Register Status After Initialization".
13
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
3. Status register 2
Status register 2 is a 1-byte register that is used to display and set various modes. The bit configuration is shown below.
B7
B6
B5
B4
B3
B2
B1
B0
INT1FE
INT1ME
INT1AE
32kE
INT2FE
INT2ME
INT2AE
TEST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R / W: Read / write
Figure 13
Status Register 2
B0: TEST
This is a test flag for ABLIC Inc. Be sure to set this flag to "0" in use. If this flag is set to "1", be sure to initialize to set
"0".
B1: INT2AE, B2: INT2ME, B3: INT2FE
These bits are used to select the output mode for the INT2 pin. Table 11 shows how to select the mode. To use an
alarm 2 interrupt, set alarm interrupt mode, then access the INT2 register.
Table 11
INT2AE
*1.
INT2ME
Output Modes for INT2 Pin
INT2FE
0
0
0
*1
0
1
*1
1
0
*1
1
1
1
0
0
Don't care (both of 0 and 1 are acceptable).
INT2 Pin Output Mode
No interrupt
Output of user-set frequency
Per-minute edge interrupt
Minute-periodical interrupt 1 (50% duty)
Alarm 2 interrupt
B4: 32kE, B5: INT1AE, B6: INT1ME, B7: INT1FE
These bits are used to select the output mode for the INT 1 pin. Table 12 shows how to select the mode. To use
alarm 1 interrupt, access the INT1 register after setting the alarm interrupt mode.
Table 12
32kE
*1.
14
INT1AE
Output Modes for INT1 Pin
INT1ME
0
0
0
*1
0
0
*1
0
1
0
0
1
0
1
0
0
1
1
*1
*1
1
Don't care (both of 0 and 1 are acceptable).
INT1FE
0
1
0
1
0
1
*1
INT 1 Pin Output Mode
No interrupt
Output of user-set frequency
Per-minute edge interrupt
Minute-periodical interrupt 1 (50% duty)
Alarm 1 interrupt
Minute-periodical interrupt 2
32.768 kHz output
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
4. INT1 register and INT2 register
The INT1 and INT2 registers are to set up the output of user-set frequency, or to set up alarm interrupt. Users are able to
switch the output mode by using the status register 2. If selecting to use the output mode for alarm interrupt by status
register 2; these registers work as alarm-time data registers. If selecting the output of user-set frequency by status
register 2; these registers work as data registers to set the frequency for clock output. From each INT1 and INT2 pin,
a clock pulse and alarm interrupt are output.
4. 1
Alarm interrupt
Users can set the alarm time (the data of day of the week, hour, minute) by using the INT1 and INT2 registers which
are 3-byte data registers. The configuration of register is as well as the data register of day of the week, hour, minute,
in the real-time data register; is expressed by the BCD code. Do not set a nonexistent day. Users are necessary to
set up the alarm-time data according to the 12 / 24 hour mode that they set by using the status register 1.
INT2 register
INT1 register
W1
W2
W4
0
0
B7
H1
H2
H4
H8
0
A1WE
W1
B0
B7
/ A1HE
H10 H20 AM
PM
B7
m1
0
B0
m2
m4
m8
H1
m1
B0
B7
Figure 14
W4
0
0
0
0
A2WE
B0
H2
H4
H8
B7
m10 m20 m40 A1mE
B7
W2
/
H10 H20 AM
PM A2HE
B0
m2
m4
m8
m10 m20 m40 A2mE
B0
INT1 Register and INT2 Register (Alarm-Time Data)
The INT1 register has A1WE, A1HE, A1mE at B0 in each byte. It is possible to make data valid; the data of day of
the week, hour, minute which are in the corresponding byte; by setting these bits to "1". This is as well in A2WE,
A2HE, A2mE in the INT2 register.
Setting example: alarm time "7:00 pm" in the INT1 register
(1)
12-hour mode (status register 1 B6 = 0)
Set up 7:00 PM
Data written to INT1 register
*1
*1
*1
*1
*1
Day of the week
Hour
1
1
1
0
0
Minute
0
0
0
0
0
B7
*1. Don't care (both of 0 and 1 are acceptable).
(2)
*1
0
0
*1
1
0
0
1
1
B0
*1
0
0
*1
1*2
0
0
1
1
B0
24-hour mode (status register 1 B6 = 1)
Set up 19:00 PM
Data written to INT1 register
*1
*1
*1
*1
*1
Day of the week
Hour
1
0
0
1
1
Minute
0
0
0
0
0
B7
*1. Don't care (both of 0 and 1 are acceptable).
*2.
Set up the AM / PM flag along with the time setting.
15
2-WIRE REAL-TIME CLOCK
S-35390A
4. 2
Rev.4.2_04
Output of user-set frequency
The INT1 and INT2 registers are 1-byte data registers to set up the output frequency. Setting each bit B7 to B3 in the
register to "1", the frequency which corresponds to the bit is output in the AND-form. SC2 to SC4 in the INT1 register,
and SC5 to SC7 in the INT2 register are 3-bit SRAM type registers that can be freely set by users.
B7
B6
B5
B4
B3
B2
B1
B0
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
SC2
SC3
SC4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R / W: Read / write
Figure 15
INT1 Register (Data Register for Output Frequency)
B7
B6
B5
B4
B3
B2
B1
B0
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
SC5
SC6
SC7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R / W: Read / write
Figure 16
INT2 Register (Data Register for Output Frequency)
Example: B7 to B3 = 50h
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
INT1 pin /
INT2 pin output
Status register 2
• Set to INT1FE or INT2FE = 1
Figure 17
16
Example of Output from INT1 and INT2 Registers (Data Register for Output Frequency)
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
1 Hz clock output is synchronized with second-counter of the S-35390A.
INT1 pin / INT2 pin
output (1 Hz)
Second-counter
n2
n1
n
Figure 18
1 Hz Clock Output and Second-counter
5. Clock correction register
The clock correction register is a 1-byte register that is used to correct advance / delay of the clock. When not using this
function, set this register to "00h". Regarding the register values, refer to " Function of Clock Correction".
B7
B6
B5
B4
B3
B2
B1
B0
V0
V1
V2
V3
V4
V5
V6
V7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R / W: Read / write
Figure 19
Clock Correction Register
6. Free register
This free register is a 1-byte SRAM type register that can be set freely by users.
B7
B6
B5
B4
B3
B2
B1
B0
F0
F1
F2
F3
F4
F5
F6
F7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R / W : Read / write
Figure 20
Free Register
17
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Power-on Detection Circuit and Register Status
The power-on detection circuit operates by power-on the S-35390A, as a result each register is cleared; each register is
set as follows.
Real-time data register:
Status register 1:
Status register 2:
INT1 register:
INT2 register:
Clock correction register:
Free register:
00 (Y), 01 (M), 01 (D), 0 (day of the week), 00 (H), 00 (M), 00 (S)
"01h"
"80h"
"80h"
"00h"
"00h"
"00h"
"1" is set in the POC flag (B0 in the status register 1) to indicate that power has been applied. To correct the oscillation
frequency, the status register 2 goes in the mode the output of user-set frequency, so that 1 Hz clock pulse is output from
the INT1 pin. When "1" is set in the POC flag, be sure to initialize. The POC flag is set to "0" due to initialization so that
the output of user-set frequency mode is cleared (Refer to " Register Status After Initialization").
For the regular operation of power-on detection circuit, as seen in Figure 21, the period to power-up the S-35390A is that
the voltage reaches 1.3 V within 10 ms after setting the IC’s power supply voltage at 0 V. When the power-on detection
circuit is not working normally is; the POC flag (B0 in the status register 1) is not in "1", or 1 Hz is not output from the INT1
pin. In this case, power-on the S-35390A once again because the internal data may be in the indefinite status.
Moreover, regarding the processing right after power-on, refer to " Flowchart of Initialization and Example of
Real-time Data Set-up".
Within 10 ms
1.3 V
0V
*1
*1. 0 V indicates that there are no potential differences between the VDD
pin and VSS pin of S-35390A.
Figure 21
18
How to Raise the Power Supply Voltage
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Register Status After Initialization
The status of each register after initialization is as follows.
Real-time data register:
Status register 1:
00 (Y), 01 (M), 01 (D), 0 (day of the week), 00 (H), 00 (M), 00 (S)
"0 B6 B5 B4 0 0 0 0 b"
(In B6, B5, B4, the data of B6, B5, B6 in the status register 1 at initialization is set.
Refer to Figure 22.)
"00h"
"00h"
"00h"
"00h"
"00h"
Status register 2:
INT1 register:
INT2 register:
Clock correction register:
Free register:
Read from status register 1
Write to status register 1
1
18
9
1
9
18
SCL
R/W
R/W
0 110000 1
L L H LL L L L
Device code
command
B7 B5 : Not reset
0
STOP
NO_ACK
B7 B5
ACK
0
START
10100000
STOP
Device code
command
ACK
0 1 1 0 0 000
ACK
START
SDA
Write "1" to reset flag and SC0.
: S-35390A output data
: Master device input data
Figure 22
Data of Status Register 1 at Initialization
19
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Low Power Supply Voltage Detection Circuit
The S-35390A has a low power supply voltage detection circuit, so that users can monitor drops in the power supply
voltage by reading the BLD flag (B1 in the status register 1). There is a hysteresis width of approx. 0.15 V typ. between
detection voltage and release voltage (refer to " Characteristics (Typical Data)"). The low power supply voltage
detection circuit does the sampling operation only once in one sec for 15.6 ms.
If the power supply voltage decreases to the level of detection voltage (VDET) or less, "1" is set to the BLD flag so that
sampling operation stops. Once "1" is detected in the BLD flag, no sampling operation is performed even if the power
supply voltage increases to the level of release voltage or more, and "1" is held in the BLD flag.
Furthermore, the S-35390A does not initialize the internal circuit even if "1" is set to the BLD flag. If the BLD flag is "1"
even after the power supply voltage is recovered, the internal circuit may be in the indefinite status. In this case, be sure to
initialize the circuit. Without initializing, if the next BLD flag reading is done after sampling, the BLD flag gets reset to "0". In
this case, be sure to initialize although the BLD flag is in "0" because the internal circuit may be in the indefinite status.
VDD
Hysteresis width
0.15 V approximately
Detection voltage
Release
voltage
Time keeping power
supply voltage (min.)
BLD flag reading
Sampling pulse
15.6 ms
1s
1s
Stop
Stop
Stop
BLD flag
Figure 23
Timing of Low Power Supply Voltage Detection Circuit
Circuits Power-on and Low Power Supply Voltage Detection
Figure 24 shows the changes of the POC flag and BLD flag due to VDD fluctuation.
Low power supply voltage
detection voltage
VDD
POC flag
BLD flag
Status register 1
reading
Figure 24
20
POC Flag and BLD Flag
Low power supply voltage
detection voltage
VSS
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Correction of Nonexistent Data and End-of-Month
When users write the real-time data, the S-35390A checks it. In case that the data is invalid, the S-35390A does the
following procedures.
1. Processing of nonexistent data
Table 13
Register
Year data
Month data
Day data
Day of the week data
24-hour
Hour data*1
12-hour
Minute data
Second data*2
Normal Data
00 to 99
01 to 12
01 to 31
0 to 6
0 to 23
0 to 11
00 to 59
00 to 59
Processing of Nonexistent Data
Nonexistent Data
XA to XF, AX to FX
00, 13 to 19, XA to XF
00, 32 to 39, XA to XF
7
24 to 29, 3X, XA to XF
12 to 20, XA to XF
60 to 79, XA to XF
60 to 79, XA to XF
Result
00
01
01
0
00
00
00
00
*1. In 12-hour mode, write the AM / PM flag (B1 in hour data in the real-time data register).
In 24-hour mode, the AM / PM flag in the real-time data register is omitted. However in the flag of reading, users are
able to read 0; 0 to 11, 1; 12 to 23.
*2. Processing of nonexistent data, regarding second data, is done by a carry pulse which is generated in 1 second, after
writing. At this point the carry pulse is sent to the minute-counter.
2. Correction of end-of-month
A nonexistent day, such as February 30 and April 31, is set to the first day of the next month.
21
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
INT1 Pin and INT2 Pin Output Mode
These are selectable for the output mode for INT1 and INT2 pins;
Alarm interrupt, the output of user-set frequency, per-minute edge interrupt output, minute-periodical interrupt output 1. In
the INT1 pin output mode, in addition to the above modes, minute-periodical interrupt output 2 and 32.768 kHz output
are also selectable.
To switch the output mode, use the status register 2. Refer to "3. Status register 2" in " Configuration of Registers".
When switching the output mode, be careful of the output status of the pin. Especially, when using alarm interrupt / output
of frequency, switch the output mode after setting "00h" in the INT1 / INT2 register. In 32.768 kHz output / per-minute edge
interrupt output / minute-periodical interrupt output, it is unnecessary to set data in the INT1 / INT2 register for users.
Refer to the followings regarding each operation of output modes.
1. Alarm interrupt output
Alarm interrupt output is the function to output "L" from the INT1 / INT2 pin, at the alarm time which is set by user has
come. If setting the pin output to "H", turn off the alarm function by setting "0" in INT1AE / INT2AE in the status register 2.
To set the alarm time, set the data of day of the week, hour and minute in the INT1 / INT2 register. Refer to "4. INT1
register and INT2 register" in " Configuration of Registers".
1. 1
Alarm setting of "W (day of the week), H (hour), m (minute)"
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1ME = INT1FE = 0
• INT2 pin output mode
INT2ME = INT2FE = 0
INT1 register
INT2 register
mx
Hx
INTx register alarm enable flag
• AxHE = AxmE = AxWE = "1"
Wx
Comparator
Second Minute Hour
Day of
Day
the week
Alarm interrupt
Month
Year
Real-time data
W (day of the week)
Real-time data
H h (m − 1) m 59 s
H h 00 m 00 s
Change by program
59 s
01 s
Change by program
H h (m + 1) m 00 s
Change by program
INT1AE / INT2AE
*1
Alarm time matches
OFF
INT1 pin / INT2 pin
Period when alarm time matches
*1. If users clear INT1AE / INT2AE once; "L" is not output from the INT1 / INT 2 pin by setting INT1AE / INT2AE enable
again, within a period when the alarm time matches real-time data.
Figure 25
22
Alarm Interrupt Output Timing
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
1. 2
Alarm setting of "H (hour)"
INTx register alarm enable flag
• AxHE = AxmE = AxWE = "1"
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1ME = INT1FE = 0
• INT2 pin output mode
INT2ME = INT2FE = 0
INT1 register
INT2 register
mx
Hx
Wx
Dx
Mx
Yx
Alarm interrupt
Comparator
Second Minute Hour
Day of Day
the week
Month
01 s
59 s
Year
Real-time data
Real-time data
H h 00 m 00 s
(H - 1) h 59 m 59 s
Change by program
Change by program
H h 01 m 00 s
H h 59 m 59 s
(H + 1) h 00 m 00 s
Change by program
Change by program
INT1AE / INT2AE
*1
Alarm time matches
OFF
INT1 pin / INT2 pin
*1
Alarm time
matches*2
OFF
Period when alarm time matches
*1. If users clear INT1AE / INT2AE once; "L" is not output from the INT1 / INT2 pin by setting INT1AE / INT2AE enable
again, within a period when the alarm time matches real-time data.
*2. If turning the alarm output on by changing the program, within the period when the alarm time matches real-time data,
"L" is output again from the INT1 / INT 2 pin when the minute is counted up.
Figure 26
Alarm Interrupt Output Timing
2. Output of user-set frequency
The output of user-set frequency is the function to output the frequency which is selected by using data, from the INT1
/ INT 2 pin, in the AND-form. Set up the data of frequency in the INT1 / INT2 register.
Refer to "4. INT1 register and INT2 register" in " Configuration of Registers".
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1AE = Don’t care (0 or 1), INT1ME = 0
• INT2 pin output mode
INT2AE = Don’t care (0 or 1), INT2ME = 0
Change by program
INT1FE / INT2FE
Free-run output starts
OFF
INT1 pin / INT2 pin
Figure 27
Output Timing of User-set Frequency
23
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
3. Per-minute edge interrupt output
Per-minute edge interrupt output is the function to output "L" from the INT 1 / INT2 pin, when the first minute-carry
processing is done, after selecting the output mode.
To set the pin output to "H", turn off the output mode of per-minute edge interrupt. In the INT1 pin output mode, input
"0" in INT1ME in the status register 2. In the INT2 pin output mode, input "0" in INT2ME.
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1AE = Don’t care (0 or 1), INT1FE = 0
• INT2 pin output mode
INT2AE = Don’t care (0 or 1), INT2FE = 0
Change by program
INT1ME / INT2ME
Minute-carry processing
Minute-carry
processing
OFF
INT1 pin / INT2 pin
"L" is output again if this period is within 7.81 ms*1.
*1. Pin output is set to "H" by disabling the output mode within 7.81 ms, because the signal of this procedure is
maintained for 7.81 ms. Note that pin output is set to "L" by setting the output mode enable again.
Figure 28
Timing of Per-Minute Edge Interrupt Output
4. Minute-periodical interrupt output 1
The minute-periodical interrupt 1 is the function to output the one-minute clock pulse (Duty 50%) from the INT 1 / INT2
pin, when the first minute-carry processing is done, after selecting the output mode.
Status register 2 setting
INT1 pin output mode
32kE = 0, INT1AE = 0
INT2 pin output mode
INT2AE = 0
Change by program (OFF)
INT1ME, INT1FE
INT2ME, INT2FE
Minute-carry
processing
Minute-carry
processing
Minute-carry
processing
Minute-carry
processing
Minute-carry
processing
INT1 pin / INT2 pin
30 s
30 s
30 s
30 s
30 s
30 s
30 s
30 s
30 s
"L" is output again if this period is within 7.81 ms*1.
"H" is output again if this period is 7.81 ms or longer.
"L" is output at the next minute-carry processing.
*1. Setting the output mode disable makes the pin output "H", while the output from the INT1 / INT2 pin is in "L".
Note that pin output is set to "L" by setting the output mode enable again.
Figure 29
24
Timing of Per-Minute Steady Interrupt Output 1
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
5. Minute-periodical interrupt output 2 (only in the INT1 pin output mode)
The output of minute-periodical interrupt 2 is the function to output "L", for 7.81 ms, from the INT 1 pin, synchronizing
with the first minute-carry processing after selecting the output mode. However, during reading in the real-time data
register, the procedure delays at 0.5 seconds max. thus output "L" from the INT 1 pin also delays at 0.5 seconds max.
During writing in the real-time data register, some delay is made in the output period due to write timing and the
second-data of writing.
(1)
During normal operation
Minute-carry processing
Minute-carry processing
Minute-carry processing
INT1 pin
7.81 ms
(2)
7.81 ms
60 s
7.81 ms
60 s
During reading operation in the real-time data register
(Normal minutecarry processing) Minute-carry processing
Minute-carry processing
Minute-carry processing
INT1 pin
0.5 s max.
7.81 ms
7.81 ms
60 s
60 s
7.81 ms
Serial
communication
Real-time data
read command
(3)
Real-time
Real-time data Real-time
data reading read command data reading
During writing operation in the real-time data register
Minute-carry processing
Minute-carry processing
Minute-carry processing
INT1 pin
7.81 ms
7.81 ms
55 s
45 s
10 s
7.81 ms
80 s
30 s
50 s
Real-time data
write timing
Second data of writing: "50" s
The output period is shorter.
Figure 30
Second data of writing: "10" s
The output period is longer.
Timing of Minute-periodical Interrupt Output 2
25
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
6. Operation of power-on detection circuit (only in the INT1 pin output mode)
When power is applied to the S-35390A, the power-on detection operates to set "1" in the POC flag (B0 in the status
register 1). A 1 Hz clock pulse is output from the INT 1 pin.
Status register 2 setting
Change by reset command
• 32kE = 0, INT1AE = INT1ME = 0
INT1FE
OFF
INT1 pin
0.5 s
Figure 31
0.5 s
Output Timing of INT 1 Pin during Operation of Power-on Detection Circuit
Function of Clock Correction
The function of clock correction is to correct advance / delay of the clock due to the deviation of oscillation frequency, in
order to make a high precise clock. For correction, the S-35390A adjusts the clock pulse by using a certain part of the
dividing circuit, not adjusting the frequency of the quartz crystal. Correction is performed once every 20 seconds (or 60
seconds). The minimum resolution is approx. 3 ppm (or approx. 1 ppm) and the S-35390A corrects in the range of 195.3
ppm to 192.2 ppm (or of 65.1 ppm to 64.1 ppm). (Refer to Table 14.) Users can set up this function by using the clock
correction register. Regarding how to calculate the setting data, refer to "1. How to calculate". When not using this
function, be sure to set "00h".
Table 14
Item
Correction
Minimum resolution
Correction range
26
Function of Clock Correction
B0 = 0
Every 20 seconds
3.052 ppm
195.3 ppm to 192.2 ppm
B0 = 1
Every 60 seconds
1.017 ppm
65.1 ppm to 64.1 ppm
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
1. How to calculate
1. 1
If current oscillation frequency > target frequency (in case the clock is fast)
*1
Correction value = 128 Integral value
Caution
(Current oscillation frequency
*3
*2
actual measurement value ) (Target oscillation frequency )
(Current oscillation frequency
*2
actual measurement value )
*4
(Minimum resolution )
The figure range which can be corrected is that the calculated value is from 0 to 64.
*1. Convert this value to be set in the clock correction register. For how to convert, refer to "(1) Calculation example
1".
*2. Measurement value when 1 Hz clock pulse is output from the INT 1 pin (or INT2 pin).
*3. Target value of average frequency when the clock correction function is used.
*4. Refer to "Table 14 Function of Clock Correction".
(1) Calculation example 1
In case of current oscillation frequency actual measurement value = 1.000070 [Hz], target oscillation frequency =
1.000000 [Hz], B0 = 0 (Minimum resolution = 3.052 ppm)
(1.000070) (1.000000)
Correction value = 128 Integral value
1.000070
) (3.052 106)
(
= 128 Integral value (22.93) = 128 22 = 106
Convert the correction value "106" to 7-bit binary and obtain "1101010b".
Reverse the correction value "1101010b" and set it to B7 to B1 of the clock correction register.
Thus, set the clock correction register:
(B7, B6, B5, B4, B3, B2, B1, B0) = (0, 1, 0, 1, 0, 1, 1, 0)
1. 2
If current oscillation frequency < target frequency (in case the clock is slow)
Correction value = Integral value
Caution
(Current oscillation frequency
(Target oscillation frequency) actual measurement value)
(Current oscillation frequency
actual measurement value)
1
(Minimum resolution)
The figure range which can be corrected is that the calculated value is from 0 to 62.
(1) Calculation example 2
In case of current oscillation frequency actual measurement value = 0.999920 [Hz], target oscillation frequency =
1.000000 [Hz]. B0 = 0 (Minimum resolution = 3.052 ppm)
(1.000000) (0.999920)
1
Correction value = Integral value
(0.999920) (3.052 10-6)
= Integral value (26.21) 1 = 26 1 = 27
Thus, set the clock correction register:
(B7, B6, B5, B4, B3, B2, B1, B0) = (1, 1, 0, 1, 1, 0, 0, 0)
(2) Calculation example 3
In case of current oscillation frequency actual measurement value = 0.999920 [Hz], target oscillation frequency =
1.000000 [Hz], B0 = 1 (Minimum resolution = 1.017 ppm)
(1.000000) (0.999920)
1
Correction value = Integral value
(0.999920) (1.017 10-6)
= Integral value (78.66) 1
This calculated value exceeds the correctable range 0 to 62.
B0 = "1" (minimum resolution = 1.017 ppm) indicates the correction is impossible.
27
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
2. Setting values for registers and correction values
Table 15
Table 16
28
Setting Values for Registers and Correction Values (Minimum Resolution: 3.052 ppm (B0 = 0))
B7
B6
B5
B4
B3
B2
B1
B0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
Correction Value
[ppm]
192.3
189.2
186.2
6.1
3.1
0
3.1
6.1
9.2
189.2
192.3
195.3
Rate
[s / day]
16.61
16.35
16.09
0.53
0.26
0
0.26
0.53
0.79
16.35
16.61
16.88
Setting Values for Registers and Correction Values (Minimum Resolution: 1.017 ppm (B0 = 1))
B7
B6
B5
B4
B3
B2
B1
B0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Correction Value
[ppm]
64.1
63.1
62.0
2.0
1.0
0
1.0
2.0
3.0
63.1
64.1
65.1
Rate
[s / day]
5.54
5.45
5.36
0.18
0.09
0
0.09
0.18
0.26
5.45
5.54
5.62
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
3. How to confirm setting value for register and result of correction
The S-35390A does not adjust the frequency of the quartz crystal by using the clock correction function. Therefore users
cannot confirm if it is corrected or not by measuring output 32.768 kHz. When the function of clock correction is being
used, the cycle of 1 Hz clock pulse output from the INT1 pin changes once in 20 times or 60 times, as shown in Figure
32.
INT1 pin
(1 Hz output)
a
a
a
19 times or 59 times
b
a
Once
In case of B0 = 0: a = 19 times, b = Once
In case of B0 = 1: a = 59 times, b = Once
Figure 32
Confirmation of Clock Correction
Measure a and b by using the frequency counter*1. Calculate the average frequency (Tave) based on the measurement
results.
B0 = 0, Tave = (a 19 b) 20
B0 = 1, Tave = (a 59 b) 60
Calculate the error of the clock based on the average frequency (Tave). The following shows an example for
confirmation.
Confirmation example: When B0 = 0, 66h is set
Measurement results: a = 1.000080 Hz, b = 0.998493 Hz
Clock Correction Register Setting Value
Before correction
After correction
00 h (Tave = a)
66 h (Tave = (a 19 b) 20)
Average Frequency [Hz]
Per Day [s]
1.000080
1.00000065
86393
86399.9
Calculating the average frequency allows to confirm the result of correction.
*1. Use a frequency counter with 7-digit or greater precision.
Caution
Measure the oscillation frequency under the usage conditions.
29
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Serial Interface
The S-35390A transmits / receives various commands via I2C-bus serial interface to read / write data. Regarding
transmission is as follows.
1. Start condition
A start condition is when the SDA line changes "H" to "L" when the SCL line is in "H", so that the access starts.
2. Stop condition
A stop condition is when the SDA line changes "L" to "H" when the SCL line is in "H", and the access stops, so that the
S-35390A gets standby.
tSU.STA
tHD.STA
tSU.STO
SCL
SDA
Start condition
Stop condition
Figure 33
Start / Stop Conditions
3. Data transfer and acknowledgment signal
Data transmission is performed for every 1-byte, after detecting a start condition. Transmit data while the SCL line is in
"L", and be careful of spec of tSU.DAT and tHD. DAT when changing the SDA line. If the SDA line changes while the SCL
line is in "H", the data will be recognized as start/stop condition in spite of data transmission. Note that by this case, the
access will be interrupted.
During data transmission, every moment receiving 1-byte data, the devices which work for receiving data send an
acknowledgment signal back. For example, as seen in Figure 34, in case that the S-35390A is the device working for
receiving data and the master device is the one working for sending data; when the 8th clock pulse falls, the master
device releases the SDA line. After that, the S-35390A sends an acknowledgment signal back, and set the SDA line to
"L" at the 9th clock pulse. The S-35390A does not output an acknowledgment signal is that the access is not being
done regularly.
SCL
(S-35390A input)
8
1
tSU.DAT
9
tHD.DAT
SDA
(Master device
output)
SDA is released
High-Z
Output acknowledgment
(Active "L")
SDA
(S-35390A output) Start condition
High-Z
tPD
Figure 34
30
Output Timing of Acknowledgment Signal
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
The followings are data reading / writing in the S-35390A.
3. 1
Data reading in the S-35390A
After detecting a start condition, the S-35390A receives device code and command. The S-35390A enters the
read-data mode by the read / write bit "1". The data is output from B7 in 1-byte. Input an acknowledgment signal
from the master device every moment that the S-35390A outputs 1-byte data. However, do not input an
acknowledgment signal (input NO_ACK) for the last data-byte output from the master device. This procedure
notifies the completion of reading. Next, input a stop condition to the S-35390A to finish access.
1-byte data
1
18
9
SCL
R/W
B7
Device code command
: S-35390A output data
B0
Input NO_ACK after the 1st byte
of data has been output.
: Master device input data
Figure 35
STOP
NO_ACK
0 1 1 0 000 1
ACK
START
SDA
Example of Data Reading 1 (1-Byte Data Register)
3-byte data
1
9
18
27
B7
B0 B7
36
SCL
R/W
: S-35390A output data
STOP
B0
NO_ACK
B7
ACK
Device code command
ACK
01100111
ACK
START
SDA
B0
Input NO_ACK after the 3rd byte of data
has been output.
: Master device input data
Figure 36
Example of Data Reading 2 (3-Byte Data Register)
31
2-WIRE REAL-TIME CLOCK
S-35390A
3. 2
Rev.4.2_04
Data writing in the S-35390A
After detecting a start condition, the S-35390A receives device code and command. The S-35390A enters the
write-data mode by the read / write bit "0". Input data from B7 to B0 in 1-byte. The S-35390A outputs an
acknowledgment signal "L" every moment that 1-byte data is input. After receiving the acknowledgment signal
which is for the last byte-data, input a stop condition to the S-35390A to finish access.
1-byte data
1
18
9
SCL
R/W
B7
STOP
Device code command
ACK
0 1 1 0 000 0
ACK
START
SDA
B0
: S-35390A output data
: Master device input data
Figure 37
Example of Data Writing 1 (1-Byte Data Register)
3-byte data
1
9
18
36
27
SCL
R/W
B0 B7
: S-35390A output data
: Master device input data
Figure 38
32
Example of Data Reading 2 (3-Byte Data Register)
B0
STOP
B0 B7
ACK
ACK
B7
Device code command
ACK
0 1100110
ACK
START
SDA
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
4. Data access
4. 1
Real-time data 1 access
1
9
72
63
18
SCL
R/W
B0
B0
B7
Year data
STOP
*2
*1
ACK
*2
B7
Device code
command
ACK
ACK
0 1 100 1 0
ACK
START
SDA
Second data
I/O mode switching
I/O mode switching
*1. Set NO_ACK = 1 when reading.
*2. Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 39
4. 2
Real-time data 2 access
1
Real-Time Data 1 Access
9
18
36
27
SCL
R/W
Minute data
*1
B0
B7
STOP
ACK
B7
Hour data
B0
Second data
I/O mode switching
Set NO_ACK = 1 when reading.
Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 40
4. 3
*2
B0
B7
I/O mode switching
*1.
*2.
ACK
*2
Device code
command
ACK
0 1 1 00 11
ACK
START
SDA
Real-Time Data 2 Access
Status register 1 access and status register 2 access
9
1
18
SCL
*1
B7
B0
Status data
I/O mode switching
*1.
*2.
STOP
Device code
command
ACK*2
0 11000
ACK
START
SDA
R/W
I/O mode switching
0: Status register 1 selected, 1: Status register 2 selected
Set NO_ACK = 1 when reading.
Figure 41
Status Register 1 Access and Status Register 2 Access
33
2-WIRE REAL-TIME CLOCK
S-35390A
4. 4
Rev.4.2_04
INT1 register access and INT2 register access
In reading / writing the INT1 and INT2 registers, data varies depending on the setting of the status register 2. Be sure
to read / write after setting the status register 2. When setting the alarm by using the status register 2, these registers
work as 3-byte alarm time data registers, in other statuses, they work as 1-byte registers. When outputting the
user-set frequency, they are the data registers to set up the frequency.
Regarding details of each data, refer to "4.
Caution
INT1 register and INT2 register" in " Configuration of Registers".
Users cannot use both functions of alarm 1 interrupt and output of user-set frequency for the
INT1 pin and INT2 pin simultaneously.
9
1
18
27
36
SCL
R/W
*1
B0
B7
Day of the week
Hour data
data
I/O mode switching
B7
STOP
*2
*3
B0
B7
ACK
ACK
I/O mode switching
*3
Device code
command
*1.
*2.
*3.
ACK
0 11010
ACK
START
SDA
B0
Minute data
0: INT1 register selected, 1: INT2 register selected
Set NO_ACK = 1 when reading.
Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 42
INT1 Register Access and INT2 Register Access
9
1
18
SCL
*1
*1.
*2.
B0
Frequency
setting data
I/O mode switching
0: INT1 register selected, 1: INT2 register selected
Set NO_ACK = 1 when reading.
Figure 43
34
B7
STOP
I/O mode switching
*2
Device code
command
ACK
0 11010
ACK
START
SDA
R/W
INT1 Register and INT2 Register (Data Register for Output Frequency) Access
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
4. 5
Clock correction register access
1
9
18
SCL
R/W
B7
Device code
command
STOP
ACK
0 110110
ACK*1
START
SDA
B0
Clock
correction data
I/O mode switching
I/O mode switching
*1.
Set NO_ACK = 1 when reading.
Figure 44
4. 6
Clock Correction Register Access
Free register access
1
9
18
SCL
R/W
I/O mode switching
*1.
ACK*1
Device code
command
B7
STOP
0 110111
ACK
START
SDA
B0
Free register
data
I/O mode switching
Set NO_ACK = 1 when reading.
Figure 45
Free Register Access
35
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Reset After Communication Interruption
In case of communication interruption in the S-35390A, for example, if the power supply voltage drops and only the master
device is reset during communication, the S-35390A does not perform the next operation because the internal circuit
keeps the status prior to communication interruption. Since the S-35390A does not have a reset pin, users usually reset its
internal circuit by inputting a stop condition. However, if the SDA is outputting "L" (during output of acknowledgment signal
or reading), the S-35390A does not accept a stop condition from the master device. In this case, users are necessary to
finish acknowledgment output or reading of the SDA. Figure 46 shows how to reset.
First, input a start condition from the master device (the S-35390A cannot detect a start condition because the SDA in the
S-35390A H is outputting "L"). Next, input a clock pulse equivalent to 7-byte data access (63-clock) from the SCL. During
this period, release the SDA line for the master device. By this procedure, SDA I/O before communication interruption is
finished, and the SDA line in the S-35390A is released. After that, inputting a stop condition resets the internal circuit and
restores the regular communication. This reset procedure is recommended to be executed at initialization of the system
after the master device's power supply voltage is raised.
If this reset procedure is executed when the S-35390A outputs an acknowledgment signal of a writing instruction, the
writing operation may be performed at the corresponding register, so caution should be exercised.
Start
condition
1
SCL
Stop
condition
Clocks equivalent to 7-byte data access
2
8
9
62
63
SDA
(Master device
output)
SDA
(S-35390A
output)
SDA
"L" or High-Z
"L"
"L" or High-Z
"L"
Figure 46
36
How to Reset
High-Z
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Flowchart of Initialization and Example of Real-time Data Set-up
Figure 47 is a recommended flowchart when the master device shifts to a normal operation status and initiates
communication with the S-35390A. Regarding how to apply power, refer to " Power-on Detection Circuit and Register
Status". It is unnecessary for users to comply with this flowchart of real-time data strictly. And if using the default data at
initializing, it is also unnecessary to set up again.
START
Read status register 1
NO
POC = 1
YES
Wait for 0.5 s
*1
NO
BLD = 0
YES
Initialize
(status register 1 B7 = 1)
Read real-time data 1
Read status register 1
NO
POC = 0
YES
NO
BLD = 0
YES
Set 24-hour / 12-hour mode
to status register 1
Read status register 1
Confirm data in status
register 1
NG
OK
Set real-time data 1
Read real-time data 1
*2
Confirm data in real-time
data 1
NG
OK
END
*1.
*2.
Do not communicate for 0.5 seconds since the power-on detection circuit is in operation.
Reading the real-time data 1 should be completed within 1 second after setting the real-time data 1.
Figure 47
Example of Initialization Flowchart
37
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Examples of Application Circuits
VCC
10 k
VCC
INT1
VDD
System
power supply
10 k
INT2
1 k
VSS
1 k
S-35390A
CPU
SDA
SCL
XOUT
XIN
VSS
Cg
Caution
1.
2.
Because the I/O pin has no protective diode on the VDD side, the relation of VCC VDD is possible,
but pay careful attention to the specifications.
Start communication under stable condition after power-on the power supply in the system.
Figure 48
Application Circuit 1
System power
supply
10 k
INT1
VDD
VCC
10 k
INT2
1 k
1 k
S-35390A
SDA
CPU
SCL
VSS
XOUT
XIN
VSS
Cg
Caution Start communication under stable condition after power-on the power supply in the system.
Figure 49
Caution
38
Application Circuit 2
The above connection diagrams do not guarantee operation.
sufficient evaluation using the actual application.
Set the constants after performing
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Adjustment of Oscillation Frequency
1. Configuration of crystal oscillation circuit
Since the crystal oscillation circuit is sensitive to external noise (the clock accuracy is affected), the following measures
are essential for optimizing the configuration.
Place the S-35390A, quartz crystal, and external capacitor (Cg) as close to each other as possible.
Increase the insulation resistance between pins and the substrate wiring patterns of XIN and XOUT.
Do not place any signal or power lines close to the crystal oscillation circuit.
Locating the GND layer immediately below the crystal oscillation circuit is recommended.
Locate the bypass capacitor adjacent to the power supply pin of the S-35390A.
Parasitic capacitance*3
XIN
Rf
Cg
Quartz crystal: 32.768 kHz
CL = 6 pF*1
Cg = None*2 to 9.1 pF
Parasitic capacitance*3
Rd
XOUT
Rf = 100 M (typ.)
Rd = 100 k (typ.)
Cd = 8 pF (typ.)
Cd
S-35390A
*1. When setting the value for the quartz crystal's CL as 7 pF, connect Cd externally if necessary.
*2. The crystal oscillation circuit operates even when Cg is not connected. Note that the oscillation frequency is in the
direction that it advances.
*3. Design the board so that the parasitic capacitance is within 5 pF.
Figure 50
Connection Diagram 1
1
Quartz crystal
Cg
Figure 51
Caution
S-35390A
8
2 XOUT
7
3 XIN
6
4 VSS
5
Locate the GND layer in the
layer immediately below
Connection Diagram 2
1. When using the quartz crystal with a CL exceeding the rated value (7 pF) (e.g: CL = 12.5 pF),
oscillation operation may become unstable. Use a quartz crystal with a CL value of 6 pF or 7 pF.
2. Oscillation characteristics is subject to the variation of each component such as substrate parasitic
capacitance, parasitic resistance, quartz crystal, and Cg. When configuring a crystal oscillation
circuit, pay sufficient attention for them.
39
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
2. Measurement of oscillation frequency
When the S-35390A is turned on, the internal power-on detector operates and a signal of 1 Hz is output from the INT 1
pin to select the quartz crystal and optimize the Cg value. Turn the power on and measure the signal with a frequency
counter following the circuit configuration shown in Figure 52.
If 1 Hz signal is not output, the power-on detector does not operate normally. Turn off the power and then turn it on again.
For how to apply power, refer to " Power-on Detection Circuit and Register Status".
Remark If the error range is 1 ppm in relation to 1 Hz, the time is shifted by approximately 2.6 seconds per month
(calculated using the following mode).
10–6 (1 ppm) 60 seconds 60 minutes 24 hours 30 days = 2.592 seconds
VDD
1 kΩ
1 kΩ
XIN
SDA
SCL
Cg
S-35390A
10 kΩ
XOUT
INT1
Open
or pull-up
INT2
VSS
Figure 52
Caution
40
Frequency
counter
Configuration of Oscillation Frequency Measurement Circuit
1. Use a high-accuracy frequency counter of 7 digits or more.
2. Measure the oscillation frequency under the usage conditions.
3. Since the 1 Hz signal continues to be output, initialization must be executed during normal
operation.
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
3. Adjustment of oscillation frequency
3. 1
Adjustment by setting Cg
Matching of the quartz crystal with the nominal frequency must be performed with the parasitic capacitance on the
board included. Select a quartz crystal and optimize the Cg value in accordance with the flowchart below.
START
Select a quartz crystal*1
Variable
capacitance
YES
Trimmer capacitor
NO
Fixed capacitor
Set to center
of variable
capacitance*3
Set Cg
NO
Frequency
Cg in
specification
YES
Optimal
value*2
Change Cg
NO
NO
YES
Make fine adjustment
of frequency using
variable capacitance
YES
END
*1. Request a quartz crystal manufacturer for a matching evaluation between the IC and the quartz crystal. The
recommended quartz crystal characteristic values are, CL value (load capacitance) = 6 pF, R1 value (equivalent
serial resistance) = 50 k max.
*2. The Cg value must be selected on the actual PCB since it is affected by parasitic capacitance. Select the
external Cg value in a range of 0 pF to 9.1 pF.
*3. Adjust the rotation angle of the variable capacitance so that the capacitance value is slightly smaller than the
center, and confirm the oscillation frequency and the center value of the variable capacitance. This is done in
order to make the capacitance of the center value smaller than one half of the actual capacitance value because
a smaller capacitance value increases the frequency variation.
Figure 53
Caution
Quartz Crystal Setting Flow
1. The oscillation frequency varies depending on the ambient temperature and power supply
voltage. Refer to " Characteristics (Typical Data)".
2. The 32.768 kHz quartz crystal operates more slowly at an operating temperature higher or
lower than 20C to 25C. Therefore, it is recommended to set the oscillator to operate
slightly faster at normal temperature.
41
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
42
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
Characteristics (Typical Data)
1. Standby current vs. VDD characteristics
2. Current consumption when 32 kHz is output
vs. VDD characteristics
Ta = 25C, CL = 6 pF
IDD1
[A]
Ta = 25C, CL = 6 pF
1.0
1.0
0.8
0.8
0.6
IDD3
[A]
0.4
0.2
0
0.6
0.4
0.2
0
2
1
3
VDD [V]
4
5
0
6
3. Current consumption during operation
vs. Input clock characteristics
0
2
1
3
VDD [V]
Ta = 25C, CL = 6 pF
IDD2
[A]
45
0.9
40
0.8
0.7
VDD = 5.0 V
0.6
IDD1
0.5
[A]
0.4
25
20
VDD = 3.0 V
15
0.2
5
0.1
0
VDD = 5.0 V
0.3
10
0
100
200
300
400
SCLfrequency [kHz]
VDD = 3.0 V
0
–40 –25
500
5. Standby current vs. Cg characteristics
0
100
0.9
80
0.8
60
0.7
40
0.6
f/f
[ppm]
75 85
VDD = 5.0 V
20
0
VDD = 3.0 V
–20
VDD = 5.0 V
–40
0.2
–60
VDD = 3.0 V
0.1
0
50
Ta = 25C, CL = 6 pF
1.0
0.3
25
Ta [C]
6. Oscillation frequency vs. Cg characteristics
Ta = 25C, CL = 6 pF
IDD1
0.5
[A]
0.4
6
CL = 6 pF
1.0
30
5
4. Standby current
vs. Temperature characteristics
50
35
4
–80
0
2
4
6
Cg [pF]
8
10
–100
0
2
4
6
Cg [pF]
8
10
43
2-WIRE REAL-TIME CLOCK
S-35390A
Rev.4.2_04
7. Oscillation frequency vs. VDD characteristics
8. Oscillation frequency
vs. Temperature characteristics
Ta = 25C, Cg = 7.5 pF
Cg = 7.5 pF
50
20
40
0
30
–20
20
f/f
[ppm]
VDD = 3.0 V
–40
10
f/f
–60
[ppm]
0
–10
–80
–20
–100
–30
–120
–40
–50
VDD = 5.0 V
0
1
2
3
VDD [V]
4
5
6
9. Oscillation start time vs. Cg characteristics
–140
–40 –25
0
25
Ta [C]
50
75 85
10. Output current characteristics 1
(VOUT vs. IOL1)
INT1 pin, INT2 pin, Ta = 25C
Ta = 25C
50
500
450
40
400
350
VDD = 5.0 V
300
tSTA
250
[ms]
200
IOL1
[mA]
VDD = 5.0 V
30
VDD = 3.0 V
20
VDD = 3.0 V
150
100
10
50
0
0
2
4
6
Cg [pF]
8
10
11. Output current characteristics 2
(VOUT vs. IOL2)
0
0
1
2
VOUT [V]
4
12. BLD detection, release voltage, VDDT (min.)
vs. Temperature characteristics
SDA pin, Ta = 25C
50
CL = 6 pF
1.4
Release voltage
1.2
40
IOL2
[mA]
3
1.0
VDD = 5.0 V
30
20
Detection voltage
0.8
BLD
[V] 0.6
VDD = 3.0 V
VDDT (min.)
0.4
10
0
44
0.2
0
0.5
1
1.5
VOUT [V]
2
2.5
0
–40 –25
0
25
Ta [C]
50
75 85
5.02±0.2
8
5
1
4
1.27
0.20±0.05
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø2.0±0.05
8.0±0.1
2.1±0.1
6.7±0.1
1
8
4
5
Feed direction
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
2,000
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
+0.3
3.00 -0.2
8
5
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
8.0±0.1
ø1.55 -0.05
(4.4)
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.25±0.05
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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