S-5470A21I-M5T1U

S-5470 Series www.ablic.com www.ablicinc.com ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 © ABLIC Inc., 2012-2016 The S-5470 Series, developed by CMOS technology, is a normally-off faint signal detection IC with an ultra-low current consumption. This IC has a function to detect certain current level of 0.7 nA typ., which makes it possible to detect faint signals for a variety of electric generating devices or sensor devices. It also has a function to detect the difference of current level, and thus detects difference between strengths of two signals input at the same time. Due to its ultra-low current consumption and low-voltage operation, the S-5470 Series is suitable for battery-operated small mobile device applications.  Features       Ultra-low current consumption: Faint current detection: Wide operation voltage range: Detection of faint signal: Detection of signal strength difference: Lead-free (Sn 100%), halogen-free IDD  0.1 nA typ. IDET = 0.7 nA typ. VDD = 0.9 V to 5.5 V Detects faint signals of approximately 0.7 nW (1.0 V, 0.7 nA typ.) Detects difference between strengths of two signals input at the same time  Applications  Detects output signals of electric generating devices or sensor devices with high internal resistance  Advanced sensing using two electric generating devices or sensor devices  Miniaturization and low power consumption for various sensors of portable and wireless devices  Package  SOT-23-5 1 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Block Diagrams 1. CMOS output product VDD *1 *1  INP *1 Current adder  Current amplifier INM *1 IDET  Current comparator Logic selection OUT  *1 VSS *1. Parasitic diode Figure 1 2. Nch open-drain output product VDD *1  INP *1 Current amplifier INM *1 Current adder  IDET  Current comparator *1 Parasitic diode Figure 2 2 OUT  VSS *1. Logic selection ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Product Name Structure Users can select the output form and output logic for the S-5470 Series. Refer to "1. Product name" regarding the contents of the product name, "2. Package" regarding the package drawings, "3. Product name list" regarding details of the product name. 1. Product name S-5470 x 21 I - M5T1 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 M5T1: SOT-23-5, Tape Operation temperature I: Ta = 40C to 85C Detection mode 21: Current amplifier current amplification ratio  2 Output form and output logic A: CMOS output (Active "H") B: CMOS output (Active "L") C: Nch open-drain output (Active "H") D: Nch open-drain output (Active "L") *1. 2. Refer to the tape drawing. Package Table 1 Package Name SOT-23-5 3. Package Drawing Codes Dimension MP005-A-P-SD Tape MP005-A-C-SD Reel MP005-A-R-SD Product name list Table 2 Product Name Output Form Output Logic Detection Mode S-5470A21I-M5T1U CMOS output Active "H" Current amplifier current amplification ratio  S-5470B21I-M5T1U CMOS output Active "L" Current amplifier current amplification ratio  S-5470C21I-M5T1U Nch open-drain output Active "H" Current amplifier current amplification ratio  S-5470D21I-M5T1U Nch open-drain output Active "L" Current amplifier current amplification ratio  Remark Please contact our sales office for products other than the above. 2 2 2 2 3 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Pin Configuration 1. SOT-23-5 Top view 5 4 1 2 3 Figure 3 4 Table 3 Pin No. 1 2 3 4 5 Symbol VDD VSS INM INP OUT Description Power supply pin GND pin Reference current input pin Detection current input pin Output pin ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Absolute Maximum Ratings Table 4 Item Power supply voltage Input voltage CMOS output product Output voltage Nch open-drain output product Symbol VDD VINP, VINM VOUT ISOURCE ISINK PD Topr Tstg Output pin current Power dissipation Operation ambient temperature Storage temperature *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm  76.2 mm  t1.6 mm (2) Name: JEDEC STANDARD51-7 The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 700 Power Dissipation (PD) [mW] Caution (Ta = 25°C unless otherwise specified) Absolute Maximum Rating Unit VSS  0.3 to VSS  7.0 V VSS  0.3 to VSS  7.0 V V VSS  0.3 to VDD  0.3 VSS  0.3 to VSS  7.0 V 20 mA 20 mA 600*1 mW 40 to 85 °C 55 to 125 °C 600 500 400 300 200 100 0 Figure 4 0 150 100 50 Ambient Temperature (Ta) [C] Power Dissipation of Package (When Mounted on Board) 5 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Electrical Characteristics Table 5 Item Symbol Condition Ta = 40°C to 85°C VINP = VSS, VINM = VSS VINP = 1.0 V, VINM = VSS  0.9   0.52 IDET  0.7  0.01 0.02 0.7 IDET  0.8 5.5 10 10 0.88 IDET  0.9 V nA nA nA  1 1 2 nA 2 Ta = 40°C to 85°C  0.5  %°C  VINP = 1.0 V VINM = 1.0 V 20 10     A A 3 3 1.8 2.0 2.2 Times 4 0.01 3.5 0.5 7.0  0.4 4.8 1.7 9.2      15 mA mA mA mA ms 5 5 6 6  Power supply voltage VDD Current consumption IDD Detection current IDET Release current IREL Detection current temperature coefficient Itc Input current IINP IINM Current amplifier current amplification ratio  2 GINM Source current ISOURCE CMOS output product VOUT = VDD  0.3 V Sink current ISINK VOUT = 0.3 V Output response time tOD 6 (Ta = 25°C, VDD = 3.0 V unless otherwise specified) Test Min. Typ. Max. Unit Circuit    VDD = 0.9 V VDD = 3.0 V VDD = 0.9 V VDD = 3.0 V ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Test Circuits VDD INP INM S-5470 Series A R*1 100 k OUT VDD INP INM S-5470 Series VSS Test Circuit 1 A INM S-5470 Series Figure 6 Open INM S-5470 Series VSS A Test Circuit 2 VDD INP OUT V *1. Resistor (R) is unnecessary for the CMOS output product. VDD INP OUT VSS *1. Resistor (R) is unnecessary for the CMOS output product. Figure 5 R*1 100 k R*1 100 k OUT VSS V *1. Resistor (R) is unnecessary for the CMOS output product. Figure 7 Test Circuit 3 Figure 8 Test Circuit 4 VDD INP INM S-5470 Series VDD INP OUT A INM S-5470 Series VSS Figure 9 Test Circuit 5 OUT A VSS Figure 10 Test Circuit 6 7 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Standard Circuits 1. Certain current level detector IINP VDD INP S-5470 Series INM *1. OUT R*1 100 k 0.1 F VOUT VSS Resistor (R) is unnecessary for the CMOS output product. Figure 11 2. Current level difference detector IINP VDD INP S-5470 Series IINM INM *1. OUT R*1 100 k 0.1 F VOUT VSS Resistor (R) is unnecessary for the CMOS output product. Figure 12 Caution 8 The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Operation The S-5470 Series detects either certain current level or the difference of current level. The operation of the S-5470 Series is described below, using CMOS output and active "H" products as examples. 1. Basic operation when detecting certain current level (INM pin = VSS) The S-5470 Series operates as follows when the INM pin is connected to VSS pin. (1) If IINP is lower than IDET, an "L" level signal is output from the OUT pin. (2) If IINP increases and becomes equal to or higher than IDET, an "H" level signal is output from the OUT pin (point A in Figure 14). Even if IINP decreases and falls below IDET, as long as IINP is higher than IREL, an "H" level signal is output from the OUT pin. (3) If IINP then decreases further and becomes equal to or lower than IREL, an "L" level signal is output from the OUT pin (point B in Figure 14). IINP: Current input to the INP pin IDET: Detection current (refer to "4. 1 Detection current (IDET)") IREL: Release current (refer to "4. 2 Release current (IREL)") Remark Caution 1. There are internal diodes at the INP pin and the INM pin. Therefore, in order to input a current to the INP pin and the INM pin, an input voltage of at least the forward voltage of these diodes is required. 2. Feed-through current (IPEAK = 100 nA) flows around the time when the OUT pin voltage switches, as shown in Figure 14. Therefore, if the input current is fixed around this time, the current consumption will increase. VDD *1 IINP IINP  INP INM *1 *1. Current adder  *1 Current amplifier IDET *1  Current comparator OUT *1  VSS Parasitic diode Figure 13 Diagram of the Operation when Detecting Certain Current Level (1) IDET IINP (2) A (3) B Hysteresis width IREL OUT pin output voltage (VOUT) H L IPEAK = 100 nA Current consumption (IDD) Figure 14 Operation when Detecting Certain Current Level 9 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 2. Basic operation when detecting the difference of current level (Current amplifier current amplification ratio  GINM) The S-5470 Series operates as follows when current (IINM) is applied to the INM pin. (1) If IINP is lower than IDET  GINM  IINM, an "L" level signal is output from the OUT pin. (2) If IINP increases and becomes equal to or higher than IDET  GINM  IINM, an "H" level signal is output from the OUT pin (point A in Figure 16). Even if IINP decreases and falls below IDET  GINM  IINM, as long as IINP is higher than IREL  GINM  IINM, an "H" level signal is output from the OUT pin. (3) If IINP then decreases further and becomes equal to or lower than IREL  GINM  IINM, an "L" level signal is output from the OUT pin (point B in Figure 16). IINP: IINM: IDET: IREL: Remark Current input to the INP pin Current input to the INM pin Detection current (refer to "4. 1 Detection current (IDET)") Release current (refer to "4. 2 Release current (IREL)") Caution 1. There are internal diodes at the INP pin and the INM pin. Therefore, in order to input a current to the INP pin and the INM pin, an input voltage of at least the forward voltage of these diodes is required. 2. Feed-through current (IPEAK = 100 nA) flows around the time when the OUT pin voltage switches, as shown in Figure 16. Therefore, if the input current is fixed around this time, the current consumption will increase. VDD INP  Current adder  *1 IINM IINM INM *1 IINP IINP *1 Current amplifier IDET *1  Current comparator OUT *1  VSS *1. Parasitic diode Figure 15 Diagram of the Operation when Detecting the Difference of Current Level (1) IDET IINP  GINM  IINM (2) A (3) B Hysteresis width IREL OUT pin output voltage (VOUT) H L IPEAK = 100 nA Current consumption (IDD) Figure 16 10 Operation when Detecting the Difference of Current Level ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 3. Temperature characteristics of detection current The shaded area in Figure 17 shows the temperature characteristics of the detection voltage in the operation temperature range. IDET [nA] 0.5%/°C IDET25 *1 0.5%/°C 40 *1. 25 85 Ta [°C] IDET25: Detection current value at Ta = 25°C Figure 17 Temperature Characteristics of Detection Current 11 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 4. Explanation of terms 4. 1 Detection current (IDET) The detection current (IDET) is the current at which the output switches to "H". The detection current varies slightly even among products with the same specification. The variation in detection current from the minimum detection current (IDET min.) to the maximum detection current (IDET max.) is called the detection current range (refer to Figure 18). Detection current IDET max. Detection current range IDET min. IINP H VOUT L Figure 18 4. 2 Detection Current Release current (IREL) The release current (IREL) is the current at which the output switches to "L". The release current varies slightly even among products with the same specification. The variation in release current from the minimum release current (IREL min.) to the maximum release current (IREL max.) is called the release current range (refer to Figure 19). The range is calculated from the actual detection current (IDET) of a product and is in the range of IDET  0.7  IREL  IDET  0.9. IINP Release current IREL max. Release current range IREL min. H VOUT L Figure 19 4. 3 Release Current Hysteresis width The hysteresis width is the current difference between the detection current and the release current (current at point B  current at point A in "Figure 14 Operation when Detecting Certain Current Level" and "Figure 16 Operation when Detecting the Difference of Current Level"). The hysteresis width between the detection current and the release current prevents malfunction caused by noise in the input current. 12 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Application Circuits 1. Certain photocurrent level detector If PD or LED exceeds a certain value, the output signal inverts. 0.1 F VDD INP INM S-5470 Series OUT VOUT VSS D1 Figure 20 Example Certain Photocurrent Level Detector (CMOS Output Product) VDD INP INM S-5470 Series OUT R 100 k 0.1 F VOUT VSS D1 Figure 21 Caution Example Certain Photocurrent Level Detector (Nch Open-drain Output Product) The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 13 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 2. Photocurrent level difference detector If the difference in the photocurrent generated by the two PDs or the two LEDs exceeds a certain value, the output signal inverts. 0.1 F VDD INP INM S-5470 Series OUT VOUT VSS D1 Figure 22 D2 Example Photocurrent Level Difference Detector (CMOS Output Product) VDD INP INM S-5470 Series OUT R 100 k 0.1 F VOUT VSS D1 Figure 23 Caution 14 D2 Example Photocurrent Level Difference Detector (Nch Open-drain Output Product) The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 3. Selection of PD or LED Use PD or LED whose generation voltage is 1.0 V or more under usable light quantity. Moreover, as for the test circuit shown in Figure 24, select PD or LED that satisfies the conditions below with detection or measurement of the quantity of light incidence in usage environment.  Certain photocurrent level detector IDET  I  Photocurrent level difference detector 1 nA  I  20 A I Light incidence A D1, D2 1V Figure 24 Caution 1. 2. Select PD or LED after thorough evaluation with actual application. ABLIC Inc. shall not take responsibility for operation and characteristics of PD or LED. As for the circuit of detecting photocurrent difference, shown in Figure 22 and Figure 23, use the two PDs or the two LEDs that have the same characteristics in generation voltage and in generation current, respectively. 15 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Precautions  Use the S-5470 Series with the output current of 20 mA or less.  The S-5470 Series may malfunction if the power supply voltage changes suddenly.  As for the detecting circuit of the photocurrent difference (Refer to "Figure 22, Figure 23 Example Photocurrent Level Difference Detector"), use the S-5470 Series when input current of INP pin is 20 A or less and input current of INM pin is 10 A or less. In case of input current excess, note that the S-5470 Series might malfunction.  The output in the S-5470 Series is unstable in lower voltage than the minimum operation voltage. At the time of power-on, use the S-5470 Series after output stabilization.  Set a capacitor of 0.1 F or more between the VDD pin and VSS pin for stabilization.  Since INP pin and INM pin is easy to be affected by disturbance noise, perform countermeasures such as mounting external parts to ICs as close as possible.  If power impedance is high, the S-5470 Series may malfunction due to voltage drop caused by feed-through current. Set wire patterns carefully for lower power impedance.  Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.  ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 16 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Characteristics (Typical Data) 1. Detection current vs. Temperature 2. Detection current vs. Power supply voltage Ta = 25C 1.0 0.8 0.8 0.6 0.4 0.2 3. IDET [nA] IDET [nA] VDD = 3.0 V 1.0 0.6 0.4 0.2 −40 −25 0 0 25 Ta [°C] 50 75 85 Release current vs. Temperature 0 4. 1 2 3 VDD [V] 4 Ta = 25C 1.0 0.8 0.8 0.2 0.6 0.4 0.2 −40 −25 0 0 25 Ta [°C] 50 75 85 0 1 2 3 VDD [V] 4 5 6 Current consumption vs. Temperature VDD = 3.0 V 3.0 VINP = 1 V IDD [nA] 5. IREL [nA] IREL [nA] VDD = 3.0 V 0.4 6 Release current vs. Power supply voltage 1.0 0.6 5 2.0 VINP = 0 V 1.0 0 −40 −25 0 25 Ta [°C] 50 75 85 17 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 6. Current consumption vs. Power supply Ta = 25C S-5470A21I 0.06 VINP = 1 V 0.03 0.02 0.01 0 1 2 3 VDD [V] 4 5 VINP = 0 V 0.02 0.01 1 2 3 4 5 6 VDD [V] Current amplifier current amplication ratio vs. Temperature VDD = 3.0 V 2.4 GINM [times] 2 3 VDD [V] 4 5 6 Ta = 25C S-5470D21I 0.06 VINP = 0 V 0.04 0.03 VINP = 1 V 0.02 0 0 18 1 0.01 0 2.2 2.0 1.8 1.6 VINP = 1 V 0.05 0.04 0.03 0.02 0 VINP = 1 V 0.05 VINP = 0 V 0.03 0 6 Ta = 25C S-5470C21I 0.06 0.04 0.01 VINP = 0 V 0 IDD [nA] IDD [nA] 0.05 0.04 IDD [nA] IDD [nA] 0.05 7. Ta = 25C S-5470B21I 0.06 −40 −25 0 25 Ta [°C] 50 75 85 0 1 2 3 VDD [V] 4 5 6 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series 8. Output response time vs. Power supply voltage Ta = 25C S-5470A21I 1.25 VINP = 1 V → 0 V 1.00 tOD [ms] tOD [ms] 1.00 0.75 0.50 VINP = 0 V → 1 V 0.25 Ta = 25C S-5470B21I 1.25 VINP = 0 V → 1 V 0.75 0.50 VINP = 1 V → 0 V 0.25 0 0 1 2 3 4 5 0 6 0 1 2 VDD [V] Ta = 25C S-5470C21I 1.25 VINP = 1 V → 0 V 0.75 tOD [ms] tOD [ms] 5 6 Ta = 25C 1.00 0.50 VINP = 0 V → 1 V 0.25 VINP = 0 V → 1 V 0.75 0.50 VINP = 1 V → 0 V 0.25 0 0 0 1 2 3 4 5 0 6 1 2 VDD [V] Source current vs. Power supply voltage 10. 3 VDD [V] 4 5 6 Sink current vs. Power supply voltage 20 10 8 Ta = −40°C 6 Ta = +25°C ISINK [mA] ISOURCE [mA] 4 S-5470D21I 1.25 1.00 9. 3 VDD [V] 4 Ta = +85°C 2 0 Ta = −40°C 15 Ta = +25°C 10 5 Ta = +85°C 0 0 1 2 3 VDD [V] 4 5 6 0 1 2 3 4 5 6 VDD [V] 19 ULTRA-LOW CURRENT CONSUMPTION NORMALLY-OFF FAINT SIGNAL DETECTION IC Rev.1.3_02 S-5470 Series  Marking Specification 1. SOT-23-5 Top view 5 (1) to (3): (4): 4 (1) (2) (3) (4) 1 2 3 Product name vs. Product code Product Code Product Name (1) (2) (3) S-5470A21I-M5T1U S-5470B21I-M5T1U S-5470C21I-M5T1U S-5470D21I-M5T1U 20 Y Y Y Y H H H H A I Q Y Product code (Refer to Product name vs. Product code) Lot number 2.9±0.2 1.9±0.2 4 5 1 2 +0.1 0.16 -0.06 3 0.95±0.1 0.4±0.1 No. MP005-A-P-SD-1.3 TITLE SOT235-A-PKG Dimensions No. MP005-A-P-SD-1.3 ANGLE UNIT mm ABLIC Inc. 4.0±0.1(10 pitches:40.0±0.2) +0.1 ø1.5 -0 +0.2 ø1.0 -0 2.0±0.05 0.25±0.1 4.0±0.1 1.4±0.2 3.2±0.2 3 2 1 4 5 Feed direction No. MP005-A-C-SD-2.1 TITLE SOT235-A-Carrier Tape No. MP005-A-C-SD-2.1 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. MP005-A-R-SD-1.1 SOT235-A-Reel TITLE No. MP005-A-R-SD-1.1 ANGLE QTY. UNIT mm ABLIC Inc. 3,000 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. 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Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com