S-8233ADFT-TB-U

S-8233A Series BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK www.sii-ic.com N Rev.6.0_01 DE SI G © Seiko Instruments Inc., 1997-2013 The S-8233A Series is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy voltage detection circuits and delay circuits. It is suitable for a 3-serial-cell lithium-ion rechargeable battery pack. „ Features (1) Internal high-accuracy voltage detection circuit y Overcharge detection voltage (9) DE MM EN (2) (3) (4) (5) (6) (7) (8) D FO R NE W 4.10 ± 0.05 V to 4.35 ± 0.05 V 50 mV- step y Overcharge release voltage 3.85 ± 0.10 V to 4.35 ± 0.10 V 50 mV- step (The overcharge release voltage can be selected within the range where a difference from overcharge detection voltage is 0 V to 0.3 V) y Overdischarge detection voltage 2.00 ± 0.08 V to 2.70 ± 0.08 V 100 mV- step y Overdischarge release voltage 2.00 ± 0.10 V to 3.70 ± 0.10 V 100 mV - step (The overdischarge release voltage can be selected within the range where a difference from overdischarge detection voltage is 0 V to 1.0 V) y Overcurrent detection voltage 1 0.15 ± 0.015 V to 0.50 ± 0.05 V 50 mV-step High-withstand voltage device (absolute maximum rating: 26 V) Wide operating voltage range: 2 V to 24 V The delay time for every detection can be set via an external capacitor. Three overcurrent detection levels (protection for short-circuiting) Internal charge/discharge prohibition circuit via the control pin The function for charging batteries from 0 V is available. Low current consumption y Operation 50 μA max. (+25 °C) y Power-down 0.1 μA max. (+25 °C) Lead-free, Sn 100%, halogen-free*1 „ Applications CO *1. Refer to “„ Product Name Structure” for details. NO T „ Package RE y Lithium-ion rechargeable battery packs y Lithium polymer rechargeable battery packs y 16-Pin TSSOP Seiko Instruments Inc. 1 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 Reference voltage 1 Overcurrent 2,3 delay circuit + − CD1 Battery 1 Overcharge + W VC1 Battery 1 Overdischarge Battery 1 Overcharge Control + CD2 Logic Battery 2 Overcharge FO + R − NE − − Overcurrent detection circuit VMP Overcurrent1, delay circuit COVT Overdischarge delay circuit CDT DE SI G VCC N „ Block Diagram Overcharge delay circuit CCT VC2 + Battery 3 Overcharge MM EN − CD3 DOP DE Battery 2 Overcharge D Battery 2 Overdischarge Reference voltage 2 COP + − Battery 3 Overdischarge Reference voltage 3 2 Floating detection circuit CTL Figure 1 The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor. NO T Remark Battery 3 Overcharge RE CO VSS Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Product Name Structure x FT − TB − x DE SI G S-8233A N 1. Product name Environmental code U : Lead-free (Sn 100%), halogen-free G : Lead-free (for details, please contact our sales office) IC direction in tape specifications*1 Package name (abbreviation) FT: 16-Pin TSSOP W Serial code Assigned from A to Z in alphabetical order NE *1. Refer to the tape specifications. R 2. Package FO Package Name Package FT016-A-P-SD Reel FT016-A-R-SD D 16-Pin TSSOP Drawing Code Tape FT016-A-C-SD 3. Product name list DE Table 1 NO T RE CO MM EN Overcharge Overcharge Overdischarge Overdischarge Overcurrent 0 V battery release detection release detection detection Conditioning Product name / Item charge voltage voltage voltage voltage1 voltage function function VCD VDD VDU VIOV1 VCu Available S-8233ACFT-TB-x 4.25 V 4.05 V 2.00 V 2.30 V 0.20 V − Unavailable S-8233ADFT-TB-x 4.10 V 4.10 V 2.00 V 2.30 V 0.20 V − Available S-8233AEFT-TB-x 4.25 V 4.10 V 2.30 V 2.70 V 0.15 V − S-8233AFFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.50 V Available Available S-8233AGFT-TB-x 4.25 V 4.05 V 2.40 V 2.70 V 0.40 V Available Available Available S-8233AIFT-TB-x 4.25 V 4.10 V 2.30 V 3.00 V 0.15 V − Available S-8233AJFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.30 V − Available S-8233AKFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.15 V − S-8233ALFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.40 V Available Available S-8233AMFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.30 V Available Available S-8233ANFT-TB-x 4.35 V 4.05 V 2.40 V 2.40 V 0.15 V Available Available S-8233AOFT-TB-x 4.35 V 4.05 V 2.40 V 2.70 V 0.15 V Available Available S-8233APFT-TB-x 4.25 V 4.05 V 2.70 V 3.00 V 0.30 V Available Available S-8233ARFT-TB-x 4.35 V 4.05 V 2.00 V 2.70 V 0.30 V Available Available S-8233ASFT-TB-x 4.25 V 4.05 V 2.40 V 2.70 V 0.50 V Available Available Remark 1. Please contact our sales office for the products with the detection voltage value other than those specified above. 2. x: G or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products. Seiko Instruments Inc. 3 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Pin Configuration 1 2 3 4 5 6 7 8 VCC NC CD1 VC1 CD2 VC2 CD3 CTL 16 15 14 13 12 11 10 9 FO R NE W Figure 2 DE SI G DOP NC COP VMP COVT CDT CCT VSS N 16-Pin TSSOP Top view Table 2 Pin No. Symbol Description 1 DOP Connects FET gate for discharge control (CMOS output) *1 2 NC No connection 3 COP Connects FET gate for charge control (Nch open-drain output) 4 VMP Detects voltage between VCC to VMP(Overcurrent detection pin) 5 COVT Connects capacitor for overcurrent detection1 delay circuit 6 CDT Connects capacitor for overdischarge detection delay circuit 7 CCT Connects capacitor for overcharge detection delay circuit 8 VSS Negative power input, and connects negative voltage for battery 3 9 CTL Charge/discharge control signal input 10 CD3 Battery 3 conditioning signal output 11 VC2 Connects battery 2 negative voltage and battery 3 positive voltage 12 CD2 Battery 2 conditioning signal output 13 VC1 Connects battery 1 negative voltage and battery 2 positive voltage CD1 Battery 1 conditioning signal output 14 *1 15 NC No connection 16 VCC Positive power input and connects battery 1 positive voltage NO T RE CO MM EN DE D *1. The NC pin is electrically open. The NC pin can be connected to VCC or VSS. 4 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Absolute Maximum Ratings Table 3 (Ta = 25°C unless otherwise specified) Absolute Maximum Ratings Unit VSS−0.3 ~ VSS+26 V N Applied Pin − DE SI G Item Symbol Input voltage between VCC and VSS VDS VSS−0.3 ~ VCC+0.3 VVMP VMP VSS−0.3 ~ VSS+26 V CD1 output pin voltage VCD1 CD1 VC1−0.3 ~ VCC+0.3 V CD2 output pin voltage VCD2 CD2 VC2−0.3 ~ VCC+0.3 V CD3 output pin voltage VCD3 CD3 VSS−0.3 ~ VCC+0.3 V DOP output pin voltage VDOP DOP VSS−0.3 ~ VCC+0.3 V COP output pin voltage VCOP COP VSS−0.3 ~ VSS+26 V Power dissipation PD Operating ambient temperature Topr NE VMP Input pin voltage − 300 (When not mounted on board) − − *1 1100 V mW mW −20 ~ +70 °C −40 ~ +125 °C D FO Tstg − Storage temperature *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7 R VIN W VC1, VC2, CTL, CCT, CDT, COVT Input pin voltage Power Dissipation (PD) [mW] 1400 MM EN 1200 DE Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. RE CO 1000 800 600 400 200 0 0 50 100 150 Ambient Temperature (Ta) [°C] NO T Figure 3 Power Dissipation of Package (When Mounted on Board) Seiko Instruments Inc. 5 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Electrical Characteristics Table 4 (1 / 2) Typ. VCU1 VCD1 VDD1 VDU1 VCU2 VCD2 VDD2 VDU2 VCU3 VCD3 VDD3 VDU3 VIOV1 VIOV2 VIOV3 TCOE1 TCOE2 4.10 to 4.35 Adjustment 3.85 to 4.35 Adjustment 2.00 to 2.70 Adjustment 2.00 to 3.70 Adjustment 4.10 to 4.35 Adjustment 3.85 to 4.35 Adjustment 2.00 to 2.70 Adjustment 2.00 to 3.70 Adjustment 4.10 to 4.35 Adjustment 3.85 to 4.35 Adjustment 2.00 to 2.70 Adjustment 2.00 to 3.70 Adjustment 0.15 to 0.50V Adjustment VCC Reference VSS Reference Ta = -20 to 70°C*4 Ta = -20 to 70°C*4 VCU1−0.05 VCD1−0.10 VDD1−0.08 VDU1−0.10 VCU2−0.05 VCD2−0.10 VDD2−0.08 VDU2−0.10 VCU3−0.05 VCD3−0.10 VDD3−0.08 VDU3−0.10 VIOV1 x 0.9 0.54 1.0 −1.0 −0.5 VCU1 VCD1 VDD1 VDU1 VCU2 VCD2 VDD2 VDU2 VCU3 VCD3 VDD3 VDU3 VIOV1 0.6 2.0 0 0 tCU1 tCU2 tCU3 tDD1 tDD2 tDD3 tIOV1 tIOV2 tIOV3 CCCT = 0.47 μF CCCT = 0.47 μF CCCT = 0.47 μF CCDT = 0.1 μF CCDT = 0.1 μF CCDT = 0.1 μF CCOVT = 0.1 μF − FET gate capacitor = 2000 pF 0.5 0.5 0.5 20 20 20 10 2 100 1.0 1.0 1.0 40 40 40 20 4 300 1.5 1.5 1.5 60 60 60 30 8 550 − 2.0 − IOPE V1 = V2 = V3 = 3.5 V − ICELL2 ICELL3 IPDN V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 1.5 V V1 = V2 = V3 = 3.5 V *6 V1 = V2 = V3 = 3.5 V V1 = V2 = V3 = 1.5 V *6 V1 = V2 = V3 = 1.5 V NO T RE CO VDSOP Resistance between VSS and VMP Input voltage CTL"H" Input voltage CTL"L" Input voltage 6 RVCM RVSM VCTL(H) VCTL(L) Unit Test Test Condition Circuit 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 − − s s s ms ms ms ms ms μs 9 10 11 9 10 11 12 12 12 6 6 6 6 6 6 7 7 7 24 V − − 20 50 μA 5 3 −300 −300 − 0 0 − 300 300 0.1 nA nA μA 5 5 5 3 3 3 0.40 0.20 0.40 0.20 0.90 0.50 0.90 0.50 1.40 0.80 1.40 0.80 MΩ MΩ MΩ MΩ 6 6 6 6 3 3 3 3 VCCx0.8 − − − − VCCx0.2 V V − − − − NE R Seiko Instruments Inc. VCU1+0.05 V VCD1+0.10 V VDD1+0.08 V VDU1+0.10 V VCU2+0.05 V VCD2+0.10 V VDD2+0.08 V VDU2+0.10 V VCU3+0.05 V VCD3+0.10 V VDD3+0.08 V VDU3+0.10 V VIOV1 x 1.1 V 0.66 V 3.0 V 1.0 mV/°C 0.5 mV/°C W 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 − − FO − − Max. DE SI G Min. MM EN Detection voltage Overcharge detection voltage 1 Overcharge release voltage 1 Overdischarge detection voltage 1 Overdischarge release voltage 1 Overcharge detection voltage 2 Overcharge release voltage 2 Overdischarge detection voltage 2 Overdischarge release voltage 2 Overcharge detection voltage 3 Overcharge release voltage 3 Overdischarge detection voltage 3 Overdischarge release voltage 3 Overcurrent detection voltage 1*1 Overcurrent detection voltage 2 Overcurrent detection voltage 3 Voltage temperature factor 1*2 Voltage temperature factor 2*3 Delay time Overcharge detection delay time 1 Overcharge detection delay time 2 Overcharge detection delay time 3 Overdischarge detection delay time 1 Overdischarge detection delay time 2 Overdischarge detection delay time 3 Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 Operating voltage Operating voltage between VCC and VSS*5 Current consumption Current consumption (during normal operation) Current consumption for cell 2 Current consumption for cell 3 Current consumption at power down Internal resistance Resistance between VCC and VMP Condition D Symbol DE Item N (Ta = 25°C unless otherwise specified) BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 Table 4 (2 / 2) (Ta = 25°C unless otherwise specified) Typ. VDO(H) VDO(L) VCO(L) ICOL VCD1(H) VCD1(L) VCD2(H) VCD2(L) VCD3(H) VCD3(L) IOUT = 10 μA IOUT = 10 μA IOUT = 10 μA V1 = V2 = V3 = 4.5 V IOUT = 0.1 μA IOUT = 10 μA IOUT = 0.1 μA IOUT = 10 μA IOUT = 0.1 μA IOUT = 10 μA VCC-0.5 − − − VCC -0.5 − VCC -0.5 − VCC -0.5 − − − − − − − − − − − V0CHAR −*6 − Max. − Unit Test Test Condition Circuit N Min. DE SI G Output voltage DOP"H" voltage DOP"L" voltage COP"L" voltage COP OFF LEAK current CD1"H" voltage CD1"L" voltage CD 2"H" voltage CD 2"L" voltage CD3"H" voltage CD3"L" voltage 0 V battery charging function 0 V charging start voltage Condition − VSS+0.1 VSS+0.1 100 − VC1+0.1 VC2+0.1 − VSS+0.1 V V V nA V V V V V V 7 7 8 14 13 13 13 13 13 13 4 4 5 9 8 8 8 8 8 8 1.4 V 15 10 W Symbol NE Item NO T RE CO MM EN DE D FO R *1. If overcurrent detection voltage 1 is 0.50 V, both overcurrent detection voltages 1 and 2 are 0.54 to 0.55 V, but VIOV2 > VIOV1. *2. Voltage temperature factor 1 indicates overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, and overdischarge release voltage. *3. Voltage temperature factor 2 indicates overcurrent detection voltage. *4. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. *5. The DOP and COP logic must be established for the operating voltage. *6. This spec applies for only 0 V battery charging function available type. Seiko Instruments Inc. 7 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Test Circuits DE SI G N (1) Test condition 1 Test circuit 1 Set V1, V2, and V3 to 3.5 V under normal status. Increase V1 from 3.5 V gradually. The V1 voltage when COP = 'H' is overcharge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage when COP = 'L' is overcharge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when DOP = 'H' is overdischarge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L' is overdischarge release voltage 1 (VDU1). Remark The voltage change rate is 150 V/s or less. R NE W (2) Test condition 2 Test circuit 1 Set V1, V2, and V3 to 3.5 V under normal status. Increase V2 from 3.5 V gradually. The V2 voltage when COP = 'H' is overcharge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage when COP = 'L' is overcharge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when DOP = 'H' is overdischarge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L' is overdischarge release voltage 2 (VDU2). Remark The voltage change rate is 150 V/s or less. DE D FO (3) Test condition 3 Test circuit 1 Set V1, V2, and V3 to 3.5 V under normal status. Increase V3 from 3.5 V gradually. The V3 voltage when COP = 'H' is overcharge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage when COP = 'L' is overcharge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when DOP = 'H' is overdischarge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L' is overdischarge release voltage 3 (VDU3). Remark The voltage change rate is 150 V/s or less. CO MM EN (4) Test condition 4 Test circuit 2 Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal status. Increase V4 from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H', is overcurrent detection voltage 1 (VIOV1). Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal status. Fix the COVT pin at VSS, increase V4 from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H' is overcurrent detection voltage 2 (VIOV2). Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal status. Fix the COVT pin at VSS, increase V4 gradually from 0 V at 400 μs to 2 ms. The V4 voltage when DOP = 'H' and COP = 'H' is overcurrent detection voltage 3 (VIOV3). NO T RE (5) Test condition 5 Test circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal status and measure current consumption. I1 is the normal status current consumption (IOPE), I2, the cell 2 current consumption (ICELL2), and I3, the cell 3 current consumption (ICELL3). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.5 V under overdischarge status. Current consumption I1 is power-down current consumption (IPDN). (6) Test condition 6 Test circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 10.5 V under normal status. V4/I4 is the internal resistance between VCC and VMP (RVCM). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.1 V under overdischarge status. (4.5-V4)/I4 is the internal resistance between VSS and VMP (RVSM). 8 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 DE SI G N (7) Test condition 7 Test circuit 4 Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal status. Increase V5 from 0 V gradually. The V5 voltage when I1 = 10 μA is DOP'L' voltage (VD0(L)). Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V4 to VIOV2+0.1 V under overcurrent status. Increase V6 from 0 V gradually. The V6 voltage when I2 = 10 μA is the DOP'H' voltage (VDO(H)). W (8) Test condition 8 Test circuit 5 Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal status. Increase V5 from 0 V gradually. The V5 voltage when I1 = 10 μA is the COP'L' voltage (VC0(L)). R NE (9) Test condition 9 Test circuit 6 Set V1, V2, V3 to 3.5 V under normal status. Increase V1 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V1 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 1 (tCU1). Set V1, V2, V3 to 3.5 V under normal status. Decrease V1 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V1 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 1 (tDD1). DE D FO (10) Test condition 10 Test circuit 6 Set V1, V2, V3 to 3.5 V under normal status. Increase V2 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V2 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 2 (tCU2). Set V1, V2, V3 to 3.5 V under normal status. Decrease V2 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V2 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 2 (tDD2). MM EN (11) Test condition 11 Test circuit 6 Set V1, V2, V3 to 3.5 V under normal status. Increase V3 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V3 becomes 4.5 V until COP goes 'H' is the overcharge detection delay time 3 (tCU3). Set V1, V2, V3 to 3.5 V under normal status. Decrease V3 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V3 becomes 1.9 V until DOP goes 'H' is the overdischarge detection delay time 3 (tDD3). NO T RE CO (12) Test condition 12 Test circuit 7 Set V1, V2, V3 to 3.5 V and S1 to OFF under normal status. Increase V4 from 0 V to 0.55 V immediately (within 10 μs). The time after V4 becomes 0.55 V until DOP goes 'H' is the overcurrent detection delay time 1 (tI0V1). Set V1, V2, V3 to 3.5 V and S1 to OFF under normal status. Increase V4 from 0 V to 0.75 V immediately (within 10 μs). The time after V4 becomes 0.75 V until DOP goes 'H' is the overcurrent detection delay time 2 (tIOV2) Set S1 to ON to inhibit overdischarge detection. Set V1, V2, V3 to 4.0 V and increase V4 from 0 V to 6.0 V immediately (within 1 μs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V4 becomes 6.0 V until DOP goes 'H' is the overcurrent detection delay time 3 (tIOV3). Seiko Instruments Inc. 9 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 D FO R NE W DE SI G N (13) Test condition 13 Test circuit 8 Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V4, V6, and V7 to 0 V under normal status. Increase V5 from 0 V gradually. The V5 voltage when I2 = 10 μA is the CD1'L' voltage (VCD1(L)) Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V7 to 0 V under normal status. Increase V6 from 0 V gradually. The V6 voltage when I3 = 10 μA is the CD2'L' voltage (VCD2(L)). Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V6 to 0 V under normal status. Increase V7 from 0 V gradually. The V7 voltage when I4 = 10 μA is the CD3'L' voltage (VCD3(L)). Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the CD1'H' voltage (VCD1(H)). Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the CD2'H' voltage (VCD2(H)). Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V under overcharge status. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the CD3'H' voltage (VCD3(H)). DE (14) Test condition 14 Test circuit 9 Set V1, V2, and V3 to 4.5 V under overcharge status. The current I1 flowing to COP pin is COP OFF LEAK current (ICOL). NO T RE CO MM EN (15) Test condition 15 Test circuit 10 Set V1, V2, and V3 to 0 V, and V8 to 2 V, and decrease V8 gradually. The V8 voltage when COP = 'H' (VSS + 0.1 V or higher) is the 0V charge start voltage (V0CHAR). 10 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 V4 1 MΩ DOP VMP V1 CTL CD2 CDT VC2 V3 CD3 CCT S-8233A CD2 COVT VSS W V3 V2 CDT VC2 CTL VC1 CCT S-8233A VMP CD1 VC1 V2 COP VCC DE SI G CD1 N COP DOP VCC V1 1 MΩ CD3 COVT NE VSS Test circuit 1 Test circuit 2 V5 R I4 COP DOP I1 FO S1 V4 VCC VMP CD1 CTL VC1 V2 I3 VC2 V3 CD3 VSS CCT S-8233A S2 I2 VMP CD1 CTL V3 CD3 V2 V3 Test circuit 4 1 MΩ V4 DOP VMP V1 CTL COP VCC VMP CD1 CTL VC1 VC1 CD2 COVT VSS COP CD1 NO T V1 CDT VC2 COVT CO DOP VCC CCT S-8233A CD2 CDT RE I1 COP VCC Test circuit 3 V5 V4 VC1 V2 MM EN CD2 V1 DE I2 I1 DOP D V1 S1 V6 S-8233A VC2 V2 CCT CDT V3 CD3 COVT S-8233A CCT VC2 C1 = 0.47 μF CDT CD3 C2 = 0.1 μF C3 = 0.1 μF CD2 COVT C1 C2 C3 VSS VSS Test circuit 6 Test circuit 5 Figure 4 (1 / 2) Seiko Instruments Inc. 11 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 V4 1 MΩ VMP V1 CD1 V1 CTL S4 VC1 CDT S5 C3 VSS R VMP CD1 CTL FO COP VC1 CDT CD3 COVT MM EN VSS D CCT DE S-8233A VC2 V3 Test circuit 9 NO T RE CO Figure 4 (2 / 2) 12 CDT CD3 I4 V7 COVT VSS V8 VCC CD2 VC2 Test circuit 8 I1 V2 CCT S-8233A NE Test circuit 7 DOP CD2 I3 V6 V3 S6 COVT CTL VC1 S3 C2 C2 = 0.1 μF C3 = 0.1 μF CD3 V1 I2 V5 V2 C1 S1 C1 = 0.47 μF VC2 V3 CCT S-8233A VMP CD1 S2 CD2 COP W V2 DOP VCC I1 V4 S1 N COP VCC DE SI G DOP 1 MΩ Seiko Instruments Inc. V1 1 MΩ DOP COP VCC VMP CD1 CTL VC1 V2 CD2 CCT S-8233A CDT VC2 V3 CD3 COVT VSS Test circuit 10 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Operation Remark Refer to “„ Battery Protection IC Connection Example”. DE SI G N Normal status This IC monitors the voltages of the three serially-connected batteries and the discharge current to control charging and discharging. If the voltages of all the three batteries are in the range from the overdischarge detection voltage (VDD) to the overcharge detection voltage (VCU), and the current flowing through the batteries becomes equal or lower than a specified value (the VMP pin voltage is equal or lower than overcurrent detection voltage 1), the charging and discharging FETs turn on. In this status, charging and discharging can be carried out freely. This status is called the normal status. In this status, the VMP and VCC pins are shorted by the RVCM resistor. FO R NE W Overcurrent status This IC is provided with the three overcurrent detection levels (VIOV1,VIOV2 and VIOV3) and the three overcurrent detection delay time (tIOV1,tIOV2 and tIOV3) corresponding to each overcurrent detection level. If the discharging current becomes equal to or higher than a specified value (the VMP pin voltage is equal to or higher than the overcurrent detection voltage) during discharging under normal status and it continues for the overcurrent detection delay time (tIOV) or longer, the discharging FET turns off to stop discharging. This status is called an overcurrent status. The VMP and VCC pins are shorted by the RVCM resistor at this time. The charging FET turns off. When the discharging FET is off and a load is connected, the VMP pin voltage equals the VSS potential. MM EN DE D The overcurrent status returns to the normal status when the load is released and the impedance between the EB- and EB+ pins (see Figure 9) is 100 MΩ or higher. When the load is released, the VMP pin, which and the VCC pin are shorted with the RVCM resistor, goes back to the VCC potential. The IC detects that the VMP pin potential returns to overcurrent detection voltage 1 (VIOV1) or lower (or the overcurrent detection voltage 2 (VIOV2) or lower if the COVT pin is fixed at the 'L' level and overcurrent detection 1 is inhibited) and returns to the normal status. NO T RE CO Overcharge status If one of the battery voltages becomes higher than the overcharge detection voltage (VCU) during charging under normal status and it continues for the overcharge detection delay time (tCU) or longer, the charging FET turns off to stop charging. This status is called the overcharge status. The 'H' level signal is output to the conditioning pin corresponding to the battery which exceeds the overcharge detection voltage until the battery becomes equal to lower than the overcharge release voltage (VCD). The battery can be discharged by connecting an Nch FET externally. The discharging current can be limited by inserting R11, R12 and R13 resistors (see Figure 9). The VMP and VCC pins are shorted by the RVCM resistor under the overcharge status. The overcharge status is released in two cases: The battery voltage which exceeded the overcharge detection voltage (VCU) falls below the overcharge release voltage (VCD), the charging FET turns on and the normal status returns. If the battery voltage which exceeded the overcharge detection voltage (VCU) is equal or higher than the overcharge release voltage (VCD), but the charger is removed, a load is placed, and discharging starts, the charging FET turns on and the normal status returns. The release mechanism is as follows: the discharge current flows through an internal parasitic diode of the charging FET immediately after a load is installed and discharging starts, and the VMP pin voltage decreases by about 0.6 V from the VCC pin voltage momentarily. The IC detects this voltage (overcurrent detection voltage 1 or higher), releases the overcharge status and returns to the normal status. Seiko Instruments Inc. 13 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 DE SI G N Overdischarge status If any one of the battery voltages falls below the overdischarge detection voltage (VDD) during discharging under normal status and it continues for the overdischarge detection delay time (tDD) or longer, the discharging FET turns off and discharging stops. This status is called the overdischarge status. When the discharging FET turns off, the VMP pin voltage becomes equal to the VSS voltage and the IC's current consumption falls below the power-down current consumption (IPDN). This status is called the power-down status. The VMP and VSS pins are shorted by the RVSM resistor under the overdischarge and power-down statuses. W The power-down status is canceled when the charger is connected and the voltage between VMP and VSS is 3.0 V or higher (overcurrent detection voltage 3). When all the battery voltages becomes equal to or higher than the overdischarge release voltage (VDU) in this status, the overdischarge status changes to the normal status. FO R NE Delay circuits The overcharge detection delay time (tCU1 to tCU3), overdischarge detection delay time (tDD1 to tDD3), and overcurrent detection delay time 1 (tIOV1) are changed with external capacitors (C4 to C6). The delay times are calculated by the following equations: Min. Typ. Max. tCU[s] = Delay factor ( 1.07, 2.13, 3.19)×C4 [μF] tDD[s] = Delay factor ( 0.20, 0.40, 0.60)×C5 [μF] tIOV1[s] = Delay factor ( 0.10, 0.20, 0.30)×C6 [μF] DE D Caution The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor. MM EN CTL pin If the CTL pin is floated under normal status, it is pulled up to the VCC potential in the IC, and both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and discharging are also inhibited by applying the VCC pin to the CTL pin externally. At this time, the VMP and VCC pins are shorted by the RVCM resistor. When the CTL pin becomes equal to VSS potential, charging and discharging are enabled and go back to their appropriate statuses for the battery voltages. CO Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin ('L' level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations. NO T RE 0 V battery charging function This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V. When the 0 V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by connecting the charger, the charging FET gate is fixed to VSS potential. When the voltage between the gate sources of the charging FET becomes equal to or higher than the turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the discharging FET turns off and the charging current flows through the internal parasitic diode in the discharging FET. If all the battery voltages become equal to or higher than the overdischarge release voltage (VDU), the normal status returns. Caution In the products without 0 V battery charging function, the resistance between VCC and VMP and between VSS and VMP are lower than the products with 0 V battery charging function. It causes to that overcharge detection voltage increases by the drop voltage of R5 (see Figure 9) with sink current at VMP. The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0 V battery charging function. 14 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 Ex. Voltage temperature factor of overcharge detection voltage Typ. +1 mV/°C W VCU [V] DE SI G N Voltage temperature factor Voltage temperature factor 1 indicates overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, and overdischarge release voltage. Voltage temperature factor 2 indicates overcurrent detection voltage. The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 5. NE VCU25 is the overcharge detection voltage at 25°C VCU25 −20 25 70 FO R −1 mV/°C Ta [°C] NO T RE CO MM EN DE D Figure 5 Seiko Instruments Inc. 15 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Timing Chart 1. Overcharge detection V2 battery V3 battery DE SI G VCU VCD VDU Battery voltage VDD VCC DOP pin W VSS COP pin High-Z High-Z High-Z NE High-Z VSS Charger connected Load connected Delay Delay Status*1 D FO R VCHA VMP pin VCC VIOV1 VSS Delay Delay Delay & Normal status, Overcharge status, Overdischarge status, Overcurrent status, Power-down status Remark The charger is assumed to charge with a constant current. DE *1. N V1 battery VCHA indicates the open voltage of the charger. Figure 6 MM EN 2. Overdischarge detection V1 battery VCU Battery VCD VDU VDD voltage VCC CO DOP pin NO T VMP pin VSS VCHA VCC RE VSS COP pin V3 battery V2 battery High-Z VIOV1 VSS Charger connected Load connected Status*1 Delay Delay Delay Delay Delay *1. Normal status, Overcharge status, Overdischarge status, Overcurrent status, Power-down status Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger. Figure 7 16 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 3. Overcurrent detection V1, V2, and V3 batteries VCD voltage VDU DE SI G Battery N VCU VDD VCC DOP pin VSS COP pin High-Z W High-Z High-Z VSS VCC NE VMP pin VIOV1 VIOV2 VIOV3 Delay tIOV2 tIOV3 CTL pin VSSÆVCC Inhibit charging and discharging CTL pin VCCÆVSS Normal status, Overcharge status , Overdischarge status, Overcurrent status Figure 8 NO T RE CO MM EN DE *1. D Delay FO Delay tIOV1 Status* R Charger connected Load connected High-Z Seiko Instruments Inc. 17 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Battery Protection IC Connection Example EB+ FET-B R5 R6 1 MΩ FET1 C1 Nch open drain CCT VC2 CD3 FO Battery 3 C3 R FET3 R13 Overcharge delay time setting C4 S-8233A series CDT R2 1 KΩ GND: Normal operation Floating: Inhibit charging and discharging. VC1 CD2 C2 R7 CTL W FET2 Battery 2 VMP VCC CD1 R1 R12 COP NE Battery 1 R11 10 KΩ DE SI G DOP N FET-A VSS DE D R3 C5 COVT C6 Overdischarge delay time setting FET-C High: Inhibit over discharge detection. Overcurrent delay time setting EB- NO T RE CO MM EN Figure 9 [Description of Figure 9] y R11, R12, and R13 are used to adjust the battery conditioning current.The conditioning current during overcharge detection is given by Vcu (overcharge detection voltage)/R (R: resistance).To disable the conditioning function, open CD1, CD2, and CD3. y The overcharge detection delay time (tCU1 to tCU3), overdischarge detection delay time (tDD1 to tDD3), and overcurrent detection delay time (tIOV1) are changed with external capacitors (C4 to C6). See the electrical characteristics. y R6 is a pull-up resistor that turns FET-B off when the COP pin is opened. Connect a 100 kΩ to 1 MΩ resistor. y R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor. y If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the overcurrent mode. C6 must be connected to prevent it. y If capacitor C5 is not connected, the IC may enter the overdischarge status due to variations of battery voltage when the overcurrent occurs. In this case, a charger must be connected to return to the normal status. To prevent this, connect an at least 0.01 μF capacitor to C5. y If a leak current flows between the delay capacitor connection pin (CCT, CDT, or COVT) and VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less. y Overdischarge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 μA or less. If overdischarge is inhibited by using this FET, the current consumption does not fall below 0.1 μA even when the battery voltage drops and the IC enters the overdischarge detection mode. y R1, R2, and R3 must be 1 kΩ or less. y R7 is the protection of the CTL when the CTL pin voltage higher than VCC voltage. Connect a 300 Ω to 5 kΩ resister. If the CTL pin voltage never greater than the VCC voltage (ex. R7 connect to VSS), without R7 resistance is allowed . 18 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 DE SI G N Caution 1. The above constants may be changed without notice. 2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233A series with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform through evaluation using the actual application to set the constant. W „ Precautions R NE y If a charger is connected in the overdischarge status and one of the battery voltages becomes equal to or higher than the overcharge release voltage (VCU) before the battery voltage which is below the overdischarge detection voltage (VDD) becomes equal to or higher than the overdischarge release voltage (VDU), the overdischarge and overcharge statuses are entered and the charging and discharging FETs turn off. Both charging and discharging are disabled. If the battery voltage which was higher than the overcharge detection voltage (VCU) falls to the overcharge release voltage (VCD) due to internal discharging, the charging FET turns on. D FO If the charger is detached in the overcharge and overdischarge status, the overcharge status is released, but the overdischarge status remains. If the charger is connected again, the battery status is monitored after that. The charging FET turns off after the overcharge detection delay time, the overcharge and overdischarge statuses are entered. MM EN DE y If any one of the battery voltages is equal to or lower than the overdischarge release voltage (VDU) when they are connected for the first time, the normal status may not be entered. If the VMP pin voltage is made equal to or higher than the VCC voltage (if a charger is connected), the normal status is entered. y If the CTL pin floats in power-down mode, it is not pulled up in the IC, charging and discharging may not be inhibited. However, the overdischarge status becomes effective. If the charger is connected, the CTL pin is pulled up, and charging and discharging are inhibited immediately. CO y Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. NO T RE y SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. Seiko Instruments Inc. 19 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 „ Characteristics (Typical Data) 1. Detection voltage temperature characteristics VCU = 4.25 V -20 0 20 40 60 80 4.00 -40 100 Overdischarge detection voltage vs. temperature 0 20 40 60 80 100 Ta [°C] Overdischarge release voltage vs. temperature VDD = 2.35 V VDU = 2.85 V VDU [V] FO R 2.95 2.35 2.85 DE D VDD [V] -20 NE Ta [°C] 2.45 DE SI G 4.10 W 4.25 4.15 -40 VCD = 4.10 V 4.20 VCD [V] VCU [V] 4.35 N Overcharge release voltage vs. temperature Overcharge detection voltage vs. temperature 2.25 -40 -20 0 20 40 60 100 MM EN Ta [°C] 80 Overcurrent1 detection voltage vs. temperature -20 20 0 40 60 80 20 40 60 80 100 Ta [°C] 100 VIOV2 = 0.6 V 0.60 0.55 20 0 0.65 VIOV2 [V] CO -40 NO T 0.25 RE VIOV1 [V] 0.30 -20 Overcurrent2 detection voltage vs. temperature VIOV1 = 0.3 V 0.35 2.75 -40 -40 Ta [°C] -20 0 20 Ta [°C] Seiko Instruments Inc. 40 60 80 100 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 2. Current consumption temperature characteristics Current consumption vs. temperature in normal mode -40 -20 0 20 40 60 80 N DE SI G 0.5 0.0 100 -40 3. Delay time temperature characteristics Overcharge detection time vs. temperature 20 40 60 80 C = 0.1 μF VCC = 10.5 V -20 0 20 40 Ta [°C] R -20 0 20 60 80 100 40 60 80 100 Ta [°C] Overcurrent2 detection time vs. temperature VCC = 10.5 V 8 tIOV2 [ms] CO RE tIOV1 [ms] NO T 10 -40 100 40 20 -40 100 Overcurrent1 detection time vs. temperature 20 80 C = 0.1 μF VCC = 8.5 V Ta [°C] 30 60 40 FO tDD [ms] D 0 20 60 DE 1.0 MM EN tCU [s] 1.5 -20 0 Overdischarge detection time vs. temperature C = 0.47 μF VCC = 11.5 V -40 -20 NE Ta [°C] 0.5 W 25 0 VCC = 4.5 V 1.0 IPDN [nA] 50 IOPE [μA] Current consumption vs. temperature in power-down mode VCC = 10.5 V 5 2 -40 Ta [°C] -20 0 20 40 60 80 100 Ta [°C] Seiko Instruments Inc. 21 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233A Series Rev.6.0_01 Overcurrent3 (load short) detection time vs. temperature VCC = 6.0 V N DE SI G 0.25 0.10 -40 -20 0 20 40 60 80 100 W tIOV3 [ms] 0.40 NE Ta [°C] 4. Delay time vs. power supply voltage Overcurrent 3 (load short) detection time vs. power supply voltage Ta = 25°C R FO D 0.5 0 6 9 VCC [V] 12 15 MM EN 3 DE tIOV3 [ms] 1.0 NO T RE CO Caution Please design all applications of the S-8233A Series with safety in mind. 22 Seiko Instruments Inc. 9 1 8 R NE W DE SI G 16 N 5.1±0.2 DE D FO 0.17±0.05 0.22±0.08 MM EN 0.65 NO T RE CO No. FT016-A-P-SD-1.1 TITLE TSSOP16-A-PKG Dimensions No. FT016-A-P-SD-1.1 SCALE UNIT mm Seiko Instruments Inc. +0.1 4.0±0.1 ø1.5 -0 0.3±0.05 DE SI G N 2.0±0.1 8.0±0.1 W ø1.6±0.1 NE (7.2) 1.5±0.1 +0.4 1 MM EN 16 DE D 6.5 -0.2 FO R 4.2±0.2 8 9 CO Feed direction NO T RE No. FT016-A-C-SD-1.1 TITLE TSSOP16-A-Carrier Tape FT016-A-C-SD-1.1 No. SCALE UNIT mm Seiko Instruments Inc. 17.4±1.0 FO R NE W DE SI G N 21.4±1.0 D 2±0.5 ø13±0.2 NO T RE CO MM EN ø21±0.8 DE Enlarged drawing in the central part +2.0 17.4 -1.5 No. FT016-A-R-SD-2.0 TITLE TSSOP16-A- Reel No. FT016-A-R-SD-2.0 SCALE UNIT QTY. 2,000 mm Seiko Instruments Inc. N DE SI G W NE R FO D DE MM EN www.sii-ic.com The information described herein is subject to change without notice. • When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. • Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. • The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, vehicle equipment, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment, without prior written permission of Seiko Instruments Inc. • • The products described herein are not designed to be radiation-proof. CO • • NO T RE Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.