S-8233B_1

Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series The S-8233B is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy (±25 mV) voltage detection circuits and delay circuits. It is suitable for a 3-serial-cell lithium-ion battery pack. Features (1) Internal high-accuracy voltage detection circuit • Over charge detection voltage 3.80 ± 0.025 V to 4.40 ± 0.025 V 5 mV - step • Over charge release voltage 3.45 ± 0.100 V to 4.40 ± 0.100 V 5 mV - step (The over charge release voltage can be selected within the range where a difference from over charge detection voltage is 0 to 0.35 V with 50 mV - step) • Over discharge detection voltage 2.00 ± 0.08 V to 2.80 ± 0.08 V 50 mV - step Over discharge release voltage 2.00 ± 0.10 V to4.00 ± 0.10 V 50 mV - step (The over discharge release voltage can be selected within the range where a difference from over discharge detection voltage is 0 to 1.2 V with 50 mV - step) • Over current detection voltage 1 0.15 ± 0.015 V to 0.5 ± 0.05 V 50 mV - step (2) (3) (4) (5) (6) (7) (8) High input-voltage device (absolute maximum rating: 26 V) Wide operating voltage range: 2 V to 24 V The delay time for every detection can be set via an external capacitor. Three over current detection levels (protection for short-circuiting) Internal charge/discharge prohibition circuit via the control terminal The function for charging batteries from 0 V is available. Low current consumption • Operation 50 μA max. (+25°C) • Power-down 0.1 μA max. (+25°C) Lead-free products (9) Applications Lithium-ion rechargeable battery packs Package Package Name 16-PIN TSSOP Package FT016-A Drawing Code Tape FT016-A Reel FT016-A Seiko Instruments Inc. 1 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Block Diagram Rev.4.2_00 VCC Reference voltage 1 + − Battery 1 Over charge Over current 2,3 delay circuit Over current detection circuit VMP CD1 + − Battery 1 Over discharge O ver current1, delay circuit COVT VC1 Battery 1 Over charge + − Battery 2 Over charge Over discharge delay circuit CDT Control Logic Over charge delay circuit CD2 + Battery 2 Over discharge Reference voltage 2 − CCT VC2 Battery 2 Over charge + − Battery 3 Over charge DOP CD3 + Battery 3 Over discharge Reference voltage 3 − COP VSS Battery 3 Over charge Floating detection circuit CTL Figure 1 Remark The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor. 2 Seiko Instruments Inc. Rev.4.2_00 Product Name Structure 1. Product name S−8233B x FT − BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series TB − G IC direction in tape specifications*1 Package name (abbreviation) FT: 16-Pin TSSOP Serial code Assigned from A to Z in alphabetical order *1. Refer to the taping specifications. 2. Product name list Table 1 Product name / Over charge Over charge Overdischarge Overdischarge Overcurrent 0V Conditioning CTL Parameter detection release detection release voltage detection battery function logic*1 voltage voltage1 charging voltage voltage VDU VCU VIOV1 VCD VDD function S-8233BAFT-TB-G 4.225±0.025 V S-8233BCFT-TB-G 4.200±0.025 V 4.225 V*2 4.2 V 2.30±0.08 V 2.30±0.08 V 2.80±0.08 V 2.00±0.08 V 2.50±0.08 V 2.70±0.10 V 2.70±0.10 V 3.30±0.10 V 2.70±0.10 V 2.75±0.10 V 0.20±0.02 V 0.20±0.02 V 0.50±0.05 V − − − Available Unavailable Available Unavailable Available normal reverse normal reverse normal S-8233BBFT-TB-G 4.325±0.025 V 4.15±0.10 V S-8233BDFT-TB-G 4.325±0.025 V 4.15±0.10 V S-8233BEFT-TB-G 4.080±0.025 V 3.90±0.10 V 0.25±0.025 V Available 0.20±0.02 V Available *1. The input voltage of CTL for normal condition is changed by the CTL logic. (Please refer to “Operation”). *2. Without over charge detection / release hysteresis. Remark Please contact our sales office for the products with the detection voltage value other than those specified above. Seiko Instruments Inc. 3 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 Pin Configurations 16-Pin TSSOP Top view DOP NC COP VMP COVT CDT CCT V SS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC NC CD1 VC1 CD2 VC2 CD3 CTL Table 2 Pin No. 1 2 3 4 5 6 7 Symbol DOP NC COP VMP COVT CDT CCT VSS CTL CD3 VC2 CD2 VC1 CD1 NC VCC Description Connects FET gate for discharge control (CMOS output) Non connect *1 Connects FET gate for charge control (Nch open-drain output) Detects voltage between VCC to VMP(Over current detection pin) Connects capacitor for over current detection1delay circuit Connects capacitor for over discharge detection delay circuit Connects capacitor for over charge detection delay circuit Negative power input, and connects negative voltage for battery 3 Charge/discharge control signal input Battery 3 conditioning signal output Connects battery 2 negative voltage and battery 3 positive voltage Battery 2 conditioning signal output Connects battery 1 negative voltage and battery 2 positive voltage Battery 1 conditioning signal output Non connect *1 Figure 2 8 9 10 11 12 13 14 15 16 Positive power input and connects battery 1 positive voltage *1. The NC pin is electrically open. The NC pin can be connected to VCC or VSS. 4 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Absolute Maximum Ratings Table 3 (Ta = 25 °C unless otherwise specified) Item Input voltage between VCC and VSS Input terminal voltage VMP Input terminal voltage CD1 output terminal voltage CD2 output terminal voltage CD3 output terminal voltage DOP output terminal voltage COP output terminal voltage Power dissipation Operating ambient temperature Sym. VDS VIN VVMP VCD1 VCD2 VCD3 VDOP VCOP PD Topr Applied Pins − VC1, VC2, CTL, CCT, CDT, COVT VMP CD1 CD2 CD3 DOP COP − − − Rating VSS-0.3 to VSS+26 VSS-0.3 to VCC+0.3 VSS-0.3 to VSS+26 VC1-0.3 to VCC+0.3 VC2-0.3 to VCC+0.3 VSS-0.3 to VCC+0.3 VSS-0.3 to VCC+0.3 VSS-0.3 to VVMP+0.3 1100*1 -20 to +70 -40 to +125 Unit V V V V V V V V mW °C °C 300 (When not mounted on board) mW Storage temperature Tstg − *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 1200 Power Dissipation PD (mW) 1000 800 600 400 200 0 0 50 100 150 Ambient Temperature Ta (°C) Figure 3 Power Dissipation of Package (When Mounted on Board) Seiko Instruments Inc. 5 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Electrical Characteristics Table 4 (1 / 2) Item Detection voltage Over charge detection voltage 1 Over charge release voltage 1 Over discharge detection voltage 1 Over discharge release voltage 1 Over charge detection voltage 2 Over charge release voltage 2 Over discharge detection voltage 2 Over discharge release voltage 2 Over charge detection voltage 3 Over charge release voltage 3 Over discharge detection voltage 3 Over discharge release voltage 3 Over current detection voltage 1*1 Over current detection voltage 2 Over current detection voltage 3 Voltage temperature factor 1*2 Voltage temperature factor 2*3 Delay time Over charge detection delay time 1 Over charge detection delay time 2 Over charge detection delay time 3 Over discharge detection delay time 1 Over discharge detection delay time 2 Over discharge detection delay time 3 Over current detection delay time 1 Over current detection delay time 2 Over current detection delay time 3 Symbol Condition Min. Rev.4.2_00 (Ta = 25 °C unless otherwise specified) Test Test Typ. Max. Unit condition circuit VCU1 VCD1 VDD1 VDU1 VCU2 VCD2 VDD2 VDU2 VCU3 VCD3 VDD3 VDU3 VIOV1 0.6 2.0 0 0 1.0 1.0 1.0 40 40 40 20 4 300 − VCU1+0.025 V VCD1+0.10 V VDD1+0.08 V VDU1+0.10 V VCU2+0.025 V VCD2+0.10 V VDD2+0.08 V VDU2+0.10 V VCU3+0.025 V VCD3+0.10 V VDD3+0.08 V VDU3+0.10 V VIOV1×1.1 V 0.66 V 3.0 V 1.0 mV/°C 0.5 mV/°C 1.5 1.5 1.5 60 60 60 30 8 550 s s s ms ms ms ms ms μs 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 − − 9 10 11 9 10 11 12 12 12 − 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 − − 6 6 6 6 6 6 7 7 7 − VCU1 3.80 to 4.40 Adjustment VCU1-0.025 VCD1 3.45 to 4.40 Adjustment VCD1-0.10 VDD1 2.00 to 2.80 Adjustment VDD1-0.08 VDU1 2.00 to 4.00 Adjustment VDU1-0.10 VCU2 3.80 to 4.40 Adjustment VCU2-0.025 VCD2 3.45 to 4.40 Adjustment VCD2-0.10 VDD2 2.00 to 2.80 Adjustment VDD2-0.08 VDU2 2.00 to 4.00 Adjustment VDU2-0.10 VCU3 3.80 to 4.40 Adjustment VCU3-0.025 VCD3 3.45 to 4.40 Adjustment VCD3-0.10 VDD3 2.00 to 2.80 Adjustment VDD3-0.08 VDU3 2.00 to 4.00 Adjustment VDU3-0.10 VIOV1 0.15 to 0.50V Adjustment VIOV1×0.9 VIOV2 VCC Reference 0.54 VIOV3 VSS Reference 1.0 TCOE1 Ta=-20 to 70°C -1.0 TCOE2 Ta=-20 to 70°C -0.5 tCU1 tCU2 tCU3 tDD1 tDD2 tDD3 tIOV1 tIOV2 tIOV3 CCCT=0.47 μF CCCT=0.47 μF CCCT=0.47 μF CCDT=0.1 μF CCDT=0.1 μF CCDT=0.1 μF CCOVT=0.1 μF − FET gate capacitor =2000 pF 0.5 0.5 0.5 20 20 20 10 2 100 Operating voltage Operating voltage between VCC and VDSOP − VSS*4 Current consumption Current consumption (during normal V1=V2=V3=3.5 V IOPE operation) Current consumption for cell 1 ICELL1 V1=V2=V3=3.5 V Current consumption for cell 2 ICELL2 V1=V2=V3=3.5 V Current consumption for cell 3 ICELL3 V1=V2=V3=3.5 V Current consumption at power down IPDN V1=V2=V3=1.5 V Internal resistance with 0V battery charging function type Resistance between VCC and VMP RVCM V1=V2=V3=3.5 V Resistance between VSS and VMP RVSM V1=V2=V3=1.5 V Internal resistance without 0V battery charging function type. Resistance between VCC and VMP RVCM V1=V2=V3=3.5 V Resistance between VSS and VMP RVSM V1=V2=V3=1.5 V Input voltage CTL"H" Input voltage VCTL(H) − CTL"L" Input voltage VCTL(L) − 2.0 − −300 −300 −300 − 0.20 0.20 0.40 0.40 VCC x 0.8 − 24 V μA nA nA nA μA MΩ MΩ MΩ MΩ V V 20 0 0 0 − 0.50 0.50 0.90 0.90 − − 50 300 300 300 0.1 0.80 0.80 1.40 1.40 − VCC x 0.2 5 5 5 5 5 6 6 6 6 16 16 3 3 3 3 3 3 3 3 3 1 1 6 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Table 4 (2 / 2) Item Output voltage DOP"H" voltage DOP"L" voltage COP"L" voltage COP OFF LEAK current CD1"H" voltage CD1"L" voltage CD2"H" voltage CD2"L" voltage CD3"H" voltage CD3"L" voltage *5 0V battery charging function 0V charging start voltage Symbol VDO(H) VDO(L) VCO(L) ICOL VCD1(H) VCD1(L) VCD2(H) VCD2(L) VCD3(H) VCD3(L) V0CHAR Condition IOUT=10 μA IOUT=10 μA IOUT=10 μA Min. VCC-0.5 − − − VCC-0.5 − VCC-0.5 − VCC-0.5 − − (Ta = 25 °C unless otherwise specified) Test Test Typ. Max. Unit condition circuit − − − − − − − − − − − − VSS+0.1 VSS+0.1 V1=V2=V3=4.5 V IOUT=0.1 μA IOUT=10 μA IOUT=0.1 μA IOUT=10 μA IOUT=0.1 μA IOUT=10 μA V1=V2=V3=0 V 100 − VC1+0.1 − VC2+0.1 − VSS+0.1 1.4 V V V nA V V V V V V V 7 7 8 14 13 13 13 13 13 13 15 4 4 5 9 8 8 8 8 8 8 10 *1. If over current detection voltage 1 is 0.50 V, both over current detection voltages 1 and 2 are 0.54 to 0.55 V, but VIOV2 > VIOV1. *2. Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over discharge detection voltage, and over discharge release voltage. *3. Voltage temperature factor 2 indicates over current detection voltage. *4. The DOP and COP logic must be established for the operating voltage. *5. This spec applies for only 0 V battery charging function available type. Seiko Instruments Inc. 7 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Test Circuits Rev.4.2_00 Caution At the Measurement circuit from (1) to (15). If the device’s CTL logic is “normal” (S-8233BA, S-8233BC, S-8233BE) then set the CTL voltage at VSS (V4=0V). If the device’s CTL logic is “reverse” (S-8233BB, S-8233BD) then set the CTL voltage at VCC (V4=V1+V2+V3). (1) Measurement 1 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V1 from 3.5 V gradually. The V1 voltage when COP = 'H' is over charge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage when COP = 'L' is over charge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when DOP = 'H' is over discharge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L' is over discharge release voltage 1 (VDU1). Remark: The voltage change rate is 150 V/s or less. (2) Measurement 2 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V2 from 3.5 V gradually. The V2 voltage when COP = 'H' is over charge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage when COP = 'L' is over charge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when DOP = 'H' is over discharge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L' is over discharge release voltage 2 (VDU2). Remark: The voltage change rate is 150 V/s or less. (3) Measurement 3 Measurement circuit 1 Set V1, V2, and V3 to 3.5 V under normal condition. Increase V3 from 3.5 V gradually. The V3 voltage when COP = 'H' is over charge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage when COP = 'L' is over charge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when DOP = 'H' is over discharge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L' is over discharge release voltage 3 (VDU3). Remark: The voltage change rate is 150 V/s or less. (4) Measurement 4 Measurement circuit 2 Set V1, V2, V3 to 3.5 V and V5 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5 voltage when DOP = 'H' and COP = 'H', is over current detection voltage 1 (VIOV1). Set V1, V2, and V3 to 3.5 V and V5 to 0 V under normal condition. Fix the COVT terminal at VSS, increase V5 from 0 V gradually. The V5 voltage when DOP = 'H' and COP = 'H' is over current detection voltage 2 (VIOV2). Set V1, V2, and V3 to 3.5 V and V5 to 0 V under normal condition. Fix the COVT terminal at VSS, increase V5 gradually from 0 V at 400 μs to 2 ms. The V5 voltage when DOP = 'H' and COP = 'H' is over current detection voltage 3 (VIOV3). (5) Measurement 5 Measurement circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V5 to 0 V under normal condition and measure current consumption. I1 is the normal condition current consumption (IOPE), I2, the cell 2 current consumption (ICELL2), and I3, the cell 3 current consumption (ICELL3). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V5 to 4.5 V under over discharge condition. Current consumption I1 is power-down current consumption (IPDN). 8 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series (6) Measurement 6 Measurement circuit 3 Set S1 to ON, V1, V2, and V3 to 3.5 V, and V5 to 10.5 V under normal condition. V5/I5 is the internal resistance between VCC and VMP (RVCM). Set S1 to ON, V1, V2, and V3 to 1.5 V, and V5 to 4.1 V under over discharge condition. (4.5-V5)/I5 is the internal resistance between VSS and VMP (RVCM). (7) Measurement 7 Measurement circuit 4 Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V5 to 0 V under normal condition. Increase V6 from 0 V gradually. The V6 voltage when I6 = 10 μA is DOP'L' voltage (VD0 (L)). Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V5 to VIOV2+0.1 V under over current condition. Increase V7 from 0 V gradually. The V7 voltage when I7 = 10 μA is the DOP'H' voltage (VDO (H)). (8) Measurement 8 Measurement circuit 5 Set V1, V2, V3 to 3.5 V and V5 to 0 V under normal condition. Increase V6 from 0 V gradually. The V6 voltage when I1 = 10 μA is the COP'L' voltage (VC0 (L)). (9) Measurement 9 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V1 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V1 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 1 (tCU1). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V1 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V1 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 1 (tDD1). (10) Measurement 10 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V2 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V2 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 2 (tCU2). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V2 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V2 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 2 (tDD2). (11) Measurement 11 Measurement circuit 6 Set V1, V2, V3 to 3.5 V under normal condition. Increase V3 from 3.5 V to 4.5 V immediately (within 10 μs). The time after V3 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 3 (tCU3). Set V1, V2, V3 to 3.5 V under normal condition. Decrease V3 from 3.5 V to 1.9 V immediately (within 10 μs). The time after V3 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 3 (tDD3). (12) Measurement 12 Measurement circuit 7 Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V5 from 0 V to 0.55 V immediately (within 10 μs). The time after V5 becomes 0.55 V until DOP goes 'H' is the over current detection delay time 1 (tIOV1). Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V5 from 0 V to 0.75 V immediately (within 10 μs). The time after V4 becomes 0.75 V until DOP goes 'H' is the over current detection delay time 2 (tIOV2) Set S1 to ON to inhibit over discharge detection. Set V1, V2, V3 to 4.0 V and increase V5 from 0 V to 6.0 V immediately (within 1 μs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V5 becomes 6.0 V until DOP goes 'H' is the over current detection delay time 3 (tIOV3). Seiko Instruments Inc. 9 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 (13) Measurement 13 Measurement circuit 8 Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V6, V7, and V8 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10 μA is the CD1'L' voltage (VCD1(L)) Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V5, V7, and V8 to 0 V under normal condition. Increase V6 from 0 V gradually. The V6 voltage when I6 = 10 μA is the CD2'L' voltage (VCD2(L)). Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V5, V6, and V8 to 0 V under normal condition. Increase V7 from 0 V gradually. The V7 voltage when I7 = 10 μA is the CD3'L' voltage (VCD3(L)). Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 μA is the CD1'H' voltage (VCD1(H)). Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 μA is the CD2'H' voltage (VCD2(H)). Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 μA is the CD3'H' voltage (VCD3(H)). (14) Measurement 14 Measurement circuit 9 Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is COP OFF LEAK current (ICOL). (15) Measurement 15 Measurement circuit 10 Set V1, V2, and V3 to 0 V, and V5 to 2 V, and decrease V5 gradually. The V5 voltage when COP = 'H' (VSS + 0.3 V or higher) is the 0 V charge start voltage (V0CHAR). (16) Measurement 16 Measurement circuit 1 ( Measurement will be changed by the CTL logic! ) 1) If the CTL logic is “normal” Set V1, V2, and V3 to 3.5 V, and V4 to 0 V, and increase V4 gradually. The V4 voltage when COP = 'H' (VSS + 0.3 V or higher) and DOP = 'H' (VSS + 0.3 V or higher) is the CTL 'H' input voltage (VCTL(H)). After that decrease V4 gradually. The V4 voltage when COP = 'L' (VCC - 0.3 V or lower) and DOP = 'L' (VCC - 0.3 V or lower) is the CTL'L' input voltage (VCTL(L)). 2) If the CTL logic is “reverse” Set V1, V2, and V3 to 3.5 V, and V4 to10.5 V, and decrease V4 gradually. The V4 voltage when COP = 'H' (VSS + 0.3 V or higher) and DOP = 'H' (VSS + 0.3 V or higher) is the CTL'L' input voltage (VCTL(L)). After that increase V4 gradually. The V4 voltage when COP ='L' (VVMP - 0.3 V or lower) and DOP = 'L' (VCC - 0.3 V or lower) is the CTL'H' input voltage (VCTL(H)). 10 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Caution At the Measurement circuit from 1 to 10. If the device’s CTL logic is “normal” (S-8233BA, S-8233BC, S-8233BE) then set the CTL voltage at VSS (V4=0 V). If the device’s CTL logic is “reverse” (S-8233BB, S-8233BD) then set the CTL voltage at VCC (V4=V1+V2+V3). V5 1MΩ DOP VCC V1 CD1 COP VMP CTL V4 V1 CD1 VCC 1MΩ DOP COP VMP CTL V4 VC1 V2 CD2 S-8233B CCT V2 VC1 S-8233B CD2 CDT CCT VC2 V3 CD3 CDT V3 VC2 CD3 VSS COVT VSS COVT Test circuit 1 Test circuit 2 I5 V5 I1 VCC V1 I2 VC1 V2 I3 VC2 V3 CD3 VSS C OVT CDT S-8233B CD2 CCT CD1 DOP COP VMP C TL V4 S1 V6 S1 V7 S2 I7 V5 I6 DOP VCC V1 CD1 COP VMP CTL V4 VC1 V2 S-8233B CD2 CDT CCT VC2 V3 CD3 VSS COVT Test circuit 3 Figure 4 (1/2) Test circuit 4 Seiko Instruments Inc. 11 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 V6 I6 V5 1MΩ D OP DOP VCC V1 CD1 CTL COP VMP V4 COP VMP CTL V4 VCC V1 CD1 VC1 VC1 V2 S-8233B CD2 CDT CCT V2 S-8233B CD2 C1 = 0.47 μF CCT C1 CD T C2 VC2 V3 CD3 VC2 V3 CD3 C2 = 0.1 μF C3 = 0.1 μF COVT VSS COVT VSS C3 Test circuit 5 V5 1 MΩ Test circuit 6 1MΩ D OP COP VMP C TL V4 DOP VCC V1 CD1 COP VMP CTL V4 V1 I8 V8 S1 S4 I5 V5 VCC CD1 VC1 CD2 S-8233B CCT VC1 S-8233B V2 CD2 C1 = 0.47 μF VC2 V3 CD3 VSS C2 = 0.1 μF C3 = 0.1 μF COVT C3 CDT C2 V3 S2 C CT V2 C1 S1 S5 I6 V6 VC2 CD3 CDT S3 S6 I7 V7 C OVT VSS Test circuit 7 Test circuit 8 I1 DOP VCC V1 CD1 CTL COP VMP V4 V5 1 MΩ DOP VCC V1 CD1 COP VMP CTL V4 VC1 V2 S-8233B CD2 CDT V3 CCT V2 VC1 CD2 S-8233B CCT VC2 V3 CD3 VSS VC2 CD3 VSS CDT COVT COVT Test circuit 9 Figure 4 (2/2) Test circuit 10 12 Seiko Instruments Inc. Rev.4.2_00 Operation BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Remark Refer to “Battery Protection IC Connection Example”. Normal condition This IC monitors the voltages of the three serially-connected batteries and the discharge current to control charging and discharging. If the voltages of all the three batteries are in the range from the over discharge detection voltage (VDD) to the over charge detection voltage (VCU), and the current flowing through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal or lower than over current detection voltage 1), the charging and discharging FETs turn on. In this condition, charging and discharging can be carried out freely. This condition is called the normal condition. In this condition, the VMP and VCC terminals are shorted by the RVCM resistor. Over current condition This IC is provided with the three over current detection levels (VIOV1,VIOV2 and VIOV3) and the three over current detection delay time (tIOV1,tIOV2 and tIOV3) corresponding to each over current detection level. If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage is equal to or higher than the over current detection voltage) during discharging under normal condition and it continues for the over current detection delay time (tIOV) or longer, the discharging FET turns off to stop discharging. This condition is called an over current condition. The VMP and VCC terminals are shorted by the RVCM resistor at this time. The charging FET turns off. When the discharging FET is off and a load is connected, the VMP terminal voltage equals the VSS potential. The over current condition returns to the normal condition when the load is released and the impedance between the EB- and EB+ terminals (see Figure 9 for a connection example) is 100 MΩ or higher. When the load is released, the VMP terminal, which and the VCC terminal are shorted with the RVCM resistor, goes back to the VCC potential. The IC detects that the VMP terminal potential returns to over current detection voltage 1 (VIOV1) or lower (or the over current detection voltage 2 (VIOV2) or lower if the COVT terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the normal condition. Over charge condition If one of the battery voltages becomes higher than the over charge detection voltage (VCU) during charging under normal condition and it continues for the over charge detection delay time (tCU) or longer, the charging FET turns off to stop charging. This condition is called the over charge condition. The 'H' level signal is output to the conditioning terminal corresponding to the battery which exceeds the over charge detection voltage until the battery becomes equal to lower than the over charge release voltage (VCD). The battery can be discharged by connecting an Nch FET externally. The discharging current can be limited by inserting R11, R12 and R13 resistors (see Figure 9 for a connection example). The VMP and VCC terminals are shorted by the RVCM resistor under the over charge condition. The over charge condition is released in two cases: 1) The battery voltage which exceeded the over charge detection voltage (VCU) falls below the over charge release voltage (VCD), the charging FET turns on and the normal condition returns. 2) If the battery voltage which exceeded the over charge detection voltage (VCU) is equal or higher than the over charge release voltage (VCD), but the charger is removed, a load is placed, and discharging starts, the charging FET turns on and the normal condition returns. The release mechanism is as follows: the discharge current flows through an internal parasitic diode of the charging FET immediately after a load is installed and discharging starts, and the VMP terminal voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC detects this voltage (over current detection voltage 1 or higher), releases the over charge condition and returns to the normal condition. Seiko Instruments Inc. 13 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 Over discharge condition If any one of the battery voltages falls below the over discharge detection voltage (VDD) during discharging under normal condition and it continues for the over discharge detection delay time (tDD) or longer, the discharging FET turns off and discharging stops. This condition is called the over discharge condition. When the discharging FET turns off, the VMP terminal voltage becomes equal to the VSS voltage and the IC's current consumption falls below the power-down current consumption (IPDN). This condition is called the power-down condition. The VMP and VSS terminals are shorted by the RVSM resistor under the over discharge and power-down conditions. The power-down condition is canceled when the charger is connected and the voltage between VMP and VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to or higher than the over discharge release voltage (VDU) in this condition, the over discharge condition changes to the normal condition. Delay circuits The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to tDD3), and over current detection delay time 1 (tI0V1) are changed with external capacitors (C4 to C6). The delay times are calculated by the following equations: Min. tCU[S] =Delay factor ( 1.07, tDD[S] =Delay factor ( 0.20, tIOV1[S]=Delay factor ( 0.10, Typ. 2.13, 0.40, 0.20, Max. 3.19)×C4 [uF] 0.60)×C5 [uF] 0.30)×C6 [uF] Caution: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time cannot be changed via an external capacitor. CTL terminal [If the CTL logic is “normal”] If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time, the VMP and VCC terminals are shorted by the RVCM resistor. When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go back to their appropriate conditions for the battery voltages. [If the CTL logic is“reverse”] When the CTL terminal becomes equal to VSS potential, both the charging and discharging FETs turn off to inhibit charging and discharging. If the CTL terminal is floated under normal condition, charging and discharging are enabled and go back to their appropriate conditions for the battery voltages. Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin ('L' level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations. 14 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Table.5 Output voltage & current consumption by CTL terminal voltage. Statements Normal &Over voltage state High & Floated High High Typ.20 μA Comply with battery voltage Comply with battery voltage Typ.20 μA Low Comply with battery voltage Comply with battery voltage Typ.20 μA High High Typ.20 μA CTL terminal voltage CTL logic “normal” COP (Charge control) S-8233BA DOP (Discharge control) S-8233BC Current consumption S-8233BE CTL logic “reverse” COP S-8233BB S-8233BD DOP Current consumption Power down mode (Without charger) High Low Floated High Low Unknown High High High Typ. 1 nA Low High Typ. 1 nA Typ. 1 nA High High Typ. 1 nA Unknown Unknown High Unknown 0 V battery charging function This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V. When the 0 V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by connecting the charger, the charging FET gate is fixed to VSS potential. When the voltage between the gate sources of the charging FET becomes equal to or higher than the turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the discharging FET turns off and the charging current flows through the internal parasitic diode in the discharging FET. If all the battery voltages become equal to or higher than the over discharge release voltage (VDU), the normal condition returns. Caution: In the products without 0 V battery charging function, the resistance between VCC and VMP and between VSS and VMP are lower than the products with 0 V battery charging function. It causes to that over charge detection voltage increases by the drop voltage of R5 (see Figure 9 for a connection example) with sink current at VMP. The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0 V battery charging function. Voltage temperature factor Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over discharge detection voltage, and over discharge release voltage. Voltage temperature factor 2 indicates over current detection voltage. The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 5. Ex. Voltage temperature factor of over charge detection voltage Typ. VCU [V] +1 mV/°C VCU25 VCU25 is the over charge detection voltage at 25°C −1 mV/°C −20 25 70 Ta [°C] Figure 5 Seiko Instruments Inc. 15 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Timing Charts 1. Over charge detection V 1 battery B attery voltage V CU V CD V DU V DD V CC D OP terminal V SS V2 battery V3 battery Rev.4.2_00 COP terminal Hi-z VSS V CHA V CC V IOV1 V SS Hi-z Hi-z Hi-z VMP terminal C harger connected Load connected Mode *1 D elay Delay Delay Delay Delay & *1. N ormal mode, Over charge mode, Over discharge mode, Over current mode R emark T he charger is assumed to charge with a constant current. V CHA i ndicates the open voltage of the charger. Figure 6 2. Over discharge detection V1 battery V CU B attery voltage V CD V DU V DD V CC D OP terminal V SS COP terminal V SS V CHA V MP terminal V CC V IOV1 V SS Charger connected Load connected Mode *1. *1 V 2 battery V3 battery H i-z Delay Delay Delay Delay Delay N ormal mode, Over charge mode, O ver discharge mode, Over current mode Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger. Figure 7 16 Seiko Instruments Inc. Rev.4.2_00 3. Over current detection BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series V1, V2, and V3 batteries B attery voltage V CU V CD V DU V DD VCC D OP terminal VSS C OP terminal VSS V CC V IOV1 terminal V IOV2 V IOV3 V MP Charger connected Load connected Mode*1 Delay tIOV3 Inhibit charging and discharging CTL terminal VSS V CC If the CTL logic is “reverse” ,it will be exchanged V CC for VSS. CTL terminal VCC V SS Hi-z Hi-z Hi-z Hi-z D elay tIOV1 D elay tIOV2 *1. Normal mode, Over charge mode, Over discharge mode, Over current mode Figure 8 Seiko Instruments Inc. 17 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Battery Protection IC Connection Example EB+ FET-A FET-B R6 1 MΩ COP VMP Nch open drain CTL R7 1 KΩ R5 10 KΩ Rev.4.2_00 DOP FET1 Battery 1 R11 C1 VCC CD1 CTL logic is “normal” (S-8233BA) VSS(GND): Normal operation Floating or VCC: Inhibit charging and discharging. CTL logic is “reverse” (S-8233BB) Floating or VCC: Normal operation VSS(GND): Inhibit charging and discharging. R1 VC1 FET2 Battery 2 R12 C2 R2 FET3 Battery 3 R13 C3 CD3 COVT VSS R3 C6 CD2 S-8233B series CDT VC2 C5 CCT C4 Over charge delay time setting Over discharge delay time setting FET-C High: Inhibit over discharge detection. Over current delay time setting EB - Figure 9 [Description of Figure 9] R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current during over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the conditioning function, open CD1, CD2, and CD3. The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to tDD3), and over current detection delay time (tI0V1) are changed with external capacitors (C4 to C6). See the electrical characteristics. R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100 kΩ to 1 MΩ resistor. R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor. If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the over current mode. C6 must be connected to prevent it. If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of battery voltage when the over current occurs. In this case, a charger must be connected to return to the normal condition. To prevent this, connect an at least 0.01 μF capacitor to C5. If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less. Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 μA or less. If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1 μA even when the battery voltage drops and the IC enters the over discharge detection mode. R1, R2, and R3 must be 1 kΩ or less. R7 is the protection of the CTL when the CTL terminal voltage higher than VCC voltage. Connect a 300 Ω to 5 kΩ resistor. If the CTL terminal voltage never greater than the VCC voltage (ex. R7 connect to VSS), without R7 resistance is allowed . 18 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series Caution 1. The above constants may be changed without notice. 2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233B series with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform through evaluation using the actual application to set the constant. Precautions If a charger is connected in the over discharge condition and one of the battery voltages becomes equal to or higher than the over charge release voltage (VCU) before the battery voltage which is below the over discharge detection voltage (VDD) becomes equal to or higher than the over discharge release voltage (VDU), the over discharge and over charge conditions are entered and the charging and discharging FETs turn off. Both charging and discharging are disabled. If the battery voltage which was higher than the over charge detection voltage (VCU) falls to the over charge release voltage (VCD) due to internal discharging, the charging FET turns on. If the charger is detached in the over charge and over discharge condition, the over charge condition is released, but the over discharge condition remains. If the charger is connected again, the battery condition is monitored after that. The charging FET turns off after the over charge detection delay time, the over charge and over discharge conditions are entered. If any one of the battery voltages is equal to or lower than the over discharge release voltage (VDU) when they are connected for the first time, the normal condition may not be entered. If the VMP terminal voltage is made equal to or higher than the VCC voltage (if a charger is connected), the normal condition is entered. If the CTL terminal floats in power-down mode, it is not pulled up in the IC, charging may not be inhibited. However, the over discharge condition becomes effective. At that time, current consumption would be increase because CTL terminal is affected by noise. If the charger is connected, the CTL terminal is pulled up, and charging and discharging are inhibited immediately. Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. Seiko Instruments Inc. 19 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 Characteristics (Typical Data) 1. Detection voltage temperature characteristics Overcharge detection voltage vs. temperature VCU=4.25[V] 4.35 VCU (V) Overcharge release voltage vs. temperature 4.20 VCD (V) VCD=4.10[V] 4.25 4.10 4.15 -40 -20 0 20 Ta(°C) 40 60 80 100 4.00 -40 -20 0 20 Ta(°C) 40 60 80 100 Overdischarge detection voltage vs. temperature VDD=2.35[V] 2.45 VDD (V) Overdischarge release voltage vs. temperature VDU=2.85[V] 2.95 VDU (V) 2.35 2.85 2.25 -40 -20 0 20 Ta(°C) 40 60 80 100 2.75 -40 -20 0 20 Ta(°C) 40 60 80 100 Overcurrent1 detection voltage vs. temperature 0.35 VIOV1 (V) VIOV1=0.3 [V] Overcurrent2 detection voltage vs. temperature 0.65 VIOV2 (V) VIOV2=0.6 [V] 0.30 0.60 0.25 -40 -20 0 20 Ta(°C) 40 60 80 100 0.55 -40 -20 0 20 Ta(°C) 40 60 80 100 20 Seiko Instruments Inc. Rev.4.2_00 BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK S-8233B Series 2. Current consumption temperature characteristics Current consumption vs. temperature in normal mode VCC=10.5 [V] 50 IOPE (uA) Current consumption vs. temperature in power-down mode 1.0 IPDN (nA) VCC=4.5 [V] 25 0.5 0 -40 -20 0 20 Ta(°C) 40 60 80 100 0.0 -40 -20 0 20 Ta(°C) 40 60 80 100 3. Delay time temperature characteristics Overcharge detection time vs. temperature C=0.47[uF] VCC=11.5 [V] 1.5 Overdischarge detection time vs. temperature C=0.1[uF] VCC=8.5 [V] 60 tDD (ms) tCU (s) 1.0 40 0.5 -40 -20 0 20 Ta(°C) 40 60 80 100 20 -40 -20 0 20 40 60 80 100 Ta(°C) Overcurrent1 detection time vs. temperature C=0.1[uF] VCC=10.5 [V] 30 tIOV1 (ms) Overcurrent2 detection time vs. temperature VCC=10.5 [V] 8 tIOV2 (ms) 20 5 10 -40 2 -20 0 20 40 60 80 100 -40 -20 0 20 Ta(°C) 40 60 80 100 Ta(°C) Seiko Instruments Inc. 21 BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK S-8233B Series Rev.4.2_00 Overcurrent3 (load short) detection time vs. temperature 0.40 V CC =6.0 [V] tIOV3 (ms) 0.25 0.10 - 40 -20 0 20 Ta(°C) 40 60 80 100 4. Delay time vs. power supply voltage O vercurrent3 (load short) detection time vs. power supply voltage Ta=25[°C] 1 .0 tIOV3 (ms) 0 .5 0 .0 3 6 9 VCC [V] 12 15 Caution Please design all applications of the S-8233B Series with safety in mind. 22 Seiko Instruments Inc. 5.1±0.2 16 9 1 8 0.17±0.05 0.65 0.22±0.08 No. FT016-A-P-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A-PKG Dimensions FT016-A-P-SD-1.1 mm Seiko Instruments Inc. ø1.5 -0 +0.1 4.0±0.1 2.0±0.1 0.3±0.05 8.0±0.1 ø1.6±0.1 (7.2) 4.2±0.2 1.5±0.1 6.5 -0.2 +0.4 1 16 8 9 Feed direction No. FT016-A-C-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A-Carrier Tape FT016-A-C-SD-1.1 mm Seiko Instruments Inc. 21.4±1.0 17.4±1.0 17.4 -1.5 +2.0 Enlarged drawing in the central part ø21±0.8 2.0±0.5 ø13.0±0.2 No. FT016-A-R-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A- Reel FT016-A-R-SD-1.1 QTY. mm 2,000 Seiko Instruments Inc. • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.