S-8243A

Rev.2.4_00 BATTRY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series The S-8243A/B is a series of lithium-ion rechargeable battery protection ICs incorporating high-accuracy battery protection circuits, a battery monitor amp and a voltage regulator which drives microcomputer and gas gauge IC. Combining microcomputer or gas gauge IC facilitates displaying a remaining amount of battery. The S-8243A/B is suitable for protection of 3-serial or 4-serial cell lithium-ion battery packs from overcharge, overdischarge and overcurrent. Features High-accuracy voltage detection for each cell • Overcharge detection voltage n (n=1 to 4) 3.9 V to 4.4 V (50 mV step) Accuracy ±25 mV • Hysteresis voltage n (n=1 to 4) of overcharge detection −0.10 V to −0.40 V (50 mV step) or 0 V Accuracy ±50 mV (Overcharge release voltage n (=Overcharge detection voltage n + Hysteresis voltage n) can be selected within the range 3.8 V to 4.4 V.) • Overdischarge detection voltage n (n=1 to 4) 2.0 V to 3.0 V (100 mV step) Accuracy ±80 mV • Hysteresis voltage n (n=1 to 4) of overdischarge detection 0.20 V to 0.70 V or 0 V (100 mV step) Accuracy ±100 mV (Overdischarge release voltage n (=Overdischarge detection voltage n + Hysteresis voltage n) can be selected within the range 2.0 V to 3.4 V.) (2) Three-level overcurrent protection including protection for short-circuiting • Overcurrent detection voltage 1 0.05 V to 0.3 V (50 mV step) Accuracy ±25 mV • Overcurrent detection voltage 2 0.5 V Accuracy ±100 mV • Overcurrent detection voltage 3 VDD/2 Accuracy ±15 % (3) Delay times for overcharge detection, overdischarge detection and overcurrent detection 1 can be set by external capacitors. (Delay times for overcurrent detection 2 and 3 are fixed internally.) (4) Charge/discharge operation can be controlled through the control pins. (5) High-accuracy battery monitor amp GAMP = VBATTERY × 0.2 ±1.0% (6) Voltage regulator VOUT = 3.3 V ±2.4 % (3 mA max.) (7) High input-voltage device Absolute maximum rating: 26 V (8) Wide operating voltage range 6 V to 18 V (9) Wide operating temperature range: −40°C to +85 °C (10) Low current consumption Operation mode 120 μA max. Power down mode 0.1 μA max. (11) Small package 16-Pin TSSOP package (12) Lead-free products (1) Applications • Lithium-ion rechargeable battery packs • Lithium polymer rechargeable battery packs Seiko Instruments Inc. 1 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 Package Package Name 16-Pin TSSOP Package FT016-A Drawing Code Tape FT016-A Reel FT016-A 2 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Block Diagrams S-8243A Series VDD Battery protection DOP DOP,COP, RVCM,RVSM control VREG Voltage regulator COP Delay Delay Delay 660 kΩ 200 nA CTL1 VREG 1.4 MΩ Delay 440 kΩ CTL2 1.4 MΩ VMP 660 kΩ VREG Battery selection 1.4 MΩ CTL3 1.4 MΩ VREG 1.4 MΩ VC1 CTL4 1.4 MΩ VC2 Battery monitor amp 1 MΩ 5 MΩ VBATOUT 5 MΩ 1 MΩ VC3 CCT CDT VSS Remark1. Diodes in the figure are parasitic diodes. 2. Numerical values are typical values. Figure 1 Seiko Instruments Inc. 3 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 S-8243B Series VDD Battery protection DOP DOP, COP, RVCM, RVSM control VREG Voltage regulator COP Delay Delay Delay 660 kΩ 200 nA CTL1 VREG 1.4 MΩ Delay 440 kΩ CTL2 1.4 MΩ VMP 660 kΩ VREG Battery selection 1.4 MΩ CTL3 1.4 MΩ VREG 1.4 MΩ VC1 CTL4 1.4 MΩ VC2 Battery monitor amp 1 MΩ 5 MΩ VBATOUT 5 MΩ 1 MΩ VC3 CCT CDT VSS Remark1. Diodes in the figure are parasitic diodes. 2. Numerical values are typical values. Figure 2 4 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Product Name Structure 1. Product Name S-8243 x xx FT TB G IC direction in tape specifications*1 Package code FT : 16-Pin TSSOP Serial code *2 Sequentially set from AA to ZZ Product series name A : 3-cell B : 4-cell *1. Refer to the taping specifications at the end of this book. *2. Refer to the “2. Product Name List”. 2. Product Name List Table 1 S-8243A Series (For 3-Serial Cell) Overcurrent Overcharge Hysteresis voltage for Overdischarge Hysteresis voltage for 0 V battery detection voltage overcharge detection detection voltage overdischarge detection detection voltage1 charging Product name/Item [VHC] [VDL] [VHD] [VIOV1] [VCU] function Available S-8243AACFT-TB-G 4.35 ± 0.025 V −0.15 ±0.05 V 2.40 ±0.08 V 0.20 ±0.10 V 0.20 ±0.025 V 0V Available S-8243AADFT-TB-G 4.35 ± 0.025 V −0.35 ±0.05 V 2.40 ±0.08 V 0.20 ±0.025 V Note Change in the detection voltage is available in products other than listed above. Contact our sales office. Table 2 S-8243B Series (For 4-Serial Cell) Hysteresis voltage for Overdischarge Hysteresis voltage for Overcurrent Overcharge 0 V battery detection voltage overcharge detection detection voltage overdischarge detection detection voltage1 charging [VHC] [VDL] [VHD] [VIOV1] [VCU] function 0V Available S-8243BADFT-TB-G 4.35 ±0.025 V −0.25 ±0.05 V 2.40 ±0.08 V 0.25 ±0.025 V Available S-8243BAEFT-TB-G 4.35 ±0.025 V −0.15 ±0.05 V 2.40 ±0.08 V 0.20 ±0.10 V 0.20 ±0.025 V 0V Available S-8243BAFFT-TB-G 4.25 ±0.025 V −0.25 ±0.05 V 2.40 ±0.08 V 0.20 ±0.025 V Note Change in the detection voltage is available in products other than listed above. Contact our sales office. Product name/Item Seiko Instruments Inc. 5 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 Pin Configuration 1 6-Pin TSSOP Top view VDD DOP COP VMP VC1 VC2 VC3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREG CTL1 CTL2 CTL3 CTL4 VBATOUT CCT CDT Figure 3 Table 3 Pin description (S-8243A Series) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VDD DOP COP VMP VC1 VC2 VC3 VSS CDT CCT VBATOUT CTL4 CTL3 CTL2 CTL1 VREG Description Positive power input pin. Battery 1 positive voltage connection pin FET gate connection pin for discharge control (CMOS output) FET gate connection pin for charge control (Nch open-drain output) Voltage detection pin between VDD and VMP (Over current detection pin) No connection Battery1 negative voltage and battery 2 positive voltage connection pin Battery 2 negative voltage and battery 3 positive voltage connection pin Negative power input pin. Battery 3 negative voltage connection pin Capacitor connection pin for overdischarge detection delay time and over current detection1 delay time Capacitor connection pin for overcharge detection delay time Output pin for each battery voltage and offset Battery selection control signal input Battery selection control signal input Charge and discharge control signal input Charge and discharge control signal input 3.3 V voltage regulator output Table 4 Pin description (S-8243B Series) Pin No. Symbol Description 1 VDD Positive power input pin. Battery 1 positive voltage connection pin 2 DOP FET gate connection pin for discharge control (CMOS output) 3 COP FET gate connection pin for charge control (Nch open-drain output) 4 VMP Voltage detection pin between VDD and VMP (Over current detection pin) 5 VC1 Battery1 negative voltage and battery 2 positive voltage connection pin 6 VC2 Battery 2 negative voltage and battery 3 positive voltage connection pin 7 VC3 Battery 3 negative voltage and battery 4 positive voltage connection pin 8 VSS Negative power input pin. Battery 4 negative voltage connection pin 9 CDT Capacitor connection pin for overdischarge detection delay time and over current detection1 delay time 10 CCT Capacitor connection pin for overcharge detection delay time 11 VBATOUT Output pin for each battery voltage and offset 12 CTL4 Battery selection control signal input 13 CTL3 Battery selection control signal input 14 CTL2 Charge and discharge control signal input 15 CTL1 Charge and discharge control signal input 16 VREG 3.3 V voltage regulator output 6 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Absolute Maximum Ratings Table 5 Item Input voltage VDD Input voltage VMP pin Input voltage DOP pin output voltage COP pin output voltage VREG pin output voltage CTL1 pin input voltage CTL2 to CTL4 pin input voltage Cell voltage output voltage Power dissipation Symbol VDS VIN VMP VDOP VCOP VOUT VCTL1 VCTLn VBATOUT PD (Ta = 25°C unless otherwise specified) Applied Pins Rating Unit V ⎯ VSS−0.3 to VSS+26 V VC1, VC2, VC3, VSS−0.3 to VDD+0.3 CCT, CDT V VMP VSS−0.3 to VSS+26 V DOP VSS−0.3 to VDD+0.3 V COP VSS−0.3 to VSS+26 V VREG VSS−0.3 to VDD+0.3 V CTL1 VSS−0.3 to VDD+0.3 V CTL2, CTL3, CTL4 VSS−0.3 to VOUT+0.3 V VBATOUT VSS−0.3 to VOUT+0.3 300 (When not mounted on board) mW ⎯ mW 1100*1 ⎯ ⎯ −40 to +85 °C ⎯ −40 to +125 °C Operation ambient temperature Topr Storage temperature Tstg *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 1200 Power Dissipation PD (mW) 1000 800 600 400 200 0 0 50 100 150 Ambient Temperature Ta (°C) Figure 4 Power Dissipation of Package (When Mounted on Board) Seiko Instruments Inc. 7 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 Electrical Characteristics (1) S-8243A Series Table 6 (1/2) (Ta = 25 °C unless otherwise specified) Item BATTERY PROTECTION Overcharge detection voltage n n=1, 2, 3 Hysteresis voltage n of overcharge detection n=1, 2, 3 Overdischarge detection voltage n=1, 2, 3 Hysteresis voltage n of Overdischarge detection n=1, 2, 3 Overcurrent detection voltage 1 Overcurrent detection voltage 2 Overcurrent detection voltage 3 Temperature coefficient for detection and release voltage Temperature coefficient for overcurrent detection voltage 0 V battery charge starting charger voltage 0 V battery charge inhibition battery voltage INTERNAL RESISTANCE Internal resistance between VMP and VDD Internal resistance between VMP and VSS VOLTAGE REGULATOR Output voltage Line regulation Load regulation BATTERY MONITOR AMP Input offset voltage n n=1, 2, 3 Voltage gain n n=1, 2, 3 Operating voltage between VDD and VSS CTL1 input voltage for High CTL1 input voltage for Low CTLn input voltage for High n=2, 3, 4 CTLn input voltage for Low n=2, 3, 4 VOFFn V1=V2=V3=3.5 V 60 0.2×0.99 165 0.2 270 0.2×1.01 mV 3 3 VOUT VDD=14 V, IOUT=3 mA 3.221 3.300 5 15 3.379 15 30 V mV mV 2 2 2 ΔVOUT1 VDD=6 V→18 V, IOUT=3 mA ΔVOUT2 VDD=14 V, IOUT=5 μA→3 mA RVDM RVSM V1=V2=V3=3.5 V V1=V2=V3=1.8 V 500 300 1100 700 2400 1500 kΩ kΩ 8 8 *2 *1 Symbol Conditions Min. VCUn Typ. Max. VCUn +0.025 VHCn +0.05 VDLn +0.08 VHDn +0.10 VIOV1 +0.025 VDD−0.40 VDD×0.575 1.0 0.5 Unit Test circuit VCUn 3.9 V to 4.4 V, 50 mV Step −0.025 VHCn −0.05 VCUn V 4 VHCn −0.10 V to −0.40 V, and 0 V VHCn V 4 VDLn 2.0 V to 3.0 V, 100 mV Step −0.08 VHDn −0.10 VDLn VDLn V 4 VHDn 0.20 V to 0.70 V, and 0 V VHDn V 4 VIOV1 VIOV2 VIOV3 TCOE1 TCOE2 0.05 V to 0.3 V, 50 mV Step ⎯ ⎯ Ta= −5 °C to +55 °C Ta= −5 °C to +55 °C −0.025 VDD−0.60 VDD×0.425 VIOV1 VIOV1 VDD−0.50 VDD×0.5 0 0 V V V mV/°C mV/°C 4 4 4 4 4 −1.0 −0.5 0 V BATTERY CHARGING FUNCTION V0CHA V0INH 0 V battery charging available 0 V battery charging unavailable ⎯ 0.4 0.8 0.7 1.5 1.1 V V 7 7 ⎯ ⎯ GAMPn V1=V2=V3=3.5 V ⎯ INPUT VOLTAGE, OPERATING VOLTAGE VDSOP VCTL1H VCTL1L VCTLnH VCTLnL ⎯ ⎯ ⎯ ⎯ ⎯ 6 VDD×0.8 ⎯ ⎯ ⎯ ⎯ ⎯ 18 V V V V V 4 6 6 3, 6 3, 6 ⎯ VDD×0.2 VOUT VOUT×0.1 ⎯ VOUT×0.9 ⎯ 8 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Table 6 (2/2) Item INPUT CURRENT Current consumption at not monitoring VBATOUT Current consumption at power down Current for VCN at not monitoring VBATOUT (n=2, 3) Current for VC2 at monitoring of VBATOUT Current for VC3 at monitoring of VBATOUT Current for CTL1 at Low Current for CTLn at High n=2,3,4 Current for CTLn at Low n=2,3,4 OUTPUT CURRENT Leak current COP Sink current COP Source current DOP Sink current DOP Source current VBATOUT Sink current VBATOUT ICOH ICOL IDOH IDOL IVBATH IVBATL VCOP=24 V VCOP=VSS+0.5 V VDOP=VDD−0.5 V VDOP=VSS+0.5 V VBATOUT=VDD−0.5 V VBATOUT=VSS+0.5 V IOPE IPDN IVCnN IVC2 IVC3 ICTL1L ICTLnH ICTLnL V1=V2=V3=3.5 V, VMP=VDD V1=V2=V3=1.5 V, VMP=VSS V1=V2=V3=3.5 V V1=V2=V3=3.5 V V1=V2=V3=3.5 V V1=V2=V3=3.5 V, VCTL1=0 V VCTLn=VOUT VCTLn=0 V Symbol Remarks Min. Typ. Max. Unit Test circuit ⎯ ⎯ −0.3 65 120 0.1 0.3 7.2 4.0 μA μA μA μA μA μA μA μA 1 1 3 3 3 5 9 9 ⎯ 0 2.0 1.0 −0.2 2.5 −2.5 ⎯ ⎯ −0.4 ⎯ 5 ⎯ −5 ⎯ ⎯ 10 10 10 100 100 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 μA μA μA μA μA μA 9 9 9 9 9 9 ⎯ ⎯ ⎯ ⎯ ⎯ Applied to S-8243AACFT and S-8243AADFT Item DELAY TIME Overcharge detection delay time Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 tCU tDL tlOV1 tlOV2 CCT=0.1 μF CDT=0.1 μF CDT=0.1 μF ⎯ 0.5 50 5 1.5 1.0 100 10 2.5 1.5 150 15 4.0 s ms ms ms 5 5 5 4 Symbol Conditions Min. Typ. Max. Unit Test circuit Overcurrent detection delay time 3 tlOV3 100 300 600 μs 4 ⎯ *1. Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n, overdischarge detection voltage n, and overdischarge release voltage n. *2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2. Seiko Instruments Inc. 9 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 (2) S-8243B Series Table 7 (1/2) (Ta = 25°C unless otherwise specified) Item DETECTION VOLTAGE Overcharge detection voltage n n=1, 2, 3, 4 Hysteresis voltage n of overcharge detection n=1, 2, 3, 4 Overdischarge detection voltage n=1, 2, 3, 4 Hysteresis voltage n of overdischarge detection n=1, 2, 3, 4 Overcurrent detection voltage 1 Overcurrent detection voltage 2 Overcurrent detection voltage 3 Temperature coefficient for detection and release voltage Temperature coefficient for overcurrent detection voltage *2 *1 Symbol Conditions Min. VCUn −0.025 VHCn −0.05 VDLn −0.08 VHDn −0.10 VIOV1 −0.025 VDD−0.60 VDD ×0.425 −1.0 −0.5 Typ. VCun Max. VCUn +0.025 Unit Test circuit VCUn 3.9 V to 4.4 V, 50 mV Step V 4 VHCn −0.10 V to −0.40 V, and 0 V VHCn VHCn +0.05 VDLn +0.08 VHDn +0.10 VIOV1 +0.025 VDD−0.40 VDD ×0.575 1.0 0.5 V 4 VDLn 2.0 V to 3.0 V, 100 mV Step VDLn V 4 VHDn 0.20 to 0.70, and 0 VHDn V 4 VIOV1 VIOV2 VIOV3 TCOE1 TCOE2 0.05 V to 0.3 V, 50 mV Step ⎯ ⎯ Ta= −5°C to +55°C Ta= −5°C to +55°C VIOV1 VDD−0.50 VDD ×0.5 0 0 V V V mV/°C mV/°C 4 4 4 4 4 0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited." depending upon the product type.) 0 V battery charge starting charger voltage 0 V battery charge inhibition battery voltage INTERNAL RESISTANCE Internal resistance between VMP and VDD Internal resistance between VMP and VSS VOLTAGE REGULATOR Output voltage Line regulation Load regulation BATTERY MONITOR AMP Input offset voltage n n=1, 2, 3, 4 Voltage gain n n=1, 2, 3, 4 Operating voltage between VDD and VSS CTL1 input voltage for High CTL1 input voltage for Low CTLn input voltage for High n=2, 3, 4 CTLn input voltage for Low n=2, 3, 4 VOFFn GAMPn V1=V2=V3= V4=3.5 V V1=V2=V3= V4=3.5 V 60 0.2×0.99 165 0.2 270 0.2×1.01 mV ⎯ 3 3 VOUT ΔVOUT1 ΔVOUT2 VDD=14V, IOUT=3 mA VDD=6 V→18 V, IOUT=3 mA VDD=14 V, IOUT=5 μA→3 mA 3.221 ⎯ ⎯ 3.300 5 15 3.379 15 30 V mV mV 2 2 2 RVDM RVSM V1=V2=V3=V4=3.5 V V1=V2=V3=V4=1.8 V 500 300 1100 700 2400 1500 kΩ kΩ 8 8 V0CHA V0INH 0 V battery charging allowed 0 V battery charging inhibited ⎯ 0.4 0.8 0.7 1.5 1.1 V V 7 7 INPUT VOLTAGE, OPERATING VOLTAGE VDSOP VCTL1H VCTL1L VCTLnH VCTLnL ⎯ ⎯ ⎯ ⎯ ⎯ 6 VDD×0.8 ⎯ VOUT×0.9 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 18 ⎯ VDD×0.2 VOUT VOUT×0.1 V V V V V 4 6 6 3, 6 3, 6 10 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Table 7 (2/2) Item INPUT CURRENT Current consumption at not monitoring VBATOUT Current consumption at power down Current for VCn at not monitoring VBATOUT (n=1, 2, 3) Current for VC1 at monitoring of VBATOUT Current for VC2 at monitoring of VBATOUT Current for VC3 at monitoring of VBATOUT Current for CTL1 at Low Current for CTLn at High n=2, 3, 4 Current for CTLn at Low n=2, 3, 4 OUTPUT CURRENT Leak current COP Sink current COP Source current DOP Sink current DOP Source current VBATOUT Sink current VBATOUT ICOH ICOL IDOH IDOL IVBATH IVBATL VCOP=24 V VCOP=VSS+0.5 V VDOP=VDD−0.5 V VDOP=VSS+0.5 V VBATOUT=VDD−0.5 V VBATOUT=VSS+0.5 V ⎯ 10 10 10 100 100 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 ⎯ ⎯ ⎯ ⎯ ⎯ μA μA μA μA μA μA 9 9 9 9 9 9 IOPE IPDN IVCnN IVC1 IVC2 IVC3 ICTL1L ICTLnH ICTLnL V1=V2=V3=V4=3.5 V, VMP=VDD V1=V2=V3=V4=1.5 V, VMP=VSS V1=V2=V3=V4=3.5 V V1=V2=V3=V4=3.5 V V1=V2=V3=V4=3.5 V V1=V2=V3=V4=3.5 V, VCTL1=0 V V1=V2=V3=V4=3.5 V, VCTL1=0 V VCTLn=VOUT VCTLn=0 V ⎯ ⎯ −0.3 ⎯ ⎯ ⎯ −0.4 ⎯ −5 65 ⎯ 0 3.2 2.0 1.0 −0.2 2.5 −2.5 120 0.1 0.3 10.4 7.2 4.0 ⎯ 5 ⎯ μA μA μA μA μA μA μA μA μA 1 1 3 3 3 3 5 9 9 Symbol Remarks Min. Typ. Max. Unit Test circuit Applied to S-8243BAEFT and S-8243BAFFT Item DELAY TIME Overcharge detection delay time Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 tCU tDL tlOV1 tlOV2 tlOV3 CCT=0.1 μF CDT=0.1 μF CDT=0.1 μF ⎯ ⎯ 0.5 50 5 1.5 100 1.0 100 10 2.5 300 1.5 150 15 4.0 600 s ms ms ms μs 5 5 5 4 4 Symbol Conditions Min. Typ. Max. Unit Test circuit Applied to S-8243BADFT Item DELAY TIME Overcharge detection delay time Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 tCU tDL tlOV1 tlOV2 tlOV3 CCT=0.1 μF CDT=0.1 μF CDT=0.1 μF ⎯ ⎯ 0.5 55.5 3.31 1.5 100 1.0 111 6.62 2.5 300 1.5 222 13.2 4.0 600 s ms ms ms μs 5 5 5 4 4 Symbol Conditions Min. Typ. Max. Unit Test circuit *1. Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n overdischarge detection voltage n, and overdischarge release voltage n. *2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2. Seiko Instruments Inc. 11 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 Test Circuits In this chapter test methods are explained for the case of S-8243B series, which is designed for 4-serial cell pack. For the case of S-8243A series, which is designed for 3-serial cell, voltage source V2 should be shorted, V3 should be read as V2, and V4 as V3. 1. Current consumption (Test circuit 1) Current consumption at not monitoring VBATOUT, IOPE , is a current measured at the VSS pin when V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. Current consumption at power down, IPDN, is a current measured at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VMP = VSS. 2. Voltage regulator (Test circuit 2) Output voltage of the regulator VOUT is a voltage measured at the VREG pin when VDD = VMP = 14 V and IOUT = 3 mA. Line regulation of the voltage regulator ΔVOUT1 is defined by the equation ΔVOUT1 = VOUT2−VOUT1 where VOUT1 is the output voltage when VDD = VMP = 6 V and IOUT = 3 mA, and VOUT2 is the output voltage when VDD = VMP = 18 V and IOUT = 3 mA. Load regulation of the regulator is defined by the equation ΔVOUT2 = VOUT3−VOUT where VOUT3 is the output voltage when VDD = VMP = 14 V and IOUT = 5 μA. 3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3) Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the measurement result provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin expressed by the following table at the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to VC3, IVCn and IVCnN are at the same time measured. Table 8 CTL3 pin status VCTL3H min. VCTL3H min. VCTL3H min. Open Open Open VCTL3L max. VCTL3L max. CTL4 pin status VCTL4H min. Open VCTL4L max. VCTL4H min. Open VCTL4L max. VCTL4H min. Open VBATOUT pin output VOFF1 VBAT1 VOFF2 VBAT2 VOFF3 VBAT3 VOFF4 VBAT4 VCn (n=1, 2, 3) pin current IVC1 at VC1 pin ⎯ IVC2 at VC2 pin ⎯ IVC3 at VC3 pin ⎯ IVCnN at VCn pin (n=1, 2, 3) ⎯ Voltage gain of the battery monitor amp for each cell is calculated by the equation GAMPn = (VBATn −VOFFn) / Vn (n = 1 to 4) 4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4) 〈〈Overcharge detection voltages, hysteresis voltages, and overdischarge detection voltages〉〉 In the following VMP = VDD and the CDT pin is open. The COP pin and the DOP pin should provide “Low”, which is a voltage equal to VDD × 0.1 V or lower, in the condition that V1 = V2 = V3 = V4 = 3.5 V. The overcharge detection voltage VCU1 is defined by the voltage at which COP pin voltage becomes “High”, which is a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1 = 3.5 V. The overcharge release voltage VCL1 is defined by the voltage at which COP pin voltage becomes “Low” when the voltage V1 is gradually decreased. The hysteresis voltage of the overcharge detection VHC1 is then defined by the difference between the overcharge detection voltage VCU1 and the overcharge release voltage VCL1. 12 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series The overdischarge detection voltage VDL1 is defined by the voltage at which DOP pin voltage becomes “High” when the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage VDU1 is defined by the voltage at which DOP pin voltage becomes “Low” when the voltage V1 is gradually increased. The hysteresis of the overdischarge detection voltage VHD1 is then defined by the difference between the overdischarge release voltage VDU1 and the overdischarge detection voltage VDL1. Other overcharge detection voltage VCUn, hysteresis voltage of overcharge detection VHCn, overdischarge detection voltage VDLn, and hysteresis of the overdischarge detection voltage VHDn ( for n = 2 to 4) are defined in the same manner as in the case for n = 1. 〈〈Overcurrent detection voltages〉〉 Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. The DOP pin voltage thus provides “Low” The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD − VMP at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased. Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD and the CDT pin voltage VCDT = VSS . The DOP pin voltage thus provides “Low”. The overcurrent detection voltage 2, VIOV2 is defined by the voltage difference VDD−VMP at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased. The overcurrent detection delay time 2, tIOV2 is a time needed for the DOP pin to become “High” from “Low” when the VM pin voltage is changed quickly to VIOV2 min.−0.2 V from the starting condition VMP = VDD. The overcurrent detection voltage 3, VIOV3 is defined by the voltage of the VM pin at which the DOP pin voltage becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms. The overcurrent detection delay time 3, tIOV3 is a time needed for the DOP pin to become “High” from “Low” when the VM pin voltage is changed quickly to VIOV3 min.−0.2 V from the starting condition VMP = VDD. 5. CTL1 pin current, overcharge detection delay, overdischarge detection delay, and overcurrent detection delay 1 (Test circuit 5) Starting condition is V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. Current that flows between the CTL1 pin and VSS is the CTL1 pin current ICTL1L. The overcharge detection delay time tCU is a time needed for the COP pin voltage to change from “Low” to “High” just after the V1 voltage is rapidly increased from 3.5 V to 4.5 V. The overdischarge detection delay time tDL is a time needed for the DOP pin voltage to change from “Low” to “High” just after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V. The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to “High” just after the VMP pin voltage is decreased from VDD to VDD−0.35 V when V1 = 3.5 V. 6. Input voltages for CTL1 and CTL2 (Test circuit 6) Starting condition is V1 = V2 = V3 = V4 = 3.5 V. Pin voltages of the COP and the DOP should be “High” when VCTL1 = VCTL1H min. and CTL2 is OPEN. Pin voltages of the COP and the DOP should be “Low” when VCTL1 = VCTL1L max. and CTL2 is OPEN. Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2H min. Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2L max. Seiko Instruments Inc. 13 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 7. 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage (Test circuit 7) One of the 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage is applied to each product according to the 0V battery charging function. Starting condition is V1 = V2 = V3 = V4 = 0 V for a product in which 0 V battery charging is available. The COP pin voltage should be lower than V0CHA max.−1 V when the VMP pin voltage VMP = V0CHA max. Starting condition is V1 = V2 = V3 = V4 = V0INH for a product in which 0 V battery charging is inhibited. The COP pin voltage should be higher than VMP−1 V when the VMP pin voltage VMP = 24 V. 8. Internal resistance (Test circuit 8) The resistance between VDD and VMP is RVDM and is calculated by the equation RVDM = VDD / IVDM where IVDM is a VMP pin current after VMP is changed to VSS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD. The resistance between VSS and VMP is RVSM and is calculated by the equation RVSM = VDD / IVSM where IVSM is a VMP pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and VMP = VDD. 9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9) Starting condition is V1 = V2 = V3 = V4 = 3.5 V. Pin current for CTL2 at “High” is ICTL2H and is obtained by setting VCTL2 = VOUT. Pin current for CTL2 at “Low” is ICTL2L and is obtained by setting VCTL2 = VSS. Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2. Pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, VMP = VDD, and VCOP = VDD. And pin current for COP at “Low” is ICOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VCOP = 0.5 V. Pin current for DOP at “Low” is IDOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VDOP = 0.5 V. And pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, VMP = VDD−1 V, and VDOP = VDD−0.5 V. Pin current for VBATOUT at “High” is IVBATH and is obtained by setting CTL3 and CTL4 are open and VBATOUT = VOFF3−0.5 V. And pin current for VBATOUT at “Low” is IVBATL and is obtained by setting VBATOUT = VOFF3+0.5 V. 1 V DD 2 DOP 3 COP 4 VMP V1 5 VC1 V2 6 VC2 V3 V4 7 V C3 CCT 10 C DT 9 7 VC3 8 V SS CCT 10 C DT 9 V REG 16 C TL1 15 C TL2 1 4 C TL3 13 C TL4 1 2 VBATOUT 11 1 VDD 2 D OP 3 COP 4 V MP 5 V C1 6 V C2 VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 V BATOUT 11 V A 8 VSS C1=1 μ F C1= 1 μ F IOUT Test circuit 1 Test circuit 2 14 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series R1=1 MΩ 1 VDD 2 DOP 3 COP 4 VMP V1 V2 V3 V4 VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 1 VDD 2 DOP 3 COP 4 VMP V1 5 VC1 V2 V3 6 VC2 7 VC3 VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 A A A 5 VC1 6 VC2 7 VC3 8 VSS V V4 8 VSS V C1=1 μF V C1=1 μF Test circuit 3 1 VDD 2 DOP 3 COP 4 VMP V1 5 VC1 V2 V3 V4 6 VC2 7 VC3 8 VSS CTL4 12 VBATOUT 11 CCT 10 CDT 9 VREG 16 CTL1 15 CTL2 14 Test circuit 4 R1=1 MΩ 1 VDD VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 A 2 DOP 3 COP CTL3 13 4 VMP V1 5 VC1 V2 V3 6 VC2 7 VC3 8 VSS V V C3=0.1 μF C2=0.1 μF C1=1 μF V4 C1=1 μF Test circuit 5 R1=1 MΩ 1 VDD 2 DOP 3 COP V1 V2 V3 6 VC2 7 VC3 8 VSS 4 VMP 5 VC1 VREG 16 CTL1 15 Test circuit 6 1 VDD 2 DOP 3 COP VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 C1=1 μF V1 V2 V3 V4 6 VC2 7 VC3 8 VSS A 4 VMP 5 VC1 V V4 C1=1 μF Test circuit 7 1 VDD VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 Test circuit 8 A A V1 2 DOP 3 COP 4 VMP 5 VC1 A A A A V2 6 VC2 V3 V4 7 VC3 8 VSS C1=1 μF Test circuit 9 Figure 5 Seiko Instruments Inc. 15 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 Operation 1. Battery protection circuit Battery protection protects batteries from overcharge and overdischarge, and also protects external FETs from overcurrent. 1-1 Normal condition When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than a specified value (the VMP pin voltage is lower than VIOV1), the charging and discharging FETs are turned on. 1-2 Overcharge condition When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP pin becomes high impedance and is pulled up to EB+ pin voltage by an external resistor, and the charging FET is turned off to stop charging. The overcharge condition is released when one of the following two conditions holds. a) All battery voltages become lower than VCUn + VHCn. b) VDD−VMP>VIOV1 (A load is connected, and discharging starts.) 1-3 Overdischarge condition When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. After discharging is stopped due to overdischarge condition, the S-8243 enters power down condition. 1-4 Power down condition After stopping discharging due to overdischarge condition, the S-8243 enters power down condition. In this condition, almost all circuits of the S-8243 are stopped to save current consumption. The current consumption becomes lower than IPDN. In the power down condition, the VMP pin is pulled down to VSS level by the internal RVSM resistor. In power down condition, output pin voltages are fixed at the following levels. a) COP VSS (Charging FET is turned on) b) DOP VDD (Discharging FET is turned off) c) VREG VSS (Voltage regulator circuit is off) d) VBATOUT VSS (Battery voltage monitor amp circuit is off) The power down condition is released when the following condition holds. a) VMP>VIOV3 (A charger is connected, and charging starts.) The overdischarging status is released when the following condition holds. a) All of the battery voltages are VDLn or higher, and the VMP pin voltage is VDD/2 or higher. (A charger is connected.) 1-5 Overcurrent condition The S-8243 has three overcurrent detection levels (VIOV1, VIOV2 and VIOV3) and three overcurrent detection delay times (tIOV1, tIOV2 and tIOV3) corresponding to each overcurrent detection levels. When the discharging current becomes higher than a specified value (the voltage between VDD and VMP is greater than VIOV1) and the state continues for tIOV1 or longer, the S-8243 enters the overcurrent condition in which the DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to EB+ pin voltage by an external resistor to turn off the charging FET to stop charging, and the VMP pin is pulled up to VDD voltage by the internal resistor RVDM. Operation of two other overcurrent detection levels (VIOV2 and VIOV3) and overcurrent detection delay times (tIOV2 and tIOV3) is the same as that for VIOV1 and tIOV1. The overcurrent condition is released when the following condition holds. a) VMP>{VIOV3 / (1−VIOV3) × 3 / 5−2 / 5} × RVDM (A load is released, and the impedance between the EB− and EB+ pin becomes higher.) 16 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series 1-6 0 V battery charging function Regarding the charging of a self-discharged battery (0 V battery) the S-8243 has two functions from which one should be selected. a) 0 V battery charging is allowed (0 V battery charging is available) When a charger voltage is higher than V0CHA, 0 V battery can be charged. b) 0 V battery charging is forbidden (0 V battery charging is impossible) When one of the battery voltages is lower than V0INH, 0 V battery can not be charged. Caution When the VDD pin voltage is lower than minimum of VDSOP, the operation of S-8243 series is not guaranteed. 1-7 Delay time setting Overcharge detection delay times (tCU1 to tCU4) are determined by the external capacitor at the CCT pin. Overdischarge detection delay times (tDL1 to tDL4) and overcurrent detection delay time 1 (tIOV1) are determined by the external capacitor at CDT pin. Overcurrent detection delay time 2,3 (tIOV2, tIOV3) are fixed internally. S-8243AAC, AAD, BAE, BAF min. typ. max. = Delay factor ( 5 10 15 )×CCT [μF] tCU [s] tDL [ms] = Delay factor ( 500 1000 1500 )×CDT [μF] tIOV1 [ms] = Delay factor ( 50 100 150 )×CDT [μF] S-8243BAD min. typ. max. = Delay factor ( 5 10 15 )×CCT [μF] tCU [s] tDL [ms] = Delay factor ( 555 1110 2220 )×CDT [μF] tIOV1 [ms] = Delay factor ( 33.1 66.2 132 )×CDT [μF] 2. Voltage regulator circuit Built-in voltage regulator can be used to drive a micro computer, etc. The voltage regulator supplies voltage of 3.3 V (3 mA maximum) and an external capacitor is needed. Caution In the power down condition the voltage regulator output is pulled down to the VSS level by an internal resistor. 3. Battery monitor amp circuit Battery monitor amp sends information of the batteries to a microcomputer. The battery monitor amp output is controlled and selected by CTL3 and CTL4 pins to give the following two voltages. a) VBATn = GAMPn × VBATTERYn + VOFFn where GAMPn is the n-th voltage gain of the amp, V BATTERYn is the n-th battery voltage, and VOFFn is the n-th offset voltage of the amp. b) N-th offset voltage VOFFn Each battery voltage VBATTERYn (n = 1 to 4) is thus calculated by following equation. VBATTERYn = {(VBATn − VOFFn} / GAMPn (n=1,2,3,4) After the state of CTL3 and CTL4 are changed, a time between 25 μs and 250 μs is needed for the battery monitor amp to become stable. Caution In the power down condition the battery monitor amp output is the VSS level. Seiko Instruments Inc. 17 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 4. CTL pins The S-8243 has four control pins. The CTL1 and CTL2 pins are used to control the COP and DOP pin output voltages. CTL1 takes precedence over CTL2. CTL2 takes precedence over the battery protection circuit. The CTL3 and CTL4 pins are used to control the VBATOUT pin output voltage. Table 9 CTL1 and CTL2 Mode Input Output CTL1 pin CTL2 pin External discharging FET External charging FET High High OFF OFF High Open OFF OFF High Low OFF OFF Open High OFF OFF Open Open OFF OFF Open Low OFF OFF Low High Normal*1 OFF*2 *1 Low Open Normal Normal*1 Low Low OFF Normal*1 *1. States are controlled by voltage detection circuit. *2. Off state is brought after the overcharge detection delay time tCU. Table 10 CTL3 and CTL4 Mode Input Output CTL3 pin CTL4 pin VBATOUT (A series) VBATOUT (B series) High High V1 Offset V1 Offset High Open V1×0.2 + V1 Offset V1×0.2 + V1 Offset High Low Don’t use. V2 Offset Open High Don’t use. V2×0.2 + V2 Offset Open*1 Open*1 V2 Offset V3 Offset Open Low V2×0.2 + V2 Offset V3×0.2 + V3 Offset Low High V3 Offset V4 Offset Low Open V3×0.2 + V3 Offset V4×0.2 + V4 Offset Low Low Don’t use. Don’t use. *1. CTL3 and CTL4 pins should be open when a microcomputer is not used. Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations. 18 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Timing Charts 1. Overcharge detection, Over discharge detection VCUn VCLn Battery voltage VDUn VDLn (n= 1~4) VDD DOP pin voltage VSS VDD COP pin voltage VSS VDD VIOV1 VMP pin voltage VSS VOUT VBAT VBATOUT pin *1 voltage VSS VDD VOUT VREG pin votage VSS Charger connected Load connected Overcharge detection delay time (tCU) Overdischarge detection delay time (tDL) Hi-Z Hi-Z Mode *2 *1. State depends on CTL3 and CTL4 input levels. Refer to Figure 9. *2. : Normal mode, : Overcharge mode, : Overdischarge mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 6 Seiko Instruments Inc. 19 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 2. Overcurrent detection Battery voltage VCU VCL VDU VDL VHC VHD VDD DOP pin voltage VSS COP pin voltage VSS VDD VIOV1 VIOV2 VIOV3 VSS VOUT VBATOUT VBAT *2 pin voltage VSS VDD VREG pin voltage VOUT VSS Charger connected Load connected Overcurrent detection delay time 1 ( tIOV1) Hi-Z Hi-Z Hi-Z VMP pin voltage VRETURN *1 Overcurrent detection delay time 2 ( tIOV2) Overcurrent detection delay time 3 ( tIOV3) Mode *3 *1. VRETURN = VDD / 6 (typ.) *2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9. *3. : Normal mode, : Overcurrent mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 7 20 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series 3. CTL1, CTL2 pin voltage VDD DOP pin Voltage VSS VDD COP pin Voltage VSS VOUT VBATOUT V BAT *2 pin Voltage VSS VDD VREG pin Voltage VOUT VSS VDD CTL1 pin Voltage VOUT OPEN VSS VDD CTL2 pin Voltage VOUT OPEN VSS *1. State depends on each battery voltage and the VMP pin voltage. *2. State depends on CTL3 and CTL4 input levels. Refer to Figure 8. Figure 8 VDD VDD VDD VDD VDD VDD Normal *1 Normal *1 VDD Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Normal*1 Normal*1 Seiko Instruments Inc. 21 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 4. CTL3, TL4 pin voltage VDD DOP pin *1 voltage (1) VSS (1) (1) (1) (1) (1) (1) (1) (1) COP pin *1 voltage VSS VOUT VBAT VOFF VSS VOUT VBAT VOFF VSS VDD VREG pin voltage VOUT VSS VDD CTL3 pin voltage VOUT OPEN VSS VDD CTL4 pin voltage VOUT OPEN VSS (1) (1) (1) (1) (1) (1) (1) (1) (1) S-8243A (3-serial cell) VBATOUT pin voltage V1 × 0.2 V1 offset +V1 offset Don’t use Don’t use V3 × 0.2 V2 offset +V2 offset V3 offset +V3 offset V2 × 0.2 Don’t use S-8243B (4-serial cell) VBATOUT pin voltage V1 × 0.2 V2 × 0.2 V3 × 0.2 V4 × 0.2 V1 offset +V1 offset V2 offset +V2 offset V3 offset +V3 offset V4 offset +V4 offset Don’t use *1. State depends on CTL1 and CTL2 and each battery voltage and the VMP pin voltage. Refer to Figure 6 to 8. Figure 9 22 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Battery Protection IC Connection Example 1. S-8243A Series Discharging FET Charging FET EB+ RCOP RDOP 1 VDD 2 DOP 3 COP 4 VMP VREG 16 CTL1 15 RCTL1 CTL2 14 RCTL2 CTL3 13 Microcomputer CVREG RVMP CTL1 S-8243A 5 VC1 CVC2 6 VC2 RVC2 RVC3 RVSS CCDT CVSS 8 VSS CDT 9 CVC3 7 VC3 CCT 10 VBATOUT 11 CTL4 12 RCTL3 RCTL4 RVBAT CCCT EB- Figure 10 Table 11 Constants for External Components No. Part Typ. Range Unit *1 1 RVC2 1 0.51 to 1 kΩ 2 RVC3 1 0.51 to 1*1 kΩ 3 RVSS 10 2.2 to 10*1 Ω 4 RDOP 5.1 2 to 10 kΩ 5 RCOP 1 0.1 to 1 MΩ 6 RVMP 5.1 1 to 10 kΩ 7 RCTL1 1 1 to 100 kΩ 8 RCTL2 1 1 to 10 kΩ 9 RCTL3 1 1 to 10 kΩ 10 RCTL4 1 1 to 10 kΩ 11 RVBAT 0 0 to 100 kΩ 12 CVC2 0.047 0.047 to 0.22*1 μF 13 CVC3 0.047 0.047 to 0.22*1 μF 14 CVSS 4.7 2.2 to 10*1 μF 15 CCCT 0.1 More than 0.01 μF 16 CCDT 0.1 More than 0.02 μF 17 CVREG 4.7 0.68 to 10 μF *1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS. Caution1. No resistance should be inserted in the power supply pin VDD. 2. The above constants are subject to change without prior notice. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Seiko Instruments Inc. 23 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 2. S-8243B Series Discharging FET Charging FET EB+ RCOP RDOP 1 VDD 2 DOP 3 COP 4 VMP CVC1 5 VC1 RVC1 RVC2 RVC3 RVSS CCDT CVSS 8 VSS CDT 9 CVC3 7 VC3 CCT 10 CCCT CVC2 6 VC2 VBATOUT 11 RVBAT VREG 16 CTL1 15 RCTL1 CTL2 14 RCTL2 CTL3 13 Microcomputer CVREG RVMP CTL1 S-8243B CTL4 12 RCTL3 RCTL4 EB- Figure 11 Table 12 Constants for External Components No. Part Typ. Range Unit 1 RVC1 1 0.51 to 1*1 kΩ 2 RVC2 1 0.51 to 1*1 kΩ *1 3 RVC3 1 0.51 to 1 kΩ 4 RVSS 10 2.2 to 10*1 Ω 5 RDOP 5.1 2 to 10 kΩ 6 RCOP 1 0.1 to 1 MΩ 7 RVMP 5.1 1 to 10 kΩ 8 RCTL1 1 1 to 100 kΩ 9 RCTL2 1 1 to 10 kΩ 10 RCTL3 1 1 to 10 kΩ 11 RCTL4 1 1 to 10 kΩ 12 RVBAT 0 0 to 100 kΩ 13 CVC1 0.047 0.047 to 0.22*1 μF *1 14 CVC2 0.047 0.047 to 0.22 μF 15 CVC3 0.047 0.047 to 0.22*1 μF 16 CVSS 4.7 2.2 to 10*1 μF 17 CCCT 0.1 More than 0.01 μF 18 CCDT 0.1 More than 0.02 μF 19 CVREG 4.7 0.68 to 10 μF *1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be RVC1 × CVC1 = RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS. Caution1. No resistance should be inserted in the power supply pin VDD. 2. The above constants are subject to change without prior notice. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 24 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Precautions • Pay attention to the operating conditions for input/output voltage and load current so that the power loss in the IC does not exceed the package power dissipation. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • Seiko Instruments Inc. shall not be responsible for any patent infringement by products including the S-8243 series, the method of using the S-8243 series in such products, the product specifications or the country of destination thereof. Seiko Instruments Inc. 25 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 The Example of Application Circuit 1. S-8243A Series EB+ CTL1 REG 1 VDD 2 DOP 3 COP 4 VMP 5 VC1 6 VC2 7 VC3 8 VSS VREG 16 VCC LED1 LED2 LED3 LED5 DISP VOUT ESCL ESCD SMBC SMBD VT HDQ RB1 VSS SR2 SR1 SRC SMBus VCC SCL SDA A0 A2 WP GND VREG VREG S-8243A CTL1 15 CTL2 14 Bq2063 LED4 CTL2 CTL3 CTL4 VREG VCELL1 THON CTL3 13 CTL4 12 VBATOUT 11 CCT 10 CDT 9 S-24C A1 EB− Figure 12 2. S-8243B Series EB+ CTL1 REG 1 VDD 2 DOP 3 COP 4 VMP 5 VC1 6 VC2 7 VC3 8 VSS VREG 16 CTL1 15 CTL2 14 CTL3 13 CTL4 12 VBATOUT 11 CCT 10 THON CDT 9 VT HDQ RB1 VSS SR2 SR1 SRC VREG VCC LED1 LED2 LED3 LED5 DISP VOUT ESCL ESCD SMBC SMBD SMBus VCC SCL SDA A0 A2 WP GND VREG VREG S-8243B Bq2063 LED4 CTL2 CTL3 CTL4 VCELL1 S-24C A1 EB- Figure 13 Caution The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 26 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Characteristics (Typical Data) 1. Current consumption S-8243BAF IOPE - VDD 120 100 S-8243BAF IOPE - Temp 120 100 IOPE (μA) 60 40 20 0 0 4 8 12 16 20 24 IOPE (μA) 80 80 60 40 20 0 -40 -20 0 20 40 60 80 VDD (V) Ta (°C) S-8243BAF IPDN - VDD 0.10 0.08 S-8243BAF 0.10 0.08 IPDN - Temp IPDN (μA) IPDN (μA) 0.06 0.04 0.02 0.00 0 4 8 12 16 20 24 0.06 0.04 0.02 0.00 -40 -20 0 20 40 60 80 VDD (V) Ta (°C) 2. Overcharge detection/release voltage, overdischarge detection/release voltage, overcurrent detection voltages, and delay times S-8243BAF S-8243BAF S-8243BAF VCU - Temp 4.275 4.270 4.265 4.260 4.255 4.250 4.245 4.240 4.235 4.230 4.225 -40 -20 0 20 40 60 80 VCL - Temp 4.05 4.03 2.500 2.475 2.450 2.425 2.400 2.375 2.350 2.325 2.300 -40 -20 0 VDU - Temp VCU (V) VCL (V) 3.99 3.97 3.95 -40 -20 0 20 40 60 80 VDU (V) 4.01 20 40 60 80 Ta (°C) Ta (°C) Ta (°C) S-8243BAF VDL - Temp 2.48 2.46 2.44 2.42 2.40 2.38 2.36 2.34 2.32 -40 -20 0 20 40 60 80 S-8243BAF VIOV1 - VDD 0.225 0.220 0.215 0.210 0.205 0.200 0.195 0.190 0.185 0.180 0.175 10 12 14 16 S-8243BAF VIOV1 - Temp 0.225 0.220 0.215 0.210 0.205 0.200 0.195 0.190 0.185 0.180 0.175 -40 -20 0 20 40 60 80 VIOV1 (V) Ta (°C) VDD (V) VIOV1 (V) VDL(V) Ta (°C) Seiko Instruments Inc. 27 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 S-8243BAF -0.40 -0.45 VIOV2 - VDD VDD Reference S-8243BAF -0.40 VIOV2 - Temp VDD Reference S-8243BAF VIOV3 - VDD 0.575 0.550 VIOV3 /VDD(−) -0.45 VIOV2 (V) VIOV2 (V) 0.525 0.500 0.475 0.450 0.425 -0.50 -0.55 -0.60 10 12 14 16 -0.50 -0.55 -0.60 -40 -20 0 20 40 60 80 10 12 14 16 VDD (V) Ta (°C) VDD (V) S-8243BAF VIOV3 - Temp 0.575 0.550 S-8243BAF tCU - CCT 15 S-8243BAF 2.5 2.0 tCU - Temp CCT=0.1μF VIOV3 /VDD(−) 0.525 0.500 0.475 0.450 0.425 -40 -20 0 20 40 60 80 10 tCU (s) tCU (s) 1.5 1.0 0.5 5 0 0 0.2 0.4 0.6 0.8 1 0.0 -40 -20 0 20 40 60 80 Ta (°C) CCT ( μF) Ta (°C) S-8243BAF tDL - CDT 1500 S-8243BAF 250 200 tDL- Temp CDT=0.1μF S-8243BAF 150 tIOV1 - CDT tDL (ms) tDL (V) 150 100 50 500 tIOV1 (ms) -40 -20 0 20 40 60 80 1000 100 50 0 0 0.2 0.4 0.6 0.8 1 0 0 0 0.2 0.4 0.6 0.8 1 CDT ( μF) Ta (°C) C DT ( μF) S-8243BAF 25 20 tIOV1 - Temp CDT =0.1μF S-8243BAF tIOV2 -Temp 4.0 3.5 S-8243BAF tIOV3 -Temp 600 500 tIOV1 (ms) 3.0 2.5 2.0 1.5 tIOV3 (μs) -40 -20 0 20 40 60 80 15 10 5 0 -40 -20 0 20 40 60 80 tIOV2 (ms) 400 300 200 100 -40 -20 0 20 40 60 80 Ta (°C) Ta (°C) Ta (°C) 28 Seiko Instruments Inc. Rev.2.4_00 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series 3. COP/DOP pin current S-8243BAF ICOH - VCOP 0.10 0.08 0.06 0.04 0.02 0.00 0 4 8 12 16 20 24 S-8243BAF ICOL - VCOP 40 35 30 25 20 15 10 5 0 0 3.5 7 10.5 14 VCOP (V) ICOL (m A) ICOH (μA) VCOP (V) S-8243BAF IDOH - VDOP 0 -1 S-8243BAF 40 35 30 25 20 15 10 5 0 0 3.5 7 IDOL - VDOP IDOH (m A) -2 -3 -4 -5 0 1.8 3.6 5.4 7.2 IDOL (m A) 10.5 14 VDOP (V) VDOP (V) 4. Voltage regulator S-8243BAF VOUT - Temp 3.6 3.5 S-8243BAF 3.8 VOUT - VDD VDD =0→24V, Ta=25°C S-8243BAF 4.0 VOUT - IOUT V1=V2=V3=V4=VBAT IOUT = 5μA VOUT (V) VOUT (V) 3.4 3.3 3.2 3.1 3.0 -40 -20 0 20 40 60 80 3.3 100μA 2.8 10mA 3mA 2.3 0 4 8 12 16 20 24 3.0 VOUT (V) 2.0 1.0 0.0 0 20 VDD=6V 18V 10V 14V Ta (°C) VDD (V) 40 60 80 100 IOUT (mA) S-8243BAF VOUT - IOUT 4.0 3.0 VOUT (V) 85°C 2.0 1.0 0.0 0 20 40 60 80 100 25°C Ta=-40°C IOUT (mA) Seiko Instruments Inc. 29 BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK S-8243A/B Series Rev.2.4_00 5. Battery monitor amp S-8243BAF 180 175 V OFF1 VOFF - VBAT V1=V2=V3=V4=VBAT S-8243BAF VOFF - Temp 180 175 VOFF (mV) 170 165 160 155 150 5 S-8243BAF 0.202 VOFF2 VOFF1 GAMP (−) 0.201 0.200 0.199 0.198 GAMP2 GAMP3 GAMP - VBAT V1=V2=V3=V4=VBAT GAMP4 VOFF (mV) 170 165 160 155 150 1 V OFF2 V OFF3 2 3 V OFF4 4 VOFF3 VOFF4 1 2 GAMP1 3 VBAT (V) 4 5 VBAT (V) -40 -20 0 20 40 60 80 Ta (°C) S-8243BAF GAMP- Temp 0.202 0.201 GAMP (−) GAMP3 GAMP4 0.200 0.199 GAMP2 GAMP1 0.198 -40 -20 0 20 40 60 80 Ta (°C) 30 Seiko Instruments Inc. 5.1±0.2 16 9 1 8 0.17±0.05 0.65 0.22±0.08 No. FT016-A-P-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A-PKG Dimensions FT016-A-P-SD-1.1 mm Seiko Instruments Inc. ø1.5 -0 +0.1 4.0±0.1 2.0±0.1 0.3±0.05 8.0±0.1 ø1.6±0.1 (7.2) 4.2±0.2 1.5±0.1 6.5 -0.2 +0.4 1 16 8 9 Feed direction No. FT016-A-C-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A-Carrier Tape FT016-A-C-SD-1.1 mm Seiko Instruments Inc. 21.4±1.0 17.4±1.0 17.4 -1.5 +2.0 Enlarged drawing in the central part ø21±0.8 2.0±0.5 ø13.0±0.2 No. FT016-A-R-SD-1.1 TITLE No. SCALE UNIT TSSOP16-A- Reel FT016-A-R-SD-1.1 QTY. mm 2,000 Seiko Instruments Inc. • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.