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S-8550AA-I8T1U

S-8550AA-I8T1U

  • 厂商:

    SII(精工半导体)

  • 封装:

    SMD8

  • 描述:

    Buck Switching Regulator IC Positive Adjustable 1.1V 1 Output 600mA 8-SMD, Flat Lead

  • 数据手册
  • 价格&库存
S-8550AA-I8T1U 数据手册
S-8550 Series STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS www.ablic.com www.ablicinc.com Rev.5.0_02 © ABLIC Inc., 2007-2015 The S-8550 Series is a CMOS synchronous rectification step-down switching regulator which mainly consists of a reference voltage circuit, an oscillator, an error amplifier, a phase compensation circuit, a PWM controller, an under voltage lockout circuit (UVLO), a current limit circuit, and a power MOS FET. The oscillation frequency is high at 1.2 MHz, so a high efficiency, large output current, step-down switching regulator can be achieved by using small external parts. The built-in synchronous rectification circuit makes achieving high efficiency easier compared with conventional step-down switching regulators. A ceramic capacitor can be used as an output capacitor. High-density mounting is supported by adopting packages small SOT-23-5 and super-small and thin SNT-8A.  Features  Oscillation frequency: 1.2 MHz  Input voltage range: 2.0 V to 5.5 V  Output voltage range: Arbitrarily settable by external output voltage setting resistor  Output current: 600 mA  Reference voltage: 0.6 V 2.0%  Efficiency: 92%  Soft-start function: 1 ms typ.  Shutdown function: Shutdown current consumption : 1.0 A max.  Built-in current limit circuit  Pch power MOS FET on-resistance: 0.4  typ.  Nch power MOS FET on-resistance: 0.3  typ.  Constant continuous mode operation (no light load mode)  Lead-free, Sn 100%, halogen-free*1 *1. Refer to “ Product Name Structure” for details.  Applications  Mobile devices, such as mobile phones, Bluetooth devices, wireless devices, digital audio players, digital still cameras, portable DVD players, and portable CD players  Packages  SOT-23-5  SNT-8A 1 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Block Diagram 1. SOT-23-5 VIN Current limit circuit FB IC internal power supply Error amplifier     Reference voltage PWM control circuit *1 L Triangular wave generation circuit VIN ON/OFF circuit CIN VOUT CONT PWM comparator *1 CFB RFB1 RFB2 UVLO circuit ON/OFF COUT VSS *1. Parasitic diode Figure 1 2. SNT-8A VIN Current limit circuit FB IC internal power supply Error amplifier     Reference voltage PWM control circuit *1 L Triangular wave generation circuit VIN CIN ON/OFF circuit Figure 2 CFB RFB1 RFB2 VSS *1. Parasitic diode 2 *1 UVLO circuit ON/OFF VOUT CONT PWM comparator PVSS COUT STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Product Name Structure 1. Product name 1. 1 SOT-23-5 S-8550 A A - M5T1 x Environmental code U: Lead-free (Sn 100%), halogen-free G: Lead-free (for details, please contact our sales office) Package name abbreviation and packing specification*1 M5T1: SOT-23-5, tape Oscillation frequency A: 1.2 MHz *1. 1. 2 Refer to the tape drawing. SNT-8A S-8550 A A - I8T1 U Environmental code U: Lead-free (Sn 100%), halogen-free Package name abbreviation and packing specification*1 I8T1: SNT-8A, tape Oscillation frequency A: 1.2 MHz *1. 2. Refer to the tape drawing. Packages Package Name SOT-23-5 SNT-8A Package MP005-A-P-SD PH008-A-P-SD Drawing Code Tape Reel MP005-A-C-SD MP005-A-R-SD PH008-A-C-SD PH008-A-R-SD Land  PH008-A-L-SD 3 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Pin Configurations 1. SOT-23-5 Table 1 Pin No. Symbol Description Top view 1 VIN IC power supply pin 5 2 VSS GND pin 4 Shutdown pin 3 “H” : Power on (normal operation) “L” : Power off (standby) 1 2 3 Figure 3 2. ON/OFF 4 FB Output voltage feedback pin 5 CONT External inductor connection pin SNT-8A Table 2 Top view 1 2 3 4 8 7 6 5 Figure 4 4 Pin No. 1 2 3 Symbol FB NC*1 VSS*2 Description Output voltage feedback pin No connection Small signal GND Pin Shutdown pin “H”:Power on (normal operation) 4 ON/OFF “L”:Power off (standby) 5 VIN IC power supply pin PVSS*2 6 Power GND pin NC*1 7 No connection 8 CONT External inductor connection pin *1. The NC pin is electrically open. The NC pin can be connected to VIN, VSS or PVSS. *2. Connect VSS and PVSS to GND. STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Absolute Maximum Ratings Table 3 Absolute Maximum Ratings (Unless otherwise specified: Ta  25C, VSS  0 V) Item VIN pin voltage FB pin voltage CONT pin voltage ON/OFF pin voltage CONT pin current Power SOT-23-5 dissipation SNT-8A Operating temperature Storage temperature Symbol VIN VFB VCONT VON/OFF ICONT PD Topr Tstg Absolute Maximum Rating Unit VSS  0.3 to VSS + 6.0 VSS  0.3 to VIN + 0.3 VSS  0.3 to VIN + 0.3 VSS  0.3 to VIN + 0.3 1300 600*1 450*1 40 to +85 40 to +125 V V V V mA mW mW C C *1. When mounted on printed circuit board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 1. The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 2. Since this IC has a built-in power MOS FET, make sure that dissipation of the power MOS FET does not exceed the allowable power dissipation of the package. (Refer to Figure 5.) Generally, dissipation of a switching regulator can be calculated by the following equation. Dissipation = (100 (%)  efficiency (%)) / efficiency (%)  output voltage  load current The greater part of dissipation depends on the built-in power MOS FET, however, dissipation of the inductor is also included. In addition, since power dissipation of the package also changes according to a mounting board or a mounting state, fully check them using an actually mounted mode. (PD) [mW] 700 600 Power dissipation Caution 400 300 SNT-8A 200 100 0 Figure 5 SOT-23-5 500 0 50 100 150 Ambient temperature (Ta) [C] Power Dissipation of Package (Mounted on Board) 5 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Electrical Characteristics Table 4 Electrical Characteristics (Unless otherwise specified: VIN  3.6 V, VOUT  1.8 V (the conditions in Table 5), Ta  +25C) Item Min. Typ. Max. Unit Test Circuit 2.0 1.1 0.588   0.6 5.5 4.0 0.612 V V V 2 2 2  100  ppm/C 2 VIN = 2.0 V to 5.5 V, FB pin VIN = 2.0 V to 5.5 V, VON/OFF  0 V fosc = 1.2 MHz, no external parts, VFB = VFB(S)  1.1 V ICONT = 100 mA ICONT = 100 mA VIN = 2.0 V to 5.5 V, VON/OFF  0 V, VCONT = 0 or 3.6 V 0.1  +0.1 A 1   1.0 A 1  200 400 A 1   0.4 0.3 0.6 0.5  1  0.01 0.5 A 1   Time required to reach 90% of VOUT(S) VIN = 2.0 V to 5.5 V, ON/OFF pin VIN = 2.0 V to 5.5 V, ON/OFF pin VIN = 2.0 V to 5.5 V, ON/OFF pin VIN = 2.0 V to 5.5 V, ON/OFF pin  800 1.02 1000 1.2 1200 1.38 mA MHz 1 2 0.7 1.0 1.3 ms 2 0.9  0.1 0.1 1.4     1.6  0.3 0.1 0.1 1.78 V V A A V 2 2 1 1 2 Symbol Operating input voltage Output voltage range*1 FB voltage FB voltage temperature coefficient FB pin input current Current consumption during shutdown VIN VOUT VFB VFB Ta IFB Current consumption 1 ISS1 Power MOS FET on-resistance RPFET RNFET ISSS Power MOS FET leakage current Limit current Oscillation frequency ILIM fosc Soft-start time tSS High level input voltage Low level input voltage High level input current Low level input current UVLO detection voltage VSH VSL ISH ISL VUVLO ILSW Condition  VIN = VOUT(S) + 0.4 V to 5.5 V VIN = VOUT(S) + 0.4 V to 5.5 V Ta = 40C to +85C *1. VOUT(S) is the output voltage set value, and VOUT is the typ. value of the actual output voltage. VOUT(S) can be set depending on the ratio between the VFB value and output voltage set resistors (RFB1, RFB2). For details, refer to “ External Parts Selection”.  External Parts When Measuring Electrical Characteristics Table 5 Element Name Inductor Input capacitor Output capacitor Output voltage set resistor 1 Output voltage set resistor 2 Phase compensation capacitor 6 Symbol L CIN COUT RFB1 RFB2 CFB External Parts Constant Manufacturer 3.3 H 4.7 F 10 F 36 k 18 k 68 pF Taiyo Yuden Co., Ltd. TDK Corporation TDK Corporation Rohm Co., Ltd. Rohm Co., Ltd. Murata Manufacturing Co., Ltd. Part Number NR4018T3R3M C3216X7R1E475K C3216X7R1C106K MCR03 Series 3602 MCR03 Series 1802 GRM1882C1H680J STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Test Circuits 1. A VIN CIN CONT S-8550 Series FB ON/OFF VSS PVSS*1 ↓ *1. PVSS pin is unavailable for the S-8550 Series with SOT-23-5. Figure 6 2. L VIN CIN CONT S-8550 Series FB ON/OFF VSS PVSS*1 COUT VOUT CFB RFB1 V ↓ IOUT RFB2 V *1. PVSS pin is unavailable for the S-8550 Series with SOT-23-5. Figure 7 7 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Operation 1. Synchronous rectification PWM control step-down switching regulator 1. 1 Synchronous rectification The synchronous rectification method lowers voltage drop to greatly reduce power dissipation since an Nch power MOS FET, having resistance much lower than conventional switching regulators, is used. In conventional switching regulators, current flows in the diode connected between the GND and CONT pins when the Pch power MOS FET is off. The forward drop voltage (Vf) of such diodes is large, between 0.3 V to 0.7 V, so the power dissipation used to be very large. Synchronous rectification ultra-low resistance Nch transistors repeat on and off, in synchronization with the operation of the Pch driver, in the reverse cycle of the Pch driver. Moreover, the built-in P and N through prevention circuit helps much reduction of power consumption during operation. 1. 2 PWM control The S-8550 Series is a switching regulator using a pulse width modulation method (PWM) and features low current consumption. In conventional PFM control switching regulators, pulses are skipped when the output load current is low, causing a fluctuation in the ripple frequency of the output voltage, resulting in an increase in the ripple voltage. In the S-8550 Series, the switching frequency does not change, although the pulse width changes from 0% to 100% corresponding to each load current. The ripple voltage generated from switching can thus be removed easily using a filter because the switching frequency is constant. 2. Soft-start function The soft-start circuit built in the S-8550 Series controls the rush current and the overshoot of the output voltage when powering on, the ON/OFF pin is switched from the “L” level to the “H” level, or the UVLO operation is released. 3. A reference voltage adjustment method is adopted as the soft-start method. Shutdown pin This pin stops or starts step-up operations. Switching the shutdown pin to the “L” level stops operation of all the internal circuits and reduces the current consumption significantly. pulled down internally. DO NOT use the shutdown pin in a floating state because it is not pulled up or DO NOT apply voltage of between 0.3 V and 0.9 V to the shutdown pin because applying such a voltage increases the current consumption. If the shutdown pin is not used, connect it to the VIN pin. Table 6 Shutdown Pin “H” “L” CR Oscillation Circuit Operates Stops VIN ON/OFF VSS Figure 8 8 Output Voltage Set value Hi-Z STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 4. S-8550 Series Current limit circuit A current limit circuit is built in the S-8550 Series. The current limit circuit monitors the current that flows in the Pch power MOS FET and limits current in order to prevent thermal destruction of the IC due to an overload or magnetic saturation of the inductor. When a current exceeding the current limit detection value flows in the Pch power MOS FET, the current limit circuit operates and turns off the Pch power MOS FET since the current limit detection until one clock of the oscillator ends. The Pch power MOS FET is turned on in the next clock and the current limit circuit resumes current detection operation. If the value of the current that flows in the Pch power MOS FET remains the current limit detection value or more, the current limit circuit functions again and the same operation is repeated. Once the value of the current that flows in the Pch power MOS FET is lowered up to the specified value, the normal operation status restores. A slight overshoot is generated in the output voltage when the current limit is released. The current limit detection value is fixed to 1 A (typ.) in the IC. If the time taken for the current limit to be detected is shorter than the time required for the current limit circuit in the IC to detect, the current value that is actually limited increases. Generally, the voltage difference between the VIN and VOUT pins is large, the current limit detection status is reached faster and the current value increases. 5. 100% duty cycle The S-8550 Series operates up to the maximum duty cycle at 100%. Even when the input voltage is lowered up to the output voltage value set using the external output voltage setting resistor, the Pch power MOS FET is kept on and current can be supplied to the load. The output voltage at this time is the input voltage from which the voltage drop due to the direct resistance of the inductor and the on-resistance of the Pch power MOS FET are subtracted. 6. UVLO function The S-8550 Series includes a UVLO (under-voltage lockout) circuit to prevent the IC from malfunctioning due to a transient status when power is applied or a momentary drop of the supply voltage. When UVLO is in the detection state, the Pch and Nch power MOS FETs stop switching operation, and the CONT pin become Hi-Z. Once the S-8550 Series is in the UVLO detection status, the soft-start function is reset, but the soft-start operates by the releasing operation of UVLO after that. Note that the other internal circuits operate normally and that the status is different from the power-off status. The hysteresis width is set for the UVLO circuit to prevent a malfunction due to a noise that is generated in the input voltage. A voltage about 150 mV (typ.) higher than the UVLO detection voltage is the release voltage. 9 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Operation Principle The S-8550 Series is a step-down synchronous rectification switching regulator based on constant PWM control. Figure 9 shows the basic circuit diagram. A step-down switching regulator starts current supply by the input voltage (VIN) when the Pch power MOS FET is turned on and holds energy in the inductor at the same time. current held in the inductor is released. When the Pch power MOS FET is turned off, the The released current flows in the smoothing circuit, with the energy loss held minimum, supplies the output voltage (VOUT) lower than VIN. switching frequency (fosc) and ON time (ton). VOUT is kept constant by controlling the With the PWM control method, VOUT is made constant by controlling the ON time with fOSC unchanged. I1 L Pch power MOS FET Control circuit VIN Figure 9 1. COUT I2 VOUT Nch power MOS FET Basic Circuit Drawing of Step-down Switching Regulator Continuous mode The following explains how the current flows to the inductor when the step-down operation is constant and stable. When the Pch power MOS FET is turned on, current I1 flows in the direction shown by the arrow in Figure 9, and energy is stored in the inductor (L). When the output capacitor (COUT) is charged, supply of the output current (IOUT) is started at the same time. The inductor current (IL) gradually increases in proportion to the ON time (tON) of the Pch power MOS FET as shown in Figure 10 (changes from IL min. to IL max.). When the Pch power MOS FET is turned off, the Nch power MOS FET is turned on and IL tries to hold IL max. Consequently, current I2 flows in the direction shown by the arrow in Figure 9. reaches IL min. when the OFF time (tOFF) has elapsed. turned off and the next cycle is entered. As a result, IL gradually decreases and When tOFF has elapsed, the Nch power MOS FET is The above sequence is repeated. As explained in the above, the continuous mode refers to the operation in the current cycle in which IL linearly changes from IL min. to IL max. Even if IL min. is less than 0 A, IL min. keeps flowing (backflow current flows). IL IL max. IL min. t ton toff T = 1/fOSC Figure 10 10 Continuous Mode (Current Cycle of Inductor Current (IL)) STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 2. S-8550 Series Backflow current The S-8550 Series performs PWM synchronous rectification even if IL min. is less than 0 A, so a backflow current is generated in VIN and the backflow current becomes maximum when no load is applied (Refer to Figure 11). Use the following equation to calculate the maximum backflow current value, which should be taken into consideration when designing. Duty (IOUT  0)  VOUT / VIN Example : VIN  3.6 V, VOUT  1.8 V …… Duty  50% IL  V / L  ton  (VIN  VOUT)  Duty / (L  fOSC) Example : VIN  3.6 V, VOUT  1.8 V, fOSC  1.2 MHz, L  3.3 H …… IL  227 mA IL max.  IL / 2  113.5 mA, IL min.  IL / 2  113.5 mA The current value waveform of the inductor is a triangular wave, of which the maximum value is IL max. and the minimum value is IL min. (negative value), and the negative value (the portion marked by diagonal lines in Figure 11) backflows when no load is applied (Refer to Figure 11). If about 113.5 mA of IOUT flows in the above conditions, the minimum value (IL min.) of the triangular wave is made 0 mA and no backflow current flows. When an input capacitor (CIN) is connected, the backflow current is absorbed by CIN, thus reducing the backflow current to flow in the power supply. Be sure to connect an input capacitor to reduce backflow current to the power supply (Refer to Figure 12). The above presents the conditions required to prevent backflow current from flowing, which is only a guideline. Perform sufficient confirmation using an actual application. Inductor current with no load Inductor current when load is a current of 113.5 mA IL IL IL max. 227 mA 113.5 mA IL max. IL Backflow current IL min. 0 mA IOUT 113.5 mA Figure 11 IL 113.5 mA IOUT IL min. 0 mA Backflow current = 0 mA Example of Conditions to Prevent Backflow Current from Flowing VIN Backflow current VIN VOUT CONT CIN Inductor current IL Figure 12 Backflow Current 11 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  External Parts Selection 1. Inductor The inductance (L value) has a strong influence on the maximum output current (IOUT) and efficiency (). The peak current (IPK) increases by decreasing L and the stability of the circuit improves and IOUT increases. If L is decreased further, the current drive capability of the external transistor is insufficient and IOUT decreases. If the L value is increased, the loss due to IPK of the power MOS FET decreases and the efficiency becomes maximum at a certain L value. Further increasing L decreases the efficiency due to the increased loss of the DC resistance of the inductor. The recommended L value for the S-8550 Series is 3.3 H. When selecting an inductor, note the allowable current of the inductor. If a current exceeding this allowable current flows through the inductor, magnetic saturation occurs, substantially lowering the efficiency. Therefore, select an inductor so that IPK does not exceed the allowable current. IPK is expressed by the following equations in the discontinuous mode and continuous mode. IPK = IOUT + VOUT  (VIN  VOUT) 2  fOSC  L  VIN fOSC  Oscillation frequency Table 7 Manufacturer Taiyo Yuden Co., Ltd. Sumida Corporation TDK Corporation FDK Corporation 12 Typical Inductors L Value DC Resistance Rated Current Dimensions (L  W  H) [mm] NR4018T3R3M 3.3 H 0.07  max. 1.23 A max. 4.0  4.0  1.8 NR3012T3R3M 3.3 H 0.1  max. 0.91 A max. 3.0  3.0  1.2 CDRH3D16/HP-3R3 3.3 H 0.085  max. 1.40 A max. 4.0  4.0  1.8 CDRH2D11/HP-3R3 3.3 H 0.173  max. 0.9 A max. 3.2  3.2  1.2 VLF4012AT-3R3M 3.3 H 0.12  max. 1.3 A max. 3.7  3.5  1.2 VLF3010AT-3R3M 3.3 H 0.17  max. 0.87 A max. 2.6  2.8  1.0 MIP3226D3R3M 3.3 H 0.104  max. 1.2 A max. 3.2  2.6  1.0 MIPS2520D3R3M 3.3 H 0.156  max. 1.0 A max. 2.5  2.0  1.0 Part Number STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 2. S-8550 Series Capacitors (CIN, COUT) A ceramic capacitor can be used for the input (CIN) and output (COUT) sides. impedance and averages the input current to improve efficiency. CIN lowers the power supply Select CIN according to the impedance of the power supply to be used. The recommended capacitance is 4.7 F for the S-8550 Series when a general lithium ion rechargeable battery is used. Select as COUT a capacitor with large capacitance and small ESR for smoothing the ripple voltage. The optimum capacitor selection depends on the L value, capacitance value, wiring, and application (output load). Select COUT after sufficient evaluation under actual use conditions. 3. Output voltage setting resistors (RFB1, RFB2), capacitor for phase compensation (CFB) With the S-8550 Series, VOUT can be set to any value by external divider resistors. resistors across the VOUT and VSS pins. VOUT = (RFB1  RFB2) RFB2 Connect the divider Because VFB  0.6 V typ., VOUT can be calculated by this equation.  0.6 Connect divider resistors RFB1 and RFB2 as close to the IC to minimize effects from of noise. If noise does have an effect, adjust the values of RFB1 and RFB2 so that RFB1  RFB2 < 100 k. CFB connected in parallel with RFB1 is a capacitor for phase compensation. By setting the zero point (the phase feedback) by adding capacitor CFB to output voltage setting resistor RFB1 in parallel, the feedback loop gains the phase margin. As a result, the stability can be obtained. In principle, to use the portion how much the phase has feed back by the zero point effectively, define CFB referring to the following equation. CFB  1 2    RFB1  70 kHz This equation is the reference. The followings are explanation regarding the proper setting. To use the portion how much the phase has feed back by the zero point effectively, set RFB1 and CFB so that the zero point goes into the higher frequency than the pole frequency of L and COUT. The following equations are the pole frequency of L and COUT and the zero point frequency by CFB and RFB1. fpole  fzero  1 2 L  COUT 1 2    RFB1  CFB The transient response can be improved by setting the zero point frequency in the range of lower frequency. However, since the gain becomes higher in the range of high frequency, the total phase of feedback loop delays 180 or more by setting the zero point frequency in the significantly lower range. As a result, the gain cannot be 0 dB or lower in the frequency range thus the operation might be unstable. Determine the proper value after the sufficient evaluation under the actual condition. The typical constants by our evaluation are in Table 8. Table 8 Constant for External Parts VOUT(s) [V] 1.1 1.8 3.3 4.0 RFB1 [k] 36 36 36 51 RFB2 [k] 43 18 8 9 CFB [pF] 56 68 120 100 L [H]*1 COUT [F]*1 3.3 3.3 3.3 3.3 10 10 10 10 *1. The recommended parts in Table 5 13 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Standard Circuits 1. SOT-23-5 VIN Current limit circuit FB Error amplifier     Reference voltage VIN IC internal power supply *1 CONT 3.3 H PWM comparator L Triangular wave generation circuit ON/OFF circuit CIN 4.7 F PWM control circuit CFB 68 pF *1 1.0 F UVLO circuit ON/OFF VOUT RFB1 36 k RFB2 18 k COUT 10 F VSS Ground point *1. Parasitic diode Figure 13 2. SNT-8A VIN Current limit circuit FB Error amplifier     Reference voltage VIN CIN 4.7 F IC internal power supply PWM control circuit *1 CONT PWM comparator L Triangular wave generation circuit ON/OFF circuit ON/OFF 3.3 H *1 CFB 68 pF 1.0 F UVLO circuit VSS VOUT RFB1 36 k RFB2 18 k COUT 10 F PVSS Ground point *1. Parasitic diode Figure 14 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using an actual application to set the constants. 14 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Precaution  Mount external capacitors, diodes, and inductors as close as possible to the IC, and make a one-point grounding.  Characteristics ripple voltage and spike noise occur in IC containing switching regulators. Moreover rush current flows at the time of a power supply injection. Because these largely depend on the inductor, the capacitor and impedance of power supply used, fully check them using an actually mounted model.  The 1.0 F capacitance connected between the VIN and VSS pins is a bypass capacitor. It stabilizes the power supply in the IC when application is used with a heavy load, and thus effectively works for stable switching regulator operation. Allocate the bypass capacitor as close to the IC as possible, prioritized over other parts.  Although the IC contains a static electricity protection circuit, static electricity or voltage that exceeds the limit of the protection circuit should not be applied.  The power dissipation of the IC greatly varies depending on the size and material of the board to be connected. Perform sufficient evaluation using an actual application before designing.  ABLIC Inc. assumes no responsibility for the way in which this IC is used on products created using this IC or for the specifications of that product, nor does ABLIC Inc. assume any responsibility for any infringement of patents or copyrights by products that include this IC either in Japan or in other countries. 15 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Characteristics (Typical Data) 1. Example of Major Power Supply Dependence Characteristics (Ta  +25C) 1. 1 Current consumption 1 (ISS1) vs. Input voltage (VIN) 500 1. 2 Current consumption during shutdown (ISSS) vs. Input voltage (VIN) 1.0 0.8 ISSS [μA] ISS1 [μA] 400 300 200 100 0 3.5 4.0 4.5 5.0 5.5 VIN [V] 1. 3 Oscillation frequency (fosc) vs. Input voltage (VIN) 1.38 1.34 1.30 1.26 1.22 1.18 1.14 1.10 1.06 1.02 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN [V] 3.0 1. 5 Power MOS FET on-resistance (RFET) vs. Input voltage (VIN) 0.8 0.6 0.5 Pch 0.4 0.3 Nch 0.2 2.0 2.5 3.0 3.5 4.0 VIN [V] 4.5 5.0 5.5 1. 7 ON/OFF pin input voltage“H” (VSH) vs. Input voltage (VIN) 0.9 3.5 4.0 4.5 5.0 5.5 VIN [V] Soft-start time (tSS) vs. Input voltage (VIN) 1.3 2.5 3.0 0.9 0.8 0.7 3.5 4.0 VIN [V] 4.5 5.0 5.5 1. 6 Power MOS FET leakage current (ILSW) vs. Input voltage (VIN) 0.5 0.4 0.3 0.2 Pch 0.1 0 −0.1 Nch −0.2 −0.3 −0.4 −0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN [V] 1. 8 ON/OFF pin input voltage“L” (VSL) vs. Input voltage (VIN) 0.9 VSL [V] 0.7 0.6 0.5 0.6 0.5 0.4 0.4 0.3 0.3 3.5 4.0 VIN [V] 2.0 1.0 0.7 3.0 3.0 1.2 0.8 2.5 2.5 1.1 0.8 2.0 2.0 ILSW [μA] RFET [] 0.7 1. 4 tSS [ms] 2.5 fOSC [MHz] 2.0 VSH [V] 0.4 0.2 0 16 0.6 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 VIN [V] 4.5 5.0 5.5 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 1. 9 S-8550 Series FB voltage (VFB) vs. Input voltage (VIN) 612 VFB [mV] 608 604 600 596 592 588 2.0 3.0 3.5 4.0 VIN [V] 4.5 5.0 5.5 Example of Major Temperature Characteristics (Ta  40 to +85C) ISS1 [μA] 2. 1 Current consumption 1 (ISS1) vs. Temperature (Ta) 500 VIN = 5.5 V 400 VIN = 3.6 V 300 VIN = 2.0 V 200 2. 2 Current consumption during shutdown (ISSS) vs. Temperature (Ta) 1.0 0.8 ISSS [μA] 2. 2.5 100 −40 −25 0 0 25 Ta [C] 50 75 85 fOSC [MHz] 2. 3 Oscillation frequency (fosc) vs. Temperature (Ta) 1.32 VIN = 5.5 V 1.28 VIN = 3.6 V 1.24 VIN = 2.0 V 1.20 1.16 2. 4 25 Ta [C] −40 −25 25 Ta [C] 50 75 85 0.4 0.3 −40 −25 0 25 Ta [C] 50 75 85 75 85 Soft-start time (tSS) vs. Temperature (Ta) 1.3 1.1 1.0 VIN = 5.5 V VIN = 3.6 V VIN = 2.0 V 0.9 0.7 0 50 −40 −25 0 25 Ta [C] 50 75 85 2. 6 Power MOS FET leakage current (ILSW) vs. Temperature (Ta) 0.5 0.4 0.3 Nch 0.2 VIN = 5.5 V 0.1 0 −0.1 Pch −0.2 VIN = 5.5 V −0.3 −0.4 −0.5 −40 −25 75 85 0 25 50 Ta [C] ILSW [μA] RFET [] 0 0.8 2. 5 Power MOS FET on-resistance (RFET) vs. Temperature (Ta) 0.8 Nch Pch 0.7 VIN = 5.5 V VIN = 5.5 V V IN = 3.6 V VIN = 3.6 V 0.6 VIN = 2.0 V VIN = 2.0 V 0.5 0.2 −40 −25 1.2 1.12 1.08 0.4 0.2 tSS [ms] 0 VIN = 5.5 V VIN = 3.6 V VIN = 2.0 V 0.6 17 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series 2. 7 ON/OFF pin input voltage“H” (VSH) vs. Temperature (Ta) 0.9 2. 8 ON/OFF pin input voltage“L” (VSL) vs. Temperature (Ta) 0.9 VIN = 5.5 V 0.8 VIN = 3.6 V 0.7 VIN = 2.0 V 0.6 0.8 VSL [V] VIN = 3.6 V VIN = 5.5 V VIN = 2.0 V 0.6 0.5 0.4 0.4 0.3 −40 −25 0 25 Ta [C] 50 −40 −25 75 85 2. 9 UVLO detection voltage (VUVLO) vs. Temperature (Ta) 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 −40 −25 75 85 0 25 50 Ta [C] 3. 0.5 0.3 0 25 Ta [C] 50 75 85 2. 10 FB voltage (VFB) vs. Temperature (Ta) 612 VIN = 5.5 V VIN = 3.6 V 608 VIN = 2.0 V 604 VFB [mV] VUVLO [V] VSH [V] 0.7 600 596 592 588 −40 −25 0 25 Ta [C] 50 75 85 Examples of Transient Response Characteristics (Unless otherwise specified, the used parts are ones shown in  External Parts When Measuring Electrical Characteristics.) IL −0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t [ms] 1.5 1.0 0.5 0 −0.5 1.5 1.0 0.5 0 −0.5 Shutdown pin response (VOUT  1.8 V, VIN  3.6 V, VON/OFF  0 V → 3.6 V, Ta  +25C) IOUT = 1 mA VON/OFF VOUT IL −0.2 (2) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t [ms] 0.6 0.4 0.2 0 −0.2 VON/OFF, VOUT [V] VON/OFF, VOUT [V] (1) 4 3 2 1 0 −1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t [ms] 0.6 0.4 0.2 0 −0.2 IOUT = 600 mA 4 3 VIN 2 1 VOUT 0 −1 IL [A] VOUT VIN, VOUT [V] VIN IL 3. 2 (2) IL [A] IOUT = 1 mA −0.2 18 (VOUT  1.8 V, VIN  0 V → 3.6 V, Ta  +25C) IL [A] (1) 4 3 2 1 0 −1 Powering ON IL [A] VIN, VOUT [V] 3. 1 IOUT = 600 mA 4 3 VON/OFF 2 1 VOUT 0 −1 IL −0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t [ms] STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 −0.1 3. 4 VOUT [V] (1) 0 VIN 2.2 2.0 1.8 1.6 1.4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 t [ms] VOUT −0.1 0 4.5 3.5 2.5 1.5 0.5 400 300 200 100 0 −100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 t [ms] Load fluctuations (VOUT  1.8 V, VIN  3.6 V, Ta  +25C) IOUT = 0.1 mA → 100 mA → 0.1 mA IOUT 1.90 1.85 1.80 1.75 1.70 VIN  2.6 V → 3.6 V → 2.6 V VIN [V] VOUT IOUT = 600 mA, IOUT [mA] 2.2 2.0 1.8 1.6 1.4 (2) VOUT −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 t [ms] (2) 400 300 200 100 0 −100 IOUT = 0.1 mA → 300 mA → 0.1 mA IOUT VOUT [V] VOUT [V] VIN VIN  2.6 V → 3.6 V → 2.6 V 4.5 3.5 2.5 1.5 0.5 VOUT [V] IOUT = 1 mA, VIN [V] (1) Power supply fluctuations (VOUT  1.8 V, Ta  +25C) IOUT [mA] 3. 3 S-8550 Series 1.90 1.85 1.80 1.75 1.70 VOUT −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 t [ms] 19 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Reference Data 1. Reference data for external parts Table 9 Element Name Properties of External Parts Product Name Manufacture Characteristics 3.3 H, DCRMAX  0.07 , IMAX  1.23 A Inductor NR4018T3R3M Taiyo Yuden Co., Ltd Input capacitor C3216X7R1E475K TDK Corporation 4.7 F Output capacitor C3216X7R1C106K TDK Corporation 10 F Caution The values of the external parts are based on the materials provided by each manufacturer. However, consider the characteristics of the original materials when using the above products. 2. Output current (IOUT) vs. Efficiency () Characteristics and Output current (IOUT) vs. Output voltage (VOUT) Characteristics VOUT  1.1 V (RFB1  36 k, RFB2  43 k) 2. 2 η [%] Output current (IOUT) vs. Output voltage (VOUT) 1.3 VIN = 5.5 V VIN = 3.6 V 1.2 VIN = 2.0 V 1.1 1.0 0.9 0 1 10 IOUT [mA] 100 1000 VOUT  1.8 V (RFB1  36 k, RFB2  18 k) (1) Output current (IOUT) vs. Efficiency () 100 90 VIN = 2.2 V 80 VIN = 3.6 V 70 VIN = 5.5 V 60 50 40 30 20 10 0 0 1000 1 10 100 IOUT [mA] 20 (2) VOUT [V] η [%] (1) Output current (IOUT) vs. Efficiency () 100 90 VIN = 2.0 V 80 VIN = 3.6 V 70 VIN = 5.5 V 60 50 40 30 20 10 0 0 1000 1 10 100 IOUT [mA] (2) VOUT [V] 2. 1 Output current (IOUT) vs. Output voltage (VOUT) 2.0 VIN = 5.5 V VIN = 3.6 V 1.9 VIN = 2.0 V 1.8 1.7 1.6 0 1 10 IOUT [mA] 100 1000 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 VOUT  3.3 V (RFB1  36 k, RFB2  8 k) 2. 4 Output current (IOUT) vs. Output voltage (VOUT) 3.5 VIN = 5.5 V VIN = 3.7 V 3.4 3.3 3.2 3.1 0 1 10 IOUT [mA] 100 1000 VOUT  4.0 V (RFB1  51 k, RFB2  9 k) η [%] (1) Output current (IOUT) vs. Efficiency () 100 90 VIN = 4.4 V 80 VIN = 5.5 V 70 60 50 40 30 20 10 0 0 1000 1 10 100 IOUT [mA] 3. (2) VOUT [V] η [%] (1) Output current (IOUT) vs. Efficiency () 100 90 VIN = 3.7 V 80 VIN = 5.5 V 70 60 50 40 30 20 10 0 0 1000 1 10 100 IOUT [mA] (2) VOUT [V] 2. 3 S-8550 Series Output current (IOUT) vs. Output voltage (VOUT) 4.2 VIN = 5.5 V VIN = 4.4 V 4.1 4.0 3.9 3.8 0 1 10 IOUT [mA] 100 1000 1 10 IOUT [mA] 100 1000 Output current (IOUT) vs. Ripple voltage (Vr) Characteristics 3. 1 (1) VOUT  1.1 V (RFB1  36 k, RFB2  43 k) VIN = 3.6 V 50 (2) 40 Vr [mV] Vr [mV] 40 VIN = 5.5 V 50 30 20 10 30 20 10 0 0 0 1 10 IOUT [mA] 100 1000 0 21 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series 3. 2 (1) VOUT  1.8 V (RFB1  36 k, RFB2  18 k) VIN = 3.6 V 50 (2) 40 Vr [mV] Vr [mV] 40 30 20 10 1 10 IOUT [mA] 100 1000 0 VIN = 3.6 V 50 (2) Vr [mV] Vr [mV] 30 20 1000 1 10 IOUT [mA] 100 1000 VIN = 5.5 V 50 30 20 0 0 1 10 IOUT [mA] 100 1000 VOUT  4.0 V (RFB1  51 k, RFB2  9 k) VIN = 5.5 V 50 40 Vr [mV] 100 10 0 30 20 10 0 0 22 10 IOUT [mA] 40 10 (1) 1 VOUT  3.3 V (RFB1  36 k, RFB2  8 k) 40 3. 4 20 0 0 (1) 30 10 0 3. 3 VIN = 5.5 V 50 1 10 IOUT [mA] 100 1000 0 STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS Rev.5.0_02 S-8550 Series  Marking Specifications 1. SOT-23-5 Top view 5 (1) to (3): (4): 4 Product code (Refer to Product name vs. Product code.) Lot number (1) (2) (3) (4) 1 2 3 Product name vs. Product code Product Code (1) (2) (3) R 5 A Product Name S-8550AA-M5T1x Remark 1. x: G or U 2. Please select products of environmental code = U for Sn 100%, halogen-free products. 2. SNT-8A 8 Top view 7 6 5 (1): (2) to (4): (5), (6): (7) to (11): (1) (2) (3) (4) Blank Product code (Refer to Product name vs. Product code) Blank Lot number (5) (6) (7) (8) (9) (10) (11) 1 2 3 4 Product name vs. Product code Product name S-8550AA-I8T1U (2) R Product code (3) (4) 5 A 23 2.9±0.2 1.9±0.2 4 5 1 2 +0.1 0.16 -0.06 3 0.95±0.1 0.4±0.1 No. MP005-A-P-SD-1.3 TITLE SOT235-A-PKG Dimensions No. MP005-A-P-SD-1.3 ANGLE UNIT mm ABLIC Inc. 4.0±0.1(10 pitches:40.0±0.2) +0.1 ø1.5 -0 +0.2 ø1.0 -0 2.0±0.05 0.25±0.1 4.0±0.1 1.4±0.2 3.2±0.2 3 2 1 4 5 Feed direction No. MP005-A-C-SD-2.1 TITLE SOT235-A-Carrier Tape No. MP005-A-C-SD-2.1 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. MP005-A-R-SD-1.1 SOT235-A-Reel TITLE No. MP005-A-R-SD-1.1 ANGLE QTY. UNIT mm ABLIC Inc. 3,000 1.97±0.03 8 7 6 5 3 4 +0.05 1 0.5 2 0.08 -0.02 0.48±0.02 0.2±0.05 No. PH008-A-P-SD-2.1 TITLE SNT-8A-A-PKG Dimensions No. PH008-A-P-SD-2.1 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 2.25±0.05 4.0±0.1 2.0±0.05 ø0.5±0.1 0.25±0.05 0.65±0.05 4.0±0.1 4 321 5 6 78 Feed direction No. PH008-A-C-SD-2.0 TITLE SNT-8A-A-Carrier Tape No. PH008-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PH008-A-R-SD-1.0 TITLE SNT-8A-A-Reel No. PH008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 2.01 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) 1. 2. 3. 4. 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) TITLE No. PH008-A-L-SD-4.1 SNT-8A-A -Land Recommendation PH008-A-L-SD-4.1 No. ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com
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