S-93A56AD0A-J8T2GB

Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A The S-93A46A/56A/66A is a high-temperature operation, high speed, low current consumption, 1 Kbit, 2 K-bit and 4 K-bit serial E2PROM with a wide operating voltage range. It is organized as 64-word × 16-bit, 128-word × 16-bit and 256-word × 16-bit in each. It is capable of sequential read, at which time addresses are automatically incremented in 16-bit blocks. The instruction code is compatible with the NM93CS46/56/66. Features • Low current consumption • Wide operating voltage range Standby: 3.0 µA Max. (VCC = 5.5 V) Operating: 1.0 mA Max. (VCC = 5.5 V) 0.6 mA Max. (VCC = 2.7 V) Read: 2.7 to 5.5 V Write: 2.7 to 5.5 V • Sequential read capable • Write disable function when power supply voltage is low • Function to protect against write due to erroneous instruction recognition • CMOS schmitt input (CS, SK) • Endurance: 106 cycles/word* (at +85°C) 1.5 × 105 cycles/word* (at +125°C) * For each address (Word: 16 bits) • Data retention: 15 years (after rewriting 1.5 × 105 cycles/word at +125°C) • High-temperature operation: +125°C Max. • Lead-free products Packages Package name 8-Pin SOP (JEDEC) Package FJ008-A Drawing code Tape FJ008-D Reel FJ008-D Caution Before using the product in medical equipment or automobile equipment including car audios, keyless entries and engine control units, contact to SII is indispensable. Seiko Instruments Inc. 1 CMOS SERIAL E2PROM S-93A46A/56A/66A Pin Assignment 8-Pin SOP (JEDEC) Top view 1 8 Rev.2.1_00 Table 1 Pin No. Pin name Pin description 1 CS Chip select input CS VCC 2 SK Serial clock input 2 7 SK NC 3 DI Serial data input 3 6 DI TEST 4 DO Serial data output 4 5 5 GND Ground DO GND *1 6 TEST Test 7 NC No connection 8 VCC Power supply Figure 1 *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected S-93A46AD0A-J8T2GB (Dynamic burn-in) so long as the absolute maximum rating is not exceeded. S-93A56AD0A-J8T2GB (Dynamic burn-in) S-93A66AD0A-J8T2GB (Dynamic burn-in) Remark Refer to the “Package drawings” for the details. S-93A46AD0A-J8T2GD (Wafer burn-in) S-93A56AD0A-J8T2GD (Wafer burn-in) S-93A66AD0A-J8T2GD (Wafer burn-in) 2 Seiko Instruments Inc. Rev.2.1_00 Block Diagram Memory array Address decoder CMOS SERIAL E2PROM S-93A46A/56A/66A VCC GND Data register DI Mode decode logic CS Clock pulse monitoring circuit Output buffer DO Voltage detector SK Clock generator Figure 2 Instruction Sets 1. S-93A46A Table 2 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 A5 A5 A5 0 1 1 0 5 A4 A4 A4 1 0 1 0 Address 6 A3 A3 A3 x x x x 7 A2 A2 A2 x x x x 8 A1 A1 A1 x x x x 9 A0 A0 A0 x x x x Data 10 to 25 D15 to D0 output*1 D15 to D0 input  D15 to D0 input    *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter Seiko Instruments Inc. 3 CMOS SERIAL E2PROM S-93A46A/56A/66A 2. S-93A56A Table 3 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 x x x 0 1 1 0 5 A6 A6 A6 1 0 1 0 6 A5 A5 A5 x x x x Address 7 A4 A4 A4 x x x x 8 9 10 11 Rev.2.1_00 Data 12 to 27 D15 to D0 output*1 D15 to D0 input  D15 to D0 input    A3 A2 A3 A2 A3 A2 x x x x x x x x A1 A0 A1 A0 A1 A0 x x x x x x x x *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter 3. S-93A66A Table 4 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 A7 A7 A7 0 1 1 0 5 A6 A6 A6 1 0 1 0 6 A5 A5 A5 x x x x Address 7 A4 A4 A4 x x x x 8 9 10 11 Data 12 to 27 D15 to D0 output*1 D15 to D0 input  D15 to D0 input    A3 A2 A3 A2 A3 A2 x x x x x x x x A1 A0 A1 A0 A1 A0 x x x x x x x x *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter 4 Seiko Instruments Inc. Rev.2.1_00 Absolute Maximum Ratings Table 5 CMOS SERIAL E2PROM S-93A46A/56A/66A Item Symbol Ratings Unit Power supply voltage VCC V −0.3 to +7.0 Input voltage VIN V −0.3 to VCC +0.3 Output voltage VOUT V −0.3 to VCC Operating ambient temperature Topr −40 to +125 °C Storage temperature Tstg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 6 Item Power supply voltage High level input voltage Low level input voltage Symbol Condition Min. VCC READ/EWDS 2.7 WRITE/ERASE/ 2.7 WRAL/ERAL/EWEN VIH  0.8 × VCC 0.0 VIL  Typ.     Max. 5.5 5.5 VCC 0.2 × VCC Unit V V V V Pin Capacitance Table 7 Item Input Capacitance Output Capacitance Symbol Condition CIN VIN = 0 V COUT VOUT = 0 V (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Min. Typ. Max. Unit 8 pF   10 pF   Seiko Instruments Inc. 5 CMOS SERIAL E2PROM S-93A46A/56A/66A Endurance Table 8 Rev.2.1_00 Operating temperature Endurance NW −40 to +125°C *1. For each address (Word: 16 bits) Item Symbol Min. 1.5 × 105 Typ.  Max.  Unit cycles/word*1 DC Electrical Characteristics Table 9 Item Current consumption (READ) Symbol ICC1 Condition DO no load VCC = 4.5 to 5.5 V Min. Typ. Max.   VCC = 2.7 to 4.5 V Min. Typ. Max.   Unit mA 1.0 0.6 Table 10 Item Current consumption (WRITE) Symbol ICC2 Condition DO no load VCC = 4.5 to 5.5 V Min. Typ. Max.   VCC = 2.7 to 4.5 V Min. Typ. Max.   Unit mA 2.0 1.5 Table 11 Item Standby current consumption Input leakage current Output leakage current Low level output voltage High level output voltage Write enable latch data hold voltage Symbol ISB ILI ILO VOL VOH Condition CS = GND, DO = Open, Other inputs to VCC or GND VIN = GND to VCC VOUT = GND to VCC IOL = 2.1 mA IOL = 100 µA IOH = −400 µA IOH = −100 µA IOH = −10 µA VDH Only when write disable mode VCC = 4.5 to 5.5 V Min. Typ. Max.      2.4 VCC− 0.3 VCC− 0.2 1.5  0.1 0.1       3.0 2.0 2.0 0.6 0.2     VCC = 2.7 to 4.5 V Min. Typ. Max.       VCC− 0.3 VCC− 0.2 1.5  0.1 0.1       3.0 2.0 2.0  0.2     Unit µA µA µA V V V V V V 6 Seiko Instruments Inc. Rev.2.1_00 AC Electrical Characteristics Table 12 Test Conditions CMOS SERIAL E2PROM S-93A46A/56A/66A Input pulse voltage Output reference voltage Output load 0.1 × VCC to 0.9 × VCC 0.5 × VCC 100 pF Table 13 Parameter Symbol VCC = 4.5 to 5.5 V Min. Typ. Max. VCC = 2.7 to 4.5 V Min. Typ. Max. Unit CS setup time tCSS 0.2 — — 0.4 — — µs CS hold time tCSH 0 — — 0 — — µs CS deselect time tCDS 0.2 — — 0.2 — — µs Data setup time tDS 0.1 — — 0.2 — — µs Data hold time tDH 0.1 — — 0.2 — — µs Output delay time tPD — — 0.6 — — 1.2 µs *1 Clock frequency fSK 0 — 1.0 0 — 0.5 MHz Clock pulse width tSKH, tSKL 0.2 — — 0.5 — — µs Output disable time tHZ1, tHZ2 0 — 0.2 0 — 0.5 µs Output enable time tSV 0 — 0.15 0 — 0.5 µs *1. The clock cycle of the SK clock (frequency: fSK) is 1/fSK µs. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made to equal tSKL(Min.) + tSKH(Min.). Table 14 Parameter Write time Symbol tPR Min.  VCC = 2.7 to 5.5 V Typ. 4.0 Unit Max. 8.0 ms Seiko Instruments Inc. 7 CMOS SERIAL E2PROM S-93A46A/56A/66A Rev.2.1_00 tCSS CS tSKH SK tDS DI Hi-Z *1 1/fSK *2 tCDS tSKL tCSH tDH tDS tDH Valid data Valid data tPD tSV tPD Hi-Z DO (READ) DO Hi-Z tHZ2 tHZ1 Hi-Z (VERIFY) *1. Indicates high impedance. *2. 1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made to equal tSKL(Min.) + tSKH(Min.). Figure 3 Timing Chart 8 Seiko Instruments Inc. Rev.2.1_00 Operation CMOS SERIAL E2PROM S-93A46A/56A/66A All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An instruction set is input in the order of start bit, instruction, address, and data. Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS. While a low level is being input to CS, the S-93A66A is in standby mode, so the SK and DI inputs are invalid and no instructions are allowed. Start Bit A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit is not recognized even if the SK pulse is input as long as the DI pin is low. 1. Dummy Clock SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial memory operation. For example, when the CPU instruction set is 16 bits, the number of instruction set clocks can be adjusted by inserting the 7-bit dummy clock in S-93A46A and the 5-bit dummy clock in S-93A56A/66A. 2. Start Bit input Failure • When the output status of the DO pin is high during the verify period after a write operation, if a high level is input to the DI pin at the rising edge of SK, the S-93A66A recognizes that a start bit has been input. To prevent this failure, input a low level to the DI pin during the verify operation period (Refer to “4.1 Verify Operation”). • When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the data output from the CPU and the serial memory collide may be generated, preventing successful input of the start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”. Seiko Instruments Inc. 9 CMOS SERIAL E2PROM S-93A46A/56A/66A 3. Reading (READ) Rev.2.1_00 The READ instruction reads data from a specified address. After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the last input address (A0) has been latched, the output status of the DO pin changes from high impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of SK. 3.1 Sequential Read After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically increments the address, and causes the 16-bit data at the next address to be output sequentially. The above method makes it possible to read the data in the whole memory space. The A1 A0 = 1 1 1) rolls over to the top address (An A1 A0 = 0 0 0). last address (An CS SK DI DO 1 2 3 4 5 6 7 8 9 10 11 12 22 23 24 25 26 27 38 39 40 41 42 43 1 0 A5 A4 A3 A2 A1 A0 Hi-Z 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13 Hi-Z ADRINC ADRINC Figure 4 Read Timing (S-93A46A) CS SK DI DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 40 41 42 43 44 45 1 0 A6 A5 A4 A3 A2 A1 A0 Hi-Z x:S-93A56A A7:S-93A66A 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13 Hi-Z ADRINC ADRINC Figure 5 Read Timing (S-93A56A/66A) 10 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 4. Writing (WRITE, ERASE, WRAL, ERAL) A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and chip erase (ERAL). A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write period, so do not input an instruction. Input an instruction while the output status of the DO pin is high or high impedance (Hi-Z). A write operation is valid only in program enable mode (refer to “5. Write Enable (EWEN) and Write Disable (EWDS)”). 4.1 Verify Operation A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4 ms), so if the completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to confirm the status of a write operation is called a verify operation. (1) Operation After the write operation has started (CS = low), the status of the write operation can be verified by confirming the output status of the DO pin by inputting a high level to CS again. This sequence is called a verify operation, and the period that a high level is input to the CS pin after the write operation has started is called the verify operation period. The relationship between the output status of the DO pin and the write operation during the verify operation period is as follows. • DO pin = low: Writing in progress (busy) • DO pin = high: Writing completed (ready) (2) Operation Example There are two methods to perform a verify operation: Waiting for a change in the output status of the DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing it again to verify the output status of the DO pin. The latter method allows the CPU to perform other processing during the wait period, allowing an efficient system to be designed. Caution 1. Input a low level to the DI pin during a verify operation. 2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is high, the S-93A66A latches the instruction assuming that a start bit has been input. In this case, note that the DO pin immediately enters a high-impedance (Hi-Z) state. Seiko Instruments Inc. 11 CMOS SERIAL E2PROM S-93A46A/56A/66A 4.2 Writing Data (WRITE) Rev.2.1_00 To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address, and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to set the data to 1 before writing. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS CS SK DI DO 1 2 0 1 3 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 D15 25 D0 Verify Standby Hi-Z tSV busy ready tHZ1 tPR Hi-Z Figure 6 Data Write Timing (S-93A46A) tCDS CS SK DI DO 1 2 0 3 1 Hi-Z 4 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 D15 27 D0 Verify Standby x:S-93A56A A7:S-93A66 tSV busy ready tHZ1 tPR Hi-Z Figure 7 Data Write Timing (S-93A56A/66A) 12 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 4.3 Erasing Data (ERASE) To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input the ERASE instruction and address following the start bit. There is no need to input data. The data erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS Standby CS SK DI DO 1 2 1 1 3 4 A5 Hi-Z 5 A4 6 A3 7 A2 8 A1 9 A0 tSV Verify busy tHZ1 ready tPR Hi-Z Figure 8 Data Erase Timing (S-93A46A) tCDS CS SK DI DO 1 2 1 1 Hi-Z 3 4 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 tSV Verify Standby x:S-93A56A A7:S-93A66A busy tHZ1 ready tPR Hi-Z Figure 9 Data Erase Timing (S-93A56A/66A) Seiko Instruments Inc. 13 CMOS SERIAL E2PROM S-93A46A/56A/66A 4.4 Writing to Chip (WRAL) Rev.2.1_00 To write the same 16-bit data to the entire memory address space, change CS to high, and then input the WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write operation starts when CS goes low. There is no need to set the data to 1 before writing. When the clocks more than the specified number been input, the clock pulse monitoring circuit cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS CS SK DI DO 1 2 0 0 3 0 Hi-Z 4 1 4Xs 5 6 7 8 9 10 D15 25 D0 Verify Standby tSV busy ready tHZ1 tPR Hi-Z Figure 10 Chip Write Timing (S-93A46A) tCDS CS SK DI DO 1 2 0 0 3 0 Hi-Z 4 1 6Xs 5 6 7 8 9 10 11 12 D15 27 D0 Verify Standby tSV busy ready tHZ1 tPR Hi-Z Figure 11 Chip Write Timing (S-93A56A/66A) 14 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 4.5 Erasing Chip (ERAL) To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to input data. The chips erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. CS SK DI DO tPR 1 2 3 4 5 6 7 8 9 Standby tCDS Verify 0 0 1 0 4Xs tSV Busy Ready tHZ1 Hi-Z Figure 12 Chip Erase Timing (S-93A46A) CS SK DI DO 1 2 3 4 5 6 7 8 9 10 tCDS 11 Verify Standby 0 0 1 0 6Xs tSV B usy tPR Ready tHZ1 Hi-Z Figure 13 Chip Erase Timing (S-93A56A/66A) Seiko Instruments Inc. 15 CMOS SERIAL E2PROM S-93A46A/56A/66A 5. Write Enable (EWEN) and Write Disable (EWDS) Rev.2.1_00 The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is enabled is called the program enable mode. The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is disabled is called the program disable mode. After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address (optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been input. CS SK DI 1 0 2 3 0 4 5 6 7 8 9 Standby 11=EWEN 00=EWDS 4Xs Figure 14 Write Enable/Disable Timing (S-93A46A) CS SK DI 1 2 0 3 0 4 5 6 7 8 9 10 11 Standby 11=EWEN 00=EWDS 6Xs Figure 15 Write Enable/Disable Timing (S-93A56A/66A) (1) Recommendation for write operation disable instruction It is recommended to implement a design that prevents an incorrect write operation when a write instruction is erroneously recognized by executing the write operation disable instruction when executing instructions other than write instruction, and immediately after power-on and before power off. 16 Seiko Instruments Inc. Rev.2.1_00 Write Disable Function when Power Supply Voltage is Low CMOS SERIAL E2PROM S-93A46A/56A/66A The S-93A46A/56A/66A provides a built-in detector to detect a low power supply voltage and disable writing. When the power supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of about 0.3 V (Refer to Figure 16). Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed. When the power supply voltage drops during a write operation, the data being written to an address at that time is not guaranteed. Hysteresis About 0.3 V Release voltage (+VDET) 2.05 V Typ. Power supply voltage Detection voltage (−VDET) 1.75 V Typ. Write instruction cancelled Write disable state (EWDS) automatically set Figure 16 Operation when Power Supply Voltage is Low Seiko Instruments Inc. 17 CMOS SERIAL E2PROM S-93A46A/56A/66A Rev.2.1_00 Function to Protect Against Write due to Erroneous Instruction Recognition The S-93A46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse whose count other than the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected. Erroneous Recognition of Program Disable Instruction (EWDS) as Erase Instruction (ERASE) Example of S-93A56A/66A CS 1 SK DI Input EWDS instruction Erroneous recognition as ERASE instruction due to noise pulse 1 0 Noise pulse 2 3 4 5 6 7 8 9 10 11 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 1 1 10 In products that do not incorporate a clock pulse monitoring circuit, FFFF is mistakenly written to address 00h. However the S-93A56A/66A detects the overcount and cancels the instruction without performing a write operation. Figure 17 Example of Clock Pulse Monitoring Circuit Operation 18 Seiko Instruments Inc. Rev.2.1_00 3-Wire Interface (Direct Connection between DI and DO) CMOS SERIAL E2PROM S-93A46A/56A/66A There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin. When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins of the S-93A46A/56A/66A via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input to the DI pin (Refer to “Figure 18 Connection of 3-Wire Interface”). CPU S-93A46A/56A/66A SIO DI DO R: 10 kΩ to 100 kΩ Figure 18 Connection of 3-Wire Interface I/O Pins 1. Connection of Input Pins All the input pins of the S-93A46A/56A/66A employ a CMOS structure, so design the equipment so that high impedance will not be input while the S-93A46A/56A/66A is operating. Especially, deselect the CS input (a low level) when turning on/off power and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ pull-down resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin. 2. Input and Output Pin Equivalent Circuits The following shows the equivalent circuits of input pins of the S-93A46A/56A/66A. None of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating status. Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected from the internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected. Seiko Instruments Inc. 19 CMOS SERIAL E2PROM S-93A46A/56A/66A 2.1 Input Pin Rev.2.1_00 CS Figure 19 CS Pin SK Figure 20 SK Pin DI Figure 21 DI Pin 20 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A TEST Figure 22 TEST Pin 2.2 Output Pin Vcc DO Figure 23 DO Pin 3. Input Pin Noise Elimination Time The S-93A46A/56A/66A includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated. Note, therefore, that noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds VIH/VIL. Precaution • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. Seiko Instruments Inc. 21 CMOS SERIAL E2PROM S-93A46A/56A/66A Characteristics 1. DC Characteristics 1.1 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC=5.5 V fSK=1 MHz DATA=0101 0.4 ICC1 (mA) 0.2 Rev.2.1_00 1.2 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC=3.3 V fSK=500 kHz DATA=0101 0.4 ICC1 (mA) 0.2 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 1.3 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC=2.7 V fSK=500 kHz DATA=0101 0.4 ICC1 (mA) 0.2 1.4 Current consumption (READ) ICC1 vs. power supply voltage VCC Ta=25°C fSK=1 MHz, 500 kHz DATA=0101 0.4 ICC1 (mA) 0.2 500 kHz 2 345 VCC (V) 6 7 1 MHz 0 –40 0 Ta (°C) 125 0 1.5 Current consumption (READ) ICC1 vs. power supply voltage VCC Ta=25°C fSK=100 kHz, 10 kHz DATA=0101 0.4 ICC1 (mA) 0.2 100 kHz 10 kHz 2345 VCC (V) 6 7 1.6 Current consumption (READ) ICC1 vs. Clock frequency fSK VCC=5.5 V Ta=25 (°C) 0.4 ICC1 (mA) 0.2 0 0 1 k 100 k 1 M10 M fSK (Hz) 22 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 1.8 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC=3.3 V 1.0 ICC2 (mA) 1.7 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC=5.5 V 1.0 ICC2 (mA) 0.5 0.5 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 1.9 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC=2.7 V 1.0 ICC2 (mA) 0.5 1.10 Current consumption (WRITE) ICC2 vs. power supply voltage VCC Ta=25°C 1.0 ICC2 (mA) 0.5 0 –40 0 Ta (°C) 125 0 2345 VCC (V) 67 1.11 Current consumption in standby mode ISB vs. ambient temperature Ta VCC=5.5 V CS=GND 1.0 ISB (µA) 0.5 1.12 Current consumption in standby mode ISB vs. power supply voltage VCC Ta=25°C CS=GND 1.0 ISB (µA) 0.5 0 –40 0 Ta (°C) 125 0 2 345 VCC (V) 6 7 Seiko Instruments Inc. 23 CMOS SERIAL E2PROM S-93A46A/56A/66A 1.13 Input leakage current ILI vs. ambient temperature Ta VCC=5.5 V CS, SK, DI, TEST=0 V 1.0 ILI (µA) 0.5 ILI (µA) 0.5 Rev.2.1_00 1.14 Input leakage current ILI vs. ambient temperature Ta VCC=5.5 V CS, SK, DI, TEST=5.5 V 1.0 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 1.15 Output leakage current ILO vs. ambient temperature Ta VCC=5.5 V DO=0 V 1.0 ILO (µA) 0.5 1.16 Output leakage current ILO vs. ambient temperature Ta VCC=5.5 V DO=5.5 V 1.0 ILO (µA) 0.5 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 1.17 High-level output voltage VOH vs. ambient temperature Ta VCC=4.5 V IOH=–400 µA 1.18 High-level output voltage VOH vs. ambient temperature Ta VCC=2.7 V IOH=–100 µA 4.6 VOH (V) 4.4 4.2 2.8 VOH (V) 2.6 2.4 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 24 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 1.20 Low-level output voltage VOL vs. ambient temperature Ta VCC=4.5 V IOL=2.1 mA 1.19 High-level output voltage VOH vs. ambient temperature Ta VCC=2.7 V IOH=–10 µA 2.8 VOH (V) 2.6 2.4 0.3 VOL (V) 0.2 0.1 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 1.21 Low-level output voltage VOL vs. ambient temperature Ta VCC=2.7 V IOL=100 µA 1.22 High-level output current IOH vs. ambient temperature Ta VCC=4.5 V VOH=2.4 V –10 IOH (mA) –20 0.03 VOL (V) 0.02 0.01 0 –40 0 Ta (°C) 125 –40 0 Ta (°C) 125 1.23 High-level output current IOH vs. ambient temperature Ta VCC=2.7 V VOH=2.4 V –1 IOH (mA) –2 1.24 High-level output current IOH vs. ambient temperature Ta VCC=2.7 V VOH=2.5 V –1 IOH (mA) –2 –40 0 Ta (°C) 125 –40 0 Ta (°C) 125 Seiko Instruments Inc. 25 CMOS SERIAL E2PROM S-93A46A/56A/66A 1.25 Low-level output current IOL vs. ambient temperature Ta VCC=4.5 V VOL=0.6 V 20 IOL (mA) 10 1 0 –40 0 0 –40 0 IOL (mA) 3 2 Rev.2.1_00 1.26 Low-level output current IOL vs. ambient temperature Ta VCC=2.7 V VOL=0.2 V Ta (°C) 125 Ta (°C) 125 1.27 High-level input voltage VIH vs. power supply voltage VCC Ta=25°C CS, SK 2 VIH (V) 1 1.28 High-level input voltage VIH vs. ambient temperature Ta 2 VIH (V) 1 VCC=5.5 V CS, SK 0 2 345 VCC (V) 6 7 0 –40 0 Ta (°C) 125 1.29 High-level input voltage VIH vs. power supply voltage VCC Ta=25°C DI 2 VIH (V) 1 1.30 High-level input voltage VIH vs. ambient temperature Ta 2 VIH (V) 1 VCC=5.5 V DI 0 2 345 VCC (V) 6 7 0 –40 0 Ta (°C) 125 26 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 1.32 Low-level input voltage VIL vs. ambient temperature Ta 1.31 Low-level input voltage VIL vs. power supply voltage VCC Ta=25°C CS, SK 2 VIL (V) 1 2 VIL (V) 1 VCC=5.5 V CS, SK 0 2345 VCC (V) 67 0 –40 0 Ta (°C) 125 1.33 Low-level input voltage VIL vs. power supply voltage VCC Ta=25°C DI 2 VIL (V) 1 1.34 Low-level input voltage VIL vs. ambient temperature Ta 2 VIL (V) 1 VCC=5.5 V DI 0 2345 VCC (V) 67 0 –40 0 Ta (°C) 125 1.35 Low supply voltage detection voltage −VDET vs. ambient temperature Ta 1.36 Low supply voltage release voltage +VDET vs. ambient temperature Ta 2.0 –VDET (V) 1.0 +VDET (V) 2.0 1.0 0 –40 0 0 Ta (°C) 125 –40 0 Ta (°C) 125 Seiko Instruments Inc. 27 CMOS SERIAL E2PROM S-93A46A/56A/66A 2. AC Characteristics 2.1 Maximum operating frequency fmax. vs. power supply voltage VCC Ta=25°C 10 M fmax. 1 M (Hz) 100 k 10 k 2345 VCC (V) 67 0 2345 VCC (V) 6 7 tPR (ms) 4.0 Rev.2.1_00 2.2 Write time tPR vs. power supply voltage VCC Ta=25°C 2.0 2.3 Write time tPR vs. ambient temperature Ta VCC=5.5 V 4.0 tPR (ms) 2.0 2.4 Write time tPR vs. ambient temperature Ta VCC=3.3 V 4.0 tPR (ms) 2.0 0 –40 0 Ta (°C) 125 0 –40 0 Ta (°C) 125 2.5 Write time tPR vs. ambient temperature Ta VCC=2.7 V 4.0 tPR (ms) 2.0 2.6 Data output delay time tPD vs. ambient temperature Ta VCC=4.5 V 0.3 tPD (ns) 0.2 0.1 0 –40 0 0 –40 0 Ta (°C) 125 Ta (°C) 125 28 Seiko Instruments Inc. Rev.2.1_00 CMOS SERIAL E2PROM S-93A46A/56A/66A 2.8 Data output delay time tPD vs. ambient temperature Ta VCC=2.7 V 1.5 tPD (ns) 1.0 0.5 0 –40 0 2.7 Data output delay time tPD vs. ambient temperature Ta VCC=3.3 V 0.6 tPD (ns) 0.4 0.2 0 –40 0 Ta (°C) 125 Ta (°C) 125 Seiko Instruments Inc. 29 CMOS SERIAL E2PROM S-93A46A/56A/66A Product Name Structure S-93AxxA D 0 A − J8T2 G x Burn-in specification B: Dynamic burn-in D: Wafer burn-in Package code and IC packing specifications J8T2: 8-Pin SOP (JEDEC), Tape Operation temperature A: −40 ∼ +125°C Fixed Pin assignment Product name S-93A46A: S-93A56A: S-93A66A: 1 K-bit 2 K-bit 4 K-bit Rev.2.1_00 30 Seiko Instruments Inc. 5.02±0.2 8 5 1 4 0.20±0.05 1.27 0.4±0.05 No. FJ008-A-P-SD-2.1 TITLE No. SCALE UNIT SOP8J-D-PKG Dimensions FJ008-A-P-SD-2.1 mm Seiko Instruments Inc. 2.0±0.05 ø1.55±0.05 4.0±0.1(10 pitches:40.0±0.2) 0.3±0.05 ø2.0±0.05 5°max. 8.0±0.1 2.1±0.1 6.7±0.1 1 8 4 5 Feed direction No. FJ008-D-C-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Carrier Tape FJ008-D-C-SD-1.1 mm Seiko Instruments Inc. 60° 2±0.5 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 13.5±0.5 No. FJ008-D-R-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Reel FJ008-D-R-SD-1.1 QTY. mm 2,000 Seiko Instruments Inc. • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.