N
S-93C76A
3-WIRE SERIAL E2PROM
DE
SI
G
www.ablicinc.com
Rev.7.0_03
© ABLIC Inc., 2001-2015
The S-93C76A is a high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S93C76A has the capacity of 8 K-bit, and the oganization is 512-word 16 bit. It is capable of sequential read, at which time
addresses are automatically incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Read
1.8 V to 5.5 V
Write
2.7 V to 5.5 V
2.0 MHz (VCC = 4.5 V to 5.5 V)
10.0 ms max.
D
FO
R
Operating frequency:
Write time:
Sequential read capable
Write protect function during the low power supply voltage
Endurance:
106 cycles / word*1 (Ta = 85C)
Data retention:
100 years (Ta = 25C)
20 years (Ta = 85C)
Memory capacity:
8 K-bit
Initial delivery state:
FFFFh
Operation temperature range:
Ta = 40°C to 85C
Lead-free, Sn 100%, halogen-free*2
NE
Operating voltage range:
W
Features
DE
*1. For each address (Word: 16-bit)
EN
*2. Refer to “ Product Name Structure” for details.
Packages
OM
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC
Inc. is indispensable.
NO
T
RE
C
Caution
M
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
1
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
8-Pin SOP (JEDEC)
Table 1
8-Pin SOP (JEDEC)
Top view
Pin No.
8
2
7
3
6
4
5
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
NE
Figure 1
R
S-93C76ADFJ-TB-x
8-Pin TSSOP
FO
2.
Description
W
1
Symbol
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SI
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1.
N
Pin Configurations
8-Pin TSSOP
Top view
Remark 1.
D
OM
M
S-93C76AFT-TB-x
DE
8
7
6
5
Figure 2
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
EN
1
2
3
4
Table 2
Refer to the “package drawings” for the details.
x: G or U
Please select products of environmental code = U for Sn 100%, halogen-free products.
NO
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2.
3.
2
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
TMSOP-8
Table 3
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TMSOP-8
Top view
1
2
3
4
N
3.
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
8
7
6
5
W
Figure 3
NO
T
RE
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OM
M
EN
DE
D
FO
Remark Refer to the “package drawings” for the details.
R
NE
S-93C76AFM-TF-U
3
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
Address
Memory array
decoder
GND
Output buffer
Mode decode logic
CS
SK
FO
R
Clock generator
NE
DI
NO
T
RE
C
OM
M
EN
DE
D
Figure 4
4
VCC
W
Data register
DE
SI
G
N
Block Diagram
DO
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
Instruction Sets
DE
SI
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Table 4
NE
W
Instruction
Start Bit Operation Code
Address
Data
SK input clock
1
2
3
4
5
6
7
8
9 10 11 12 13
14 to 29
*1
READ (Read data)
1
1
0
x A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output
*2
WRITE (Write data)
1
0
1
x A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data) *2
1
1
1
x A8 A7 A6 A5 A4 A3 A2 A1 A0
WRAL (Write all) *2
1
0
0
0
1
x
x
x
x
x
x
x
x
D15 to D0 Input
ERAL (Erase all) *2
1
0
0
1
0
x
x
x
x
x
x
x
x
EWEN (Write enable) *2
1
0
0
1
1
x
x
x
x
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
x
x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
*2. WRITE, ERASE, WRAL, ERAL, and EWEN are guaranteed only at VCC 2.7 V.
NO
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EN
DE
D
FO
R
Remark x: Don’t care
5
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
Absolute Maximum Ratings
DE
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Table 5
Recommended Operating Conditions
Table 6
VCC
High level input voltage
VIH
Low level input voltage
VIL
Symbol
M
Item
Input Capacitance
Output Capacitance
OM
CIN
COUT
RE
C
Endurance
Item
DE
EN
Pin Capacitance
READ, EWDS
WRITE, ERASE,
WRAL, ERAL, EWEN
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
D
Power supply voltage
Conditions
R
Symbol
FO
Item
Symbol
NE
W
Item
Symbol
Ratings
Unit
Power supply voltage
VCC
0.3 to 7.0
V
Input voltage
VIN
0.3 to VCC 0.3
V
Output voltage
VOUT
0.3 to VCC
V
Operation ambient temperature Topr
40 to 105
C
Storage temperature
Tstg
65 to 150
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Ta = 40C to 85C
Min.
Max.
1.8
5.5
Unit
V
2.7
5.5
V
2.0
0.8 VCC
0.8 VCC
0.0
0.0
0.0
VCC
VCC
VCC
0.8
0.2 VCC
0.15 VCC
V
V
V
V
V
V
Table 7
Conditions
VIN = 0 V
VOUT = 0 V
(Ta = 25C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
8
pF
10
pF
Table 8
Operation Ambient Temperature
6
Max.
Unit
cycles / word*1
10
Min.
Max.
Unit
100
20
year
year
T
Endurance
NW
Ta = 40°C to 85C
*1. For each address (Word: 16-bit)
Min.
NO
Data Retention
Item
Data retention
6
Table 9
Symbol
Operation Ambient Temperature
Ta = 25°C
Ta = 40°C to 85°C
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
DC Electrical Characteristics
DE
SI
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Table 10
Ta = 40C to 85C
Symbol Conditions VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.8 V to 2.5 V Unit
Min.
Max.
Min.
Max.
Min.
Max.
Item
Current consumption
(READ)
ICC1
DO no load
0.8
Table 11
ICC2
DO no load
2.0
Table 12
ILI
ILO
VOL
VOH
Data hold voltage
of write enable latch
VDH
Unit
1.5
mA
R
Only program disable mode
1.5
2.0
A
1.0
1.0
1.0
1.0
0.4
0.1
0.1
VCC0.3
VCC0.2 VCC0.2
1.0
1.0
0.1
A
A
V
V
V
V
V
V
2.0
1.5
2.0
1.5
NO
T
RE
C
OM
M
High level output
voltage
CS = GND, DO = Open,
Other inputs to VCC or GND
VIN = GND to VCC
VOUT = GND to VCC
IOL = 2.1 mA
IOL = 100 A
IOH = 400 A
2.4
IOH = 100 A
VCC0.3
IOH = 10 A
VCC0.2
D
ISB
DE
Standby current
consumption
Input leakage current
Output leakage current
Low level output
voltage
Conditions
mA
Ta = 40C to 85C
VCC =
VCC =
VCC =
Unit
4.5 V to 5.5 V 2.5 V to 4.5 V 1.8 V to 2.5 V
Min.
Max.
Min.
Max. Min. Max.
FO
Symbol
EN
Item
W
Current consumption
(WRITE)
0.4
Ta = 40C to 85C
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
Min.
Max.
Min.
Max.
Symbol Conditions
NE
Item
0.5
7
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
Measurement Conditions
0.1 VCC to 0.9 VCC
Input pulse voltage
0.5 VCC
Output reference voltage
Output load
100 pF
Table 14
W
NE
s
s
s
s
s
s
MHz
s
s
s
s
DE
NO
T
M
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C
Write time
Table 15
Symbol
OM
Item
8
Unit
The clock cycle of the SK clock (frequency: fSK) is 1 / fSK s. This clock cycle is determined by a combination
of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 /
fSK) cannot be made equal to tSKL (min.) tSKH (min.).
EN
*1.
tCSS
tCSH
tCDS
tDS
tDH
tPD
fSK
tSKL
tSKH
tHZ1, tHZ2
tSV
R
CS setup time
CS hold time
CS deselect time
Data setup time
Data hold time
Output delay time
Clock frequency*1
SK clock time “L” *1
SK clock time “H” *1
Output disable time
Output enable time
Ta = 40C to 85C
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.8 V to 2.5 V
Min.
Max.
Min.
Max.
Min.
Max.
0.2
—
0.4
—
1.0
—
0
—
0
—
0
—
0.2
—
0.2
—
0.4
—
0.1
—
0.2
—
0.4
—
0.1
—
0.2
—
0.4
—
—
0.4
—
0.8
—
2.0
0
2.0
0
0.5
0
0.25
0.1
—
0.5
—
1.0
—
0.1
—
0.5
—
1.0
—
0
0.15
0
0.5
0
1.0
0
0.15
0
0.5
0
1.0
FO
Symbol
D
Item
DE
SI
G
Table 13
N
AC Electrical Characteristics
tPR
Min.
Ta = 40C to 85C
VCC = 2.7 V to 5.5 V
Typ.
4.0
Unit
Max.
10.0
ms
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
*2
CS
tSKH
tCSH
tSKL
SK
tDS
DI
tDH
tDS
Valid data
tDH
Valid data
tPD
tPD
DO
tSV
(READ)
DO
*1
NE
High-Z
tHZ2
High-Z
High-Z
tHZ1
High-Z
R
(VERIFY)
Indicates high impedance.
1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics,
so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot be made equal
to tSKL (min.) tSKH (min.).
Timing Chart
NO
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EN
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D
Figure 5
FO
*1.
*2.
DE
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tCDS
W
1 / fSK
tCSS
9
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
Initial Delivery State
DE
SI
G
Initial delivery state of all addresses is “FFFFh”.
Operation
1.
NE
W
All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction
is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at
the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized
even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input
is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the
internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory
IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the
period of tCDS in between instructions.
“L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.
Reading (READ)
D
FO
R
The READ instruction is used to read the data at a specified address. When this instruction is executed, the
address A0 is input at the rising edge of SK and the DO pin, which has been in a high-impedance (High-Z) state,
outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK.
If SK is output after the 16-bit data of the specified address has been output, the address is automatically
incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at
“H”, the data of the entire memory space can be read. When the address is incremented from the last address (A8
… A1 A0 = 1 … 1 1), it returns to the first address (A8 … A1 A0 = 0 … 0 0).
1
2
1
3
0
4
5
6
7
9 10 11 12 13 14 15 16
OM
RE
C
T
NO
10
26 27 28 29 30 31 32
42 43 44 45 46 47 48
X A8 A7 A6 A5 A4 A3 A2 A1 A0
High-Z
DO
8
EN
DI
1
M
SK
DE
CS
0 D15 D14 D13
Figure 6
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
A8A7A6A5A4A3A2A1A0+1
A8A7A6A5A4A3A2A1A0+2
Read Timing
High-Z
3-WIRE SERIAL E2PROM
S-93C76A
2.
N
Rev.7.0_03
Writing (WRITE, ERASE, WRAL, ERAL)
Writing data (WRITE)
This instruction is used to write 16-bit data to a specified address.
After making CS “H”, input a start bit, the WRITE instruction, an address, and 16-bit data. If data of more than
16 bits is input, the written data is sequentially shifted at each clock, and the 16 bits input last are the valid
data. The write operation is started when CS is made “L”. It is not necessary to set data to “1” before it is
written.
D
FO
2. 1
R
NE
W
DE
SI
G
Write instructions (WRITE, ERASE, WRAL, and ERAL) are used to start writing data to the non-volatile memory by
making CS “L” after the specified number of clocks has been input.
The write operation is completed within the write time tPR (10 ms) no matter which write instruction is used. The
typical write time is less than half 10 ms. If the end of the write operation is known, therefore, the write cycle can
be minimized. To ascertain the end of a write operation, make CS “L” to start the write operation and then make
CS “H” again to check the status of the DO output pin. This series of operations is called a verify operation.
If DO outputs “L” during the verify operation period in which CS is “H”, it indicates that a write operation is in
progress. If DO outputs “H”, it indicates that the write operation is finished. The verify operation can be executed
as many times as required. This operation can be executed in two ways. One is detecting the positive transition
of DO output from “L” to “H” while holding CS at “H”. The other is detecting the positive transition of DO output
from “L” to “H” by making CS “H” once and checking DO output, and then returning CS to “L”.
During the write period, SK and DI are invalid. Do not input any instructions during this period. Input an
instruction while the DO pin is outputting “H” or is in a high-impedance state. Even while the DO pin is outputing
“H”, DO immediately goes into a high-impedance (High-Z) state if “H” of DI (start bit) is input at the rising edge of
SK.
Keep DI “L” during the verify operation period.
CS
1
DI
2
0
3
1
4
5
X
A8
6
7
A7
A6
9
10
11
12
A5
A4
A3
A2
A1
14
29
A0 D15
D0
tSV
EN
busy
tHZ1
ready
tPR
High-Z
Data Write Timing
M
Figure 7
OM
Erasing data (ERASE)
This instruction is used to erase specified 16-bit data. All the 16 bits of the data are “1”. After making CS
“H”, input a start bit, the ERASE instruction, and an address. It is not necessary to input data. The data
erase operation is started when CS is made “L”.
RE
C
2. 2
13
High-Z
DO
Standby
Verify
8
DE
SK
tCDS
tCDS
CS
SK
1
DI
NO
T
DO
2
1
Verify
3
1
4
5
6
X
A8
A7
7
8
9
10
11
12
13
A6
A5
A4
A3
A2
A1
A0
tSV
High-Z
busy
tPR
Figure 8
Standby
tHZ1
ready
High-Z
Data Erase Timing
11
3-WIRE SERIAL E2PROM
S-93C76A
N
Writing to chip (WRAL)
This instruction is used to write the same 16-bit data to the entire address space of the memory.
After making CS “H”, input a start bit, the WRAL instruction, an address, and 16-bit data. Any address may be
input. If data of more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16-bit
data input last is the valid data. The write operation is started when CS is made “L”. It is not necessary to
set the data to “1” before it is written.
DE
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2. 3
Rev.7.0_03
tCDS
CS
Verify
DI
2
0
3
0
4
0
5
6
7
8
9
10
13
14
D15
8Xs
High-Z
Figure 9
29
D0
tSV
busy
tHZ1
ready
tPR
High-Z
Chip Write Timing
FO
R
Erasing chip (ERAL)
This instruction is used to erase the data of the entire address space of the memory.
All the data is “1”. After making CS “H”, input a start bit, the ERAL instruction, and an address. Any address
may be input. It is not necessary to input data. The chip erase operation is started when CS is made “L”.
1
DI
2
0
3
0
4
1
5
0
6
7
8
9
DE
SK
D
CS
High-Z
EN
DO
NO
T
RE
C
OM
M
Figure 10
12
12
1
DO
2. 4
11
W
1
NE
SK
Standby
10
tCDS
Verify
11
12
Standby
13
8Xs
tSV
busy
tPR
Chip Erase Timing
tHZ1
ready
High-Z
3-WIRE SERIAL E2PROM
S-93C76A
3.
N
Rev.7.0_03
Write enable (EWEN) and write disable (EWDS)
DE
SI
G
The EWEN instruction is used to enable a write operation. The status in which a write operation is enabled is
called the program-enabled mode.
The EWDS instruction is used to disable a write operation. The status in which a write operation is disabled is
called the program-disabled mode.
The write operation is disabled upon power application and detection of a low supply voltage. To prevent an
unexpected write operation due to external noise or a CPU malfunctions, it should be kept in write disable mode
except when performing write operations, after power-on and before shutdown.
Standby
CS
DI
2
3
0
4
5
6
7
8
9
10
11
0
8Xs
11 = EWEN
00 = EWDS
13
Write Enable / Disable Timing
R
Figure 11
12
W
1
NE
SK
FO
Start Bit
NO
T
RE
C
OM
M
EN
DE
D
A start bit is recognized by latching the high level of DI at the rising edge of SK after changing CS to high (start bit
recognition). A write operation begins by inputting the write instruction and setting CS to low. Subsequently, by setting
CS to high again, the DO pin outputs a low level if the write operation is still in progress and a high level if the write
operation is complete (verify operation). Therefore, only after a write operation, in order to input the next command, CS
is set to high, which switches the DO pin from a high-impedance state (High-Z) to a data output state. However, if start
bit is recognized, the DO pin returns to the high-impedance state (refer to Figure 5 Timing Chart).
Make sure that data output from the CPU does not interfere with the data output from the serial memory IC when
configuring a 3 -wire interface by connecting the DI input pin and DO output pin, as such interference may cause a start
bit fetch problem. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
13
3-WIRE SERIAL E2PROM
S-93C76A
Write Protect Function during the Low Power Supply Voltage
N
Rev.7.0_03
Hysteresis
About 0.3 V
NE
Power supply voltage
W
DE
SI
G
The S-93C76A provides a built-in detector to detect a low power supply voltage and disable writing. When the power
supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled,
and the write disable state (EWDS) is automatically set. The detection voltage is 1.75 V typ., the release voltage is
2.05 V typ., and there is a hysteresis of about 0.3 V (refer to Figure 12). Therefore, when a write operation is
performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible,
a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is
executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
Release voltage (VDET)
2.05 V typ.
R
Detection voltage (VDET)
1.75 V typ.
Operation during Low Power Supply Voltage
NO
T
RE
C
OM
M
EN
DE
D
Figure 12
FO
Write instruction cancelled
Write disable state (EWDS) automatically set
14
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
N
3-Wire Interface (Direct Connection between DI and DO)
CPU
SIO
NE
DI
DO
W
S-93C76A
DE
SI
G
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93C76A via a resistor (10 k to 100 k) so that the data output from the CPU takes precedence in being input
to the DI pin (refer to Figure 13).
R: 10 k to 100 k
Connection of 3-Wire Interface
R
Figure 13
1.
FO
Input Pin and Output Pin
Connection of input pins
2.
DE
D
All the input pins of the S-93C76A employ a CMOS structure, so design the equipment so that high impedance will
not be input while the S-93C76A is operating. Especially, deselect the CS input (a low level) when turning on / off
power and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur.
Connect the CS pin to GND via a resistor (10 k to 100 k pull-down resistor). To prevent malfunction, it is
recommended to use equivalent pull-down resistors for pins other than the CS pin.
Equivalent circuit of input and output pin
NO
T
RE
C
OM
M
EN
The following shows the equivalent circuits of input pins of the S-93C76A. None of the input pins incorporate pullup and pull-down elements, so special care must be taken when designing to prevent a floating status.
Output pins are high-level / low-level / high-impedance tri-state outputs. The TEST pin is disconnected from the
internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is
satisfied, the TEST pin and internal circuit will never be connected.
15
3-WIRE SERIAL E2PROM
S-93C76A
N
Input pin
DE
SI
G
2. 1
Rev.7.0_03
CS Pin
R
Figure 14
NE
W
CS
DE
D
FO
SK, DI
NO
T
RE
C
M
OM
TEST
SK, DI Pin
EN
Figure 15
16
Figure 16
TEST Pin
3-WIRE SERIAL E2PROM
S-93C76A
Output pin
VCC
DE
SI
G
2. 2
N
Rev.7.0_03
DO Pin
FO
Figure 17
R
NE
W
DO
3. Input pin noise elimination time
DE
D
The S-93C76A includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the
supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated.
Note, therefore, that noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds VIH
/ VIL.
Precaution
EN
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
NO
T
RE
C
OM
M
● ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
17
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
DC Characteristics
1. 1
Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 2
Current consumption (READ) ICC1
vs. ambient temperature Ta
VCC = 3.3 V
fSK = 500 kHz
DATA = 0101
VCC = 5.5 V
fSK = 2 MHz
DATA = 0101
0.4
0.4
ICC1
(mA)
ICC1
(mA)
0.2
0
85
0
Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 4
VCC = 1.8 V
fSK = 10 kHz
DATA = 0101
D
0.4
DE
ICC1
(mA)
0
40
0
0.4
ICC1
(mA)
1 MHz
0.2
500 kHz
85
0
Ta (C)
Current consumption (READ) ICC1
vs. power supply voltage VCC
1. 6
RE
C
ICC1
(mA)
100 kHz
T
NO
18
10 kHz
3
4
5 6
VCC (V)
5
6
0.4
0.2
2
4
VCC = 5.0 V
Ta = 25C
0.4
0
3
Current consumption (READ) ICC1
vs. Clock frequency fSK
Ta = 25C
fSK = 100 kHz, 10 kHz
DATA = 0101
ICC1
(mA)
2
VCC (V)
M
OM
1. 5
Ta (C)
Ta = 25C
fSK = 1 MHz, 500 kHz
DATA = 0101
EN
0.2
85
Current consumption (READ) ICC1
vs. power supply voltage VCC
FO
1. 3
0
R
Ta (C)
40
40
NE
W
0.2
0
DE
SI
G
1.
N
Characteristics (Typical Data)
0.2
0
7
10 k 100 k 1 M 2M 10M
fSK (Hz)
7
3-WIRE SERIAL E2PROM
S-93C76A
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1. 8
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
VCC = 3.3 V
VCC = 5.5 V
1.0
1.0
ICC2
(mA)
ICC2
(mA)
0.5
0
0
85
Ta (C)
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1. 10
FO
VCC = 2.7 V
1.0
ICC2
(mA)
0
Ta (C)
85
Current consumption (WRITE) ICC2
vs. power supply voltage VCC
R
1. 9
40
NE
40
W
0.5
0
DE
SI
G
1. 7
N
Rev.7.0_03
Ta = 25C
1.0
ICC2
(mA)
40
0
85
EN
Ta (C)
DE
0
0.5
D
0.5
M
1. 11 Current consumption in standby mode ISB
vs. ambient temperature Ta
0
OM
RE
C
ISB
(A)
40
4
5 6
7
1. 12 Current consumption in standby mode ISB
vs. power supply voltage VCC
Ta = 25C
CS = GND
ISB
(A)
1.0
0.5
0.5
0
3
VCC (V)
VCC = 5.5 V
CS = GND
1.0
2
0
0
2
3
4
5 6
7
VCC (V)
NO
T
Ta (°C)
85
19
3-WIRE SERIAL E2PROM
S-93C76A
Input leakage current ILI
vs. ambient temperature Ta
VCC = 5.5 V
CS, SK, DI,
TEST = 0 V
VCC = 5.5 V
CS, SK, DI,
TEST = 5.5 V
1.0
1.0
ILI
(A)
ILI
(A)
0.5
W
0.5
40
0
85
Ta (C)
Output leakage current ILO
vs. ambient temperature Ta
1. 16
FO
VCC = 5.5 V
DO = 0 V
1.0
0.5
0
40
0
85
High-level output voltage VOH
vs. ambient temperature Ta
M
1. 17
EN
Ta (C)
4.4
RE
C
VOH
(V)
40
0
NO
T
Ta (C)
20
1.0
0.5
0
40
0
85
Ta (°C)
1. 18
High-level output voltage VOH
vs. ambient temperature Ta
2.7
VOH
(V)
4.2
Ta (C)
VCC = 5.5 V
DO = 5.5 V
VCC = 4.5 V
IOH = 400 A
OM
4.6
85
ILO
(A)
DE
D
ILO
(A)
0
Output leakage current ILO
vs. ambient temperature Ta
R
1. 15
40
NE
0
0
N
1. 14
Input leakage current ILI
vs. ambient temperature Ta
DE
SI
G
1. 13
Rev.7.0_03
VCC = 2.7 V
IOH = 100 A
2.6
2.5
85
40
0
Ta (C)
85
Rev.7.0_03
High-level output voltage VOH
vs. ambient temperature Ta
High-level output voltage VOH
vs. ambient temperature Ta
VCC = 2.5 V
IOH = 100 A
2.5
VOH
(V)
1. 20
1.9
VOH
(V)
2.4
2.3
85
40
Ta (C)
Low-level output voltage VOL
vs. ambient temperature Ta
FO
0.2
0
85
High-level output current IOH
vs. ambient temperature Ta
OM
RE
C
0
1. 24
High-level output current IOH
vs. ambient temperature Ta
VCC = 2.7 V
VOH = 2.4 V
1
85
0
40
0
85
Ta (C)
NO
T
Ta (C)
85
IOH
(mA)
10.0
40
0
Ta (C)
2
20.0
0
VCC = 1.8 V
IOL = 100 A
40
VCC = 4.5 V
VOH = 2.4 V
IOH
(mA)
Ta (C)
0.01
M
1. 23
EN
Ta (C)
0.03
DE
40
85
VOL 0.02
(V)
D
0.1
0
Low-level output voltage VOL
vs. ambient temperature Ta
R
VCC = 4.5 V
IOL = 2.1 mA
0.3
VOL
(V)
1. 22
NE
0
VCC = 1.8 V
IOH = 10 A
W
1.7
40
1. 21
1.8
DE
SI
G
1. 19
N
3-WIRE SERIAL E2PROM
S-93C76A
21
3-WIRE SERIAL E2PROM
S-93C76A
1. 26
High-level output current IOH
vs. ambient temperature Ta
VCC = 2.5 V
VOH = 2.2 V
VCC = 1.8 V
VOH = 1.6 V
2
1.0
IOH
(mA)
IOH
(mA)
1
0.5
0
0
W
40
85
Ta (C)
1. 27
Low-level output current IOL
vs. ambient temperature Ta
1. 28
85
Low-level output current IOL
vs. ambient temperature Ta
FO
20
0
Ta (C)
VCC = 1.8 V
VOL = 0.1 V
R
VCC = 4.5 V
VOL = 0.4 V
40
NE
0
N
High-level output current IOH
vs. ambient temperature Ta
DE
SI
G
1. 25
Rev.7.0_03
1.0
IOL
(mA)
IOL
(mA)
0.5
1. 29
40
0
Ta (C)
85
EN
0
DE
D
10
Input inverted voltage VINV
vs. power supply voltage VCC
0
M
RE
C
1.5
OM
3.0
0
1
2
3
4 5
NO
T
VCC (V)
22
0
Ta (C)
85
1. 30 Input inverted voltage VINV
vs. ambient temperature Ta
Ta = 25C
CS, SK, DI
VINV
(V)
40
VCC = 5.0 V
CS, SK, DI
3.0
VINV
(V)
2.0
6 7
0
40
0
Ta (C)
85
3-WIRE SERIAL E2PROM
S-93C76A
Low power supply detection voltage VDET
vs. ambient temperature Ta
1. 32 Low power supply release voltage VDET
vs. ambient temperature Ta
2.0
2.0
VDET
(V)
VDET
(V)
1.0
40
0
W
0
1.0
DE
SI
G
1. 31
N
Rev.7.0_03
0
85
0
85
Ta (C)
NO
T
RE
C
OM
M
EN
DE
D
FO
R
NE
Ta (C)
40
23
3-WIRE SERIAL E2PROM
S-93C76A
2. 1
Maximum operating frequency fMAX.
vs. power supply voltage VCC
2. 2
Write time tPR
vs. power supply voltage VCC
Ta = 25C
fMAX.
(Hz)
Ta = 25C
2M
1M
4
tPR
(ms)
100k
2
W
10k
2
3
4
1
5
VCC (V)
2. 4
VCC = 5.0 V
6
2
0
85
EN
40
M
Write time tPR
vs. ambient temperature Ta
6
2
40
RE
C
4
OM
6
2. 6
T
NO
0
Ta (C)
85
Data output delay time tPD
vs. ambient temperature Ta
VCC = 4.5 V
tPD
(s)
0.3
0.2
2
40
0
Ta (C)
VCC = 2.7 V
tPR
(ms)
5 6
VCC = 3.0 V
Ta (C)
2. 5
4
VCC (V)
4
D
4
tPR
(ms)
DE
tPR
(ms)
3
Write time tPR
vs. ambient temperature Ta
R
Write time tPR
vs. ambient temperature Ta
FO
2. 3
2
NE
1
24
N
AC Characteristics
DE
SI
G
2.
Rev.7.0_03
0.1
85
40
0
Ta (C)
85
7
Rev.7.0_03
Data output delay time tPD
vs. ambient temperature Ta
2. 8
Data output delay time tPD
vs. ambient temperature Ta
VCC = 2.7 V
tPD
(s)
VCC = 1.8 V
0.6
tPD
(s)
0.4
1.5
1.0
0.5
0
W
0.2
40
DE
SI
G
2. 7
N
3-WIRE SERIAL E2PROM
S-93C76A
40
85
85
Ta (C)
NO
T
RE
C
OM
M
EN
DE
D
FO
R
NE
Ta (C)
0
25
3-WIRE SERIAL E2PROM
S-93C76A
Rev.7.0_03
Product name
1. 1
DE
SI
G
1.
N
Product Name Structure
8-Pin SOP (JEDEC)
S-93C76AD
FJ
-
TB
-
x
W
Environmental code
U: Lead-free (Sn 100%), halogen-free
G: Lead-free (for details, please contact our sales office)
NE
IC direction in tape specification
Package code
FJ: 8-Pin SOP (JEDEC)
1. 2
FO
R
Product name
S-93C76AD: 8 K-bit
8-Pin TSSOP
-
TB
-
x
D
S-93C76A FT
DE
Environmental code
U: Lead-free (Sn 100%), halogen-free
G: Lead-free (for details, please contact our sales office)
EN
IC direction in tape specification
1. 3
TMSOP-8
-
TF
NO
T
RE
C
S-93C76A FM
26
Product name
S-93C76A: 8 K-bit
OM
M
Package code
FT: 8-Pin TSSOP
-
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
IC direction in tape specification
Package code
FM:
TMSOP-8
Product name
S-93C76A: 8 K-bit
Rev.7.0_03
Packages
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
Drawing Code
Tape
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
FM008-A-P-SD
FJ008-D-C-SD
FJ008-D-C-SD
FT008-E-C-SD
FT008-E-C-SD
FM008-A-C-SD
Reel
FJ008-D-R-SD
FJ008-D-R-S1
FT008-E-R-SD
FT008-E-R-S1
FM008-A-R-SD
NO
T
RE
C
OM
M
EN
DE
D
FO
R
NE
W
TMSOP-8
Package
DE
SI
G
2.
N
3-WIRE SERIAL E2PROM
S-93C76A
27
1
4
DE
SI
G
5
NE
W
8
N
5.02±0.2
DE
D
FO
R
0.20±0.05
1.27
NO
T
RE
C
OM
M
EN
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
N
2.0±0.05
ø1.55±0.05
2.1±0.1
FO
R
NE
8.0±0.1
ø2.0±0.05
W
DE
SI
G
0.3±0.05
5
Feed direction
NO
T
RE
C
OM
M
4
8
EN
1
DE
D
6.7±0.1
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
2,000
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
+0.3
5
1
4
R
NE
W
8
DE
SI
G
3.00 -0.2
DE
D
FO
0.17±0.05
EN
0.2±0.1
NO
T
RE
C
OM
M
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
+0.1
8.0±0.1
NE
ø1.55 -0.05
W
DE
SI
G
N
0.3±0.05
FO
R
(4.4)
+0.4
EN
DE
D
6.6 -0.2
8
M
1
4
NO
T
RE
C
OM
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
DE
SI
G
2.90±0.2
5
1
4
NE
W
8
D
FO
R
0.13±0.1
0.2±0.1
NO
T
RE
C
OM
M
EN
DE
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
1.00±0.1
N
4.00±0.1
+0.1
1.5 -0
NE
W
DE
SI
G
4.00±0.1
1.05±0.05
FO
R
0.30±0.05
1
EN
4
DE
D
3.25±0.05
8
Feed direction
NO
T
RE
C
OM
M
5
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
FO
R
NE
W
DE
SI
G
16.5max.
13±0.2
OM
M
EN
Enlarged drawing in the central part
DE
D
13.0±0.3
NO
T
RE
C
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
EN
DE
D
FO
R
NE
W
DE
SI
G
N
1.
M
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
OM
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
RE
C
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
T
14. For more details on the information described herein, contact our sales office.
NO
2.0-2018.01
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