N
S-93C86B
3-WIRE SERIAL E2PROM
DE
SI
G
www.ablicinc.com
Rev.5.0_03
© ABLIC Inc., 2003-2015
W
The S-93C86B is a high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S93C86B has the capacity of 16 K-bit, and the organization is 1024-word 16 bit. It is capable of sequential read, at which
time addresses are automatically incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Operating voltage range:
Read
1.8 V to 5.5 V
Write
2.7 V to 5.5 V
2.0 MHz (VCC = 4.5 V to 5.5 V)
4.0 ms max.
NE
Features
DE
D
FO
R
Operation frequency:
Write time:
Sequential read capable
Write protect function during the low power supply voltage
Function to protect against write due to erroneous instruction recognition
Endurance:
106 cycles / word*1 (Ta = 85C)
Data retention:
100 years (Ta = 25C)
20 years (Ta = 85C)
Memory capacity:
16 K-bit
Initial delivery state:
FFFFh
Operation temperature range:
Ta = 40°C to 85C
Lead-free, Sn 100%, halogen-free*2
Packages
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is
indispensable.
NO
T
RE
C
Caution
OM
8-Pin SOP (JEDEC)
8-Pin TSSOP
M
EN
*1. For each address (Word: 16-bit)
*2. Refer to “ Product Name Structure” for details.
1
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
8-Pin SOP (JEDEC)
Table 1
8-Pin SOP (JEDEC)
Top view
8
7
3
6
4
5
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
FO
R
S-93C86BD4I-J8T1x
8-Pin TSSOP
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
D
OM
S-93C86BD4I-T8T1x
Symbol
CS
Description
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
M
Figure 2
Pin No.
1
EN
8
7
6
5
Table 2
DE
8-Pin TSSOP
Top view
1
2
3
4
Description
GND
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
Figure 1
2.
Symbol
CS
NE
2
Pin No.
1
W
1
DE
SI
G
1.
N
Pin Configurations
NO
T
RE
C
Remark 1. Refer to the “package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
2
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
VCC
Address
Memory array
decoder
Data register
GND
Output buffer
DO
W
DI
NE
Mode decode logic
CS
Clock pulse
monitoring circuit
FO
R
Voltage detector
Clock generator
D
SK
DE
SI
G
N
Block Diagram
NO
T
RE
C
OM
M
EN
DE
Figure 3
3
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Table 3
Operation
Code
Start Bit
SK input clock
1
2
3
READ (Read data)
1
1
0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 Output*1
WRITE (Write data)
1
0
1
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data)
1
1
1
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
WRAL (Write all)
1
0
0
0
1
x
x
x
x
ERAL (Erase all)
1
0
0
1
0
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
*1.
5
6
7
8
x
9
x
10 11 12 13
x
x
x
W
4
x
14 to 29
D15 to D0 Input
x
x
x
x
x
x
x
x
x
x
x
x
When the 16-bit data in the specified address has been output, the data in the next address is output.
NO
T
RE
C
OM
M
EN
DE
D
FO
R
Remark x: Don’t care
4
Data
Instruction
NE
Address
DE
SI
G
N
Instruction Sets
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
N
Absolute Maximum Ratings
Item
DE
SI
G
Table 4
Symbol
Ratings
Unit
Recommended Operating Conditions
Table 5
High level input voltage
VIH
Low level input voltage
VIL
EN
Pin Capacitance
Symbol
CIN
COUT
RE
C
OM
M
Item
Input Capacitance
Output Capacitance
Endurance
READ, EWDS
WRITE, ERASE,
WRAL, ERAL, EWEN
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
FO
VCC
D
Power supply voltage
Conditions
R
Symbol
DE
Item
NE
W
Power supply voltage
VCC
0.3 to 7.0
V
Input voltage
VIN
0.3 to VCC 0.3
V
Output voltage
VOUT
0.3 to VCC
V
Operation ambient temperature Topr
40 to 105
C
Storage temperature
Tstg
65 to 150
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Ta = 40C to 85C
Min.
Max.
1.8
5.5
Unit
V
2.7
5.5
V
2.0
0.8 VCC
0.8 VCC
0.0
0.0
0.0
VCC
VCC
VCC
0.8
0.2 VCC
0.15 VCC
V
V
V
V
V
V
Table 6
(Ta = 25C, f = 1.0 MHz, VCC = 5.0 V)
Conditions
VIN = 0 V
VOUT = 0 V
Min.
Max.
8
10
Unit
pF
pF
Table 7
Item
Symbol
Operation Ambient Temperature
Endurance
NW
Ta = 40°C to 85C
*1. For each address (Word: 16-bit)
Min.
106
Max.
Unit
Cycles / word*1
NO
T
Data Retention
Item
Data retention
Table 8
Symbol
Operation Ambient Temperature
Ta = 25°C
Ta = 40°C to 85°C
Min.
100
20
Max.
Unit
year
year
5
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Table 9
Item
Symbol
Current consumption
ICC1
(READ)
Ta = 40C to 85C
Conditions VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.8 V to 2.5 V Unit
Min.
Max.
Min.
Max.
Min.
Max.
DO no load
0.8
0.5
Table 10
Current consumption
ICC2
(WRITE)
W
DO no load
1.5
mA
FO
Ta = 40C to 85C
VCC =
VCC =
VCC =
Unit
4.5 V to 5.5 V 2.5 V to 4.5 V 1.8 V to 2.5 V
Min.
Max.
Min.
Max.
Min. Max.
1.5
1.5
1.5
A
ILI
VIN = GND to VCC
1.0
1.0
1.0
A
ILO
VOUT = GND to VCC
1.0
1.0
1.0
A
2.4
VCC0.3
VCC0.2
0.4
0.1
VCC0.3
VCC0.2
0.1
VCC0.2
0.1
V
V
V
V
V
1.5
1.5
V
VOL
VOH
DE
D
IOL = 2.1 mA
IOL = 100 A
IOH = 400 A
IOH = 100 A
IOH = 10 A
Only program disable mode
OM
RE
C
T
NO
Unit
CS = GND, DO = Open,
Other inputs to VCC or GND
Data hold voltage
V
of write enable latch DH
6
mA
ISB
EN
High level output
voltage
Conditions
M
Standby current
consumption
Input leakage
current
Output leakage
current
Low level output
voltage
Symbol
2.0
Table 11
Item
0.4
Ta = 40C to 85C
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
Min.
Max.
Min.
Max.
Conditions
NE
Symbol
R
Item
DE
SI
G
N
DC Electrical Characteristics
1.5
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Table 12
Measurement Conditions
0.1 VCC to 0.9 VCC
Input pulse voltage
0.5 VCC
Output reference voltage
Output load
100 pF
Table 13
Symbol
VCC = 4.5 V to 5.5 V
VCC = 2.5 V to 4.5 V VCC = 1.8 V to 2.5 V
Max.
Min.
Max.
Min.
Unit
Max.
NE
Min.
W
Ta = 40C to 85C
Item
DE
SI
G
N
AC Electrical Characteristics
DE
D
FO
R
CS setup time
tCSS
0.2
0.4
1.0
s
CS hold time
tCSH
0
0
0
s
CS deselect time
tCDS
0.2
0.2
0.4
s
Data setup time
tDS
0.1
0.2
0.4
s
Data hold time
tDH
0.1
0.2
0.4
s
Output delay time
tPD
0.4
0.8
2.0
s
Clock frequency*1
0
2.0
0
0.5
0
0.25
MHz
fSK
SK clock time “L” *1
0.1
0.5
1.0
s
tSKL
SK clock time “H” *1
0.1
0.5
1.0
s
tSKH
Output disable time
tHZ1, tHZ2
0
0.15
0
0.5
0
1.0
s
Output enable time
tSV
0
0.15
0
0.5
0
1.0
s
*1. The clock cycle of the SK clock (frequency: fSK) is 1 / fSK s. This clock cycle is determined by a combination of
several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK)
cannot be made to equal tSKL (min.) tSKH (min.).
Item
EN
Table 14
Symbol
tPR
Unit
Max.
4.0
ms
NO
T
RE
C
OM
M
Write time
Min.
Ta = 40C to 85C
VCC = 2.7 V to 5.5 V
Typ.
2.0
7
3-WIRE SERIAL E2PROM
S-93C86B
1 / fSK
tCSS
*2
tCDS
tSKH
tCSH
tSKL
SK
tDS
DI
tDH
tDS
Valid data
tPD
(READ)
DO
tSV
W
*1
tHZ2
NE
High-Z
tDH
Valid data
tPD
DO
DE
SI
G
CS
N
Rev.5.0_03
High-Z
tHZ1
High-Z
R
(VERIFY)
High-Z
Indicates high impedance.
*2.
1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics,
FO
*1.
so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot be made to
D
equal tSKL (min.) tSKH (min.).
Timing Chart
NO
T
RE
C
OM
M
EN
DE
Figure 4
8
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
N
Initial Delivery State
DE
SI
G
Initial delivery state of all addresses is “FFFFh”.
Operation
W
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS. While
a low level is being input to CS, the S-93C86B is in standby mode, so the SK and DI inputs are invalid and no
instructions are allowed.
Start Bit
1.
NE
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit
is not recognized even if the SK pulse is input as long as the DI pin is low.
Dummy clock
2.
FO
R
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks can
be adjusted by inserting a 3-bit dummy clock for the S-93C86B.
Start bit input failure
D
When the output status of the DO pin is high during the verify period after a write operation, if a high level is input
to the DI pin at the rising edge of SK, the S-93C86B recognizes that a start bit has been input. To prevent this
failure, input a low level to the DI pin during the verify operation period (refer to “4.1 Verify operation”).
NO
T
RE
C
OM
M
EN
DE
When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the data
output from the CPU and the serial memory collide may be generated, preventing successful input of the start bit.
Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
9
3-WIRE SERIAL E2PROM
S-93C86B
Reading (READ)
N
3.
Rev.5.0_03
DE
SI
G
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A0) has been latched, the output status of the DO pin changes from high impedance (High-Z) to
low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of
SK.
Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically
increments the address, and causes the 16-bit data at the next address to be output sequentially. The
above method makes it possible to read the data in the whole memory space. The last address (A9 A1
A0 = 1 1 1) rolls over to the top address (A9 A1 A0 = 0 0 0).
W
3. 1
2
1
3
0
4
A9
5
A8
6
A7
7
A6
8
A5
9
A4
10
A3
11
A2
12
A1
High-Z
DO
13
14
15
16
26
27
28
A0
0
29
30
31
R
DI
1
D15 D14 D13
D2
D1
D0 D15 D14 D13
FO
SK
NE
CS
ADRINC
Read Timing
NO
T
RE
C
OM
M
EN
DE
D
Figure 5
10
42
43
D2
44
D1
45
46
47
D0 D15 D14 D13
ADRINC
High-Z
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Writing (WRITE, ERASE, WRAL, ERAL)
N
4.
Verify operation
A write operation executed by any instruction is completed within 4 ms (write time tPR: typically 2 ms), so if the
completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to
confirm the status of a write operation is called a verify operation.
NE
W
4. 1
DE
SI
G
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is
input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write
period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
Operation
After the write operation has started (CS = low), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting a high level to CS again. This sequence is
called a verify operation, and the period that a high level is input to the CS pin after the write operation
has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify
operation period is as follows.
DO pin = low: Writing in progress (busy)
DO pin = high: Writing completed (ready)
4. 1. 2
Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the
DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing
it again to verify the output status of the DO pin. The latter method allows the CPU to perform other
processing during the wait period, allowing an efficient system to be designed.
DE
EN
Input a low level to the DI pin during a verify operation.
If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93C86B latches the instruction assuming that a start bit has been input. In this
case, note that the DO pin immediately enters a high-impedance (High-Z) state.
NO
T
RE
C
OM
M
Caution 1.
2.
D
FO
R
4. 1. 1
11
3-WIRE SERIAL E2PROM
S-93C86B
Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address,
and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to
set the data to 1 before writing. When the clocks more than the specified number have been input, the clock
pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer
to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
DE
SI
G
N
4. 2
Rev.5.0_03
tCDS
CS
Verify
1
DI
2
0
3
1
4
5
6
7
8
9
10
11
12
13
14
29
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D0
tSV
NE
High-Z
DO
W
SK
tHZ1
busy
ready
High-Z
tPR
Data Write Timing
R
Figure 6
Standby
Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input
the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when CS goes low. When the clocks more than the specified number have been input, the
clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring
circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
CS
1
2
DI
1
3
1
4
5
A9
A8
8
9
10
11
12
A7
A6
A5
A4
A3
A2
A1
13
A0
tSV
busy
tPR
Figure 7
Standby
Verify
M
OM
RE
C
T
NO
7
tCDS
High-Z
DO
12
6
EN
SK
DE
D
FO
4. 3
Data Erase Timing
tHZ1
ready
High-Z
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write
operation starts when CS goes low. There is no need to set the data to 1 before writing. When the clocks
more than the specified number been input, the clock pulse monitoring circuit cancels the WRAL instruction.
For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
DE
SI
G
N
4. 4
tCDS
CS
Verify
2
DI
0
3
0
4
0
5
6
7
9
12
13
14
D15
8Xs
29
tSV
NE
D0
tHZ1
busy
ready
High-Z
tPR
Chip Write Timing
FO
Figure 8
Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no
need to input data. The chips erase operation starts when CS goes low. When the clocks more than the
specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For
details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
DE
D
4. 5
11
10
1
High-Z
DO
8
W
1
R
SK
Standby
1
2
3
4
DI
0
0
1
High-Z
0
6
7
8
9
Standby
Verify
tCDS
10
11
12
13
tSV
8Xs
tHZ1
busy
ready
High-Z
tPR
Figure 9
Chip Erase Timing
NO
T
RE
C
OM
DO
5
M
SK
EN
CS
13
3-WIRE SERIAL E2PROM
S-93C86B
Write enable (EWEN) and write disable (EWDS)
N
5.
Rev.5.0_03
DE
SI
G
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is
enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been
input.
CS
Standby
DI
2
0
3
4
5
6
8
8Xs
11
12
13
Write Enable/Disable Timing
R
Figure 10
T
RE
C
OM
M
EN
DE
D
FO
Recommendation for write operation disable instruction
It is recommended to implement a design that prevents an incorrect write operation when a write instruction is
erroneously recognized by executing the write operation disable instruction when executing instructions other
than write instruction, and immediately after power-on and before power off.
NO
14
10
9
0
11 = EWEN
00 = EWDS
5. 1
7
W
1
NE
SK
Rev.5.0_03
Write Protect Function during the Low Power Supply Voltage
N
3-WIRE SERIAL E2PROM
S-93C86B
Hysteresis
About 0.3 V
Power supply voltage
W
DE
SI
G
The S-93C86B provides a built-in detector. When the power supply voltage is low or at power application, the write
instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically
set. The detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of about 0.3 V
(refer to Figure 11). Therefore, when a write operation is performed after the power supply voltage has dropped and
then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a
write instruction (WRITE, ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
NE
Release voltage (VDET)
2.05 V typ.
R
Detection voltage (VDET)
1.75 V typ.
Operation during Low Power Supply Voltage
NO
T
RE
C
OM
M
EN
DE
D
Figure 11
FO
Write instruction cancelled
Write disable state (EWDS) automatically set
15
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
N
Function to Protect Against Write due to Erroneous Instruction Recognition
DE
SI
G
The S-93C86B provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation
by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock
count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse whose count other than the one specified for each write instruction (WRITE,
ERASE, WRAL, or ERAL) is detected.
Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93C86B
CS
1
2
3
4
5
6
7
8
9
10
11 12
0
0
Erroneous recognition as
ERASE instruction due to
noise pulse
1 1 10
0
0
0
D
1
0 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
DE
Input EWDS instruction
FO
DI
M
In products that do not incorporate a clock pulse monitoring circuit, FFFFh is
mistakenly written to address 00h. However the S-93C86B detects the over count
and cancels the instruction without performing a write operation.
Example of Clock Pulse Monitoring Circuit Operation
NO
T
RE
C
OM
Figure 12
16
13
R
SK
NE
W
Noise pulse
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
N
3-Wire Interface (Direct Connection between DI and DO)
CPU
SIO
NE
DI
DO
W
S-93C86B
DE
SI
G
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93C86B via a resistor (10 k to 100 k) so that the data output from the CPU takes precedence in being input
to the DI pin (refer to “Figure 13 Connection of 3-Wire Interface”).
R: 10 k to 100 k
R
Connection of 3-Wire Interface
FO
Figure 13
Input Pin and Output Pin
Connection of input pins
D
1.
2.
EN
DE
All the input pins of the S-93C86B employ a CMOS structure, so design the equipment so that high impedance will not
be input while the S-93C86B is operating. Especially, deselect the CS input (a low level) when turning on / off power
and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur. Connect the
CS pin to GND via a resistor (10 k to 100 k pull-down resistor). To prevent malfunction, it is recommended to use
equivalent pull-down resistors for pins other than the CS pin.
Equivalent circuit of input pin and output pin
NO
T
RE
C
OM
M
The following shows the equivalent circuits of input pins of the S-93C86B. None of the input pins incorporate pull-up
and pull-down elements, so special care must be taken when designing to prevent a floating status.
Output pins are high-level / low-level / high-impedance tri-state outputs. The TEST pin is disconnected from the
internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is satisfied,
the TEST pin and internal circuit will never be connected.
17
3-WIRE SERIAL E2PROM
S-93C86B
Input pin
DE
SI
G
N
2. 1
Rev.5.0_03
NE
CS Pin
R
Figure 14
W
CS
DE
D
FO
SK, DI
NO
T
RE
C
M
OM
TEST
SK, DI Pin
EN
Figure 15
18
Figure 16
TEST Pin
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Output pin
N
2. 2
DE
SI
G
VCC
NE
W
DO
Input pin noise elimination time
FO
3.
DO Pin
R
Figure 17
DE
D
The S-93C86B includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the
supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated.
Note, therefore, that noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds
VIH / VIL.
Precaution
EN
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
M
● ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
NO
T
RE
C
OM
products including this IC upon patents owned by a third party.
19
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 2
Current consumption (READ) ICC1
vs. ambient temperature Ta
0.4
ICC1
(mA)
0.2
0.2
-40
0
Ta (C)
NE
VCC5.5 V
fSK2 MHz
DATA0101
0
85
1. 4
vs. ambient temperature Ta
D
DE
ICC1
(mA)
85
1 MHz
0.2
500 kHz
0
2
M
0
Ta (C)
OM
-40
0.4
Current consumption (READ) ICC1
vs. power supply voltage VCC
1. 6
NO
0
20
2
6
7
Current consumption (READ) ICC1
VCC5.5 V
Ta25C
0.4
ICC1
(mA)
100 kHz
T
0.2
RE
C
0.4
3 4 5
VCC (V)
vs. Clock frequency fSK
Ta25C
fSK100 kHz, 10 kHz
DATA0101
ICC1
(mA)
Ta25C
fSK1 MHz, 500 kHz
DATA0101
ICC1
(mA)
EN
0.2
0
85
vs. power supply voltage VCC
VCC1.8 V
fSK500 kHz
DATA0101
0.4
0
Ta (C)
Current consumption (READ) ICC1
FO
Current consumption (READ) ICC1
-40
R
0
1. 5
VCC3.3 V
fSK500 kHz
DATA0101
0.4
ICC1
(mA)
1. 3
DE
SI
G
1. 1
DC Characteristics
W
1.
N
Characteristics (Typical Data)
0.2
10 kHz
3 4 5
VCC (V)
6
7
0
10
1k
100 k 10 M
fSK (Hz)
Rev.5.0_03
Current consumption (WRITE) ICC2
1. 8
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
VCC=5.5 V
VCC=3.3 V
1.0
1.0
ICC2
(mA)
ICC2
(mA)
0.5
0.5
-40
0
Ta (C)
0
85
Current consumption (WRITE) ICC2
1. 10
85
Current consumption (WRITE) ICC2
vs. power supply voltage VCC
FO
VCC=2.7 V
Ta=25C
1.0
1.0
ICC2
(mA)
D
ICC2
(mA)
-40
0
85
M
Ta (C)
0.5
0
EN
0
DE
0.5
1. 11
0
Ta (C)
R
vs. ambient temperature Ta
-40
NE
0
1. 9
DE
SI
G
vs. ambient temperature Ta
W
1. 7
N
3-WIRE SERIAL E2PROM
S-93C86B
Current consumption in standby mode ISB
1. 12
NO
-40
0
Ta (C)
85
5 6
7
vs. power supply voltage VCC
OM
T
0
RE
C
0.5
4
Current consumption in standby mode ISB
VCC=5.5 V
CS=GND
1.0
3
VCC (V)
vs. ambient temperature Ta
ISB
(A)
2
Ta=25C
CS=GND
ISB
(A)
1.0
0.5
0
2
3
4
5
6
7
VCC (V)
21
3-WIRE SERIAL E2PROM
S-93C86B
1. 14
vs. ambient temperature Ta
VCC=5.5 V
CS, SK, DI,
TEST=5.5 V
VCC=5.5 V
CS, SK, DI,
TEST=0 V
1.0
1.0
lLI
(A)
lLI
(A)
0.5
0.5
-40
0
0
85
Ta (C)
Output leakage current ILO
1. 16
VCC=5.5 V
DO=5.5 V
1.0
lLO
(A)
D
lLO
(A)
-40
0
85
Ta (C)
High-level output voltage VOH
OM
VCC=4.5 V
IOH=-400 A
4.6
RE
C
4.4
4.2
M
vs. ambient temperature Ta
EN
0
DE
0.5
NO
T
-40
22
Output leakage current ILO
FO
1.0
VOH
(V)
85
vs. ambient temperature Ta
VCC=5.5 V
DO=0 V
1. 17
0
Ta (C)
R
vs. ambient temperature Ta
-40
NE
0
1. 15
DE
SI
G
vs. ambient temperature Ta
Input leakage current ILI
0
85
Ta (C)
0.5
0
1. 18
-40
0
85
Ta (C)
High-level output voltage VOH
vs. ambient temperature Ta
2.8
N
Input leakage current ILI
W
1. 13
Rev.5.0_03
VCC=2.7 V
IOH=-100 A
VOH 2.6
(V)
2.4
-40
0
Ta (C)
85
Rev.5.0_03
High-level output voltage VOH
1. 20
0.3
VOL
(V)
1.8
VCC=4.5 V
IOL=2.1 mA
0.2
0.1
1.7
-40
1. 21
DE
SI
G
VCC=1.8 V
IOH=-10 A
1.9
VOH
(V)
vs. ambient temperature Ta
0
Ta (C)
85
-40
Low-level output voltage VOL
1. 22
85
High-level output current IOH
vs. ambient temperature Ta
FO
VCC=1.8 V
IOL=100 A
0.03
0
Ta (C)
R
vs. ambient temperature Ta
W
vs. ambient temperature Ta
Low-level output voltage VOL
NE
1. 19
N
3-WIRE SERIAL E2PROM
S-93C86B
VCC=4.5 V
VOH=2.4 V
-20.0
VOL 0.02
(V)
D
IOH
(mA)
1. 23
0
Ta (C)
85
High-level output current IOH
OM
VCC=2.7 V
VOH=2.4 V
-2
-1
-40
1. 24
0
85
Ta (C)
-40
0
85
Ta (C)
High-level output current IOH
vs. ambient temperature Ta
VCC=1.8 V
VOH=1.6 V
-2
IOH
(mA)
-1
0
-40
0
85
Ta (C)
NO
T
0
RE
C
IOH
(mA)
-10.0
0
M
vs. ambient temperature Ta
EN
-40
DE
0.01
23
3-WIRE SERIAL E2PROM
S-93C86B
1. 26
vs. ambient temperature Ta
Low-level output current IOL
vs. ambient temperature Ta
VCC=4.5 V
VOL=0.4 V
VCC=1.8 V
VOL=0.1 V
20
1.0
IOL
(mA)
IOL
(mA)
10
1. 27
-40
0
Ta (C)
0
85
Input inverted voltage VINV
1. 28
vs. power supply voltage VCC
0
Ta (C)
85
Input inverted voltage VINV
R
VCC=5.5 V
CS, SK, DI
FO
1.2
2.0
D
VINV
(V)
2
3
4
5
6
7
EN
0
DE
0.6
VCC (V)
M
Low supply voltage detection voltage VDET
1. 29
1.0
OM
-40
NO
T
0
RE
C
2.0
-VDET
(V)
0
Ta (C)
85
1.0
0
1. 30
vs. ambient temperature Ta
24
-40
vs. ambient temperature Ta
Ta=25C
CS, SK, DI
VINV
(V)
W
0.5
NE
0
N
Low-level output current IOL
DE
SI
G
1. 25
Rev.5.0_03
-40
0
Ta (C)
85
Low supply voltage release voltage VDET
vs. ambient temperature Ta
2.0
+VDET
(V)
1.0
0
-40
0
Ta (C)
85
Rev.5.0_03
2. 1
AC Characteristics
Maximum operating frequency fMAX.
2. 2
vs. power supply voltage VCC
Write time tPR
vs. power supply voltage VCC
Ta=25C
Ta=25C
10M
4
fMAX. 1M
(Hz)
100k
tPR
(ms)
2
2. 3
2
Write time tPR
2. 4
FO
VCC=3.3 V
tPR
(ms) 4
D
4
0
85
Ta (C)
Write time tPR
OM
VCC=2.7 V
M
vs. ambient temperature Ta
EN
-40
DE
2
6
RE
C
4
2
Write time tPR
6
6
tPR
(ms)
7
vs. ambient temperature Ta
VCC=5.5 V
2. 5
4 5 6
VCC (V)
R
vs. ambient temperature Ta
tPR
(ms)
2 3
1
3 4 5 6
VCC (V)
NE
1
W
10k
DE
SI
G
2.
N
3-WIRE SERIAL E2PROM
S-93C86B
0
85
Ta (C)
-40
2. 6
0
85
Ta (C)
Data output delay time tPD
vs. ambient temperature Ta
VCC=4.5 V
0.3
tPD
(s) 0.2
0.1
-40
0
Ta (C)
85
NO
T
-40
2
25
3-WIRE SERIAL E2PROM
S-93C86B
2. 8
vs. ambient temperature Ta
VCC=2.7 V
VCC=1.8 V
0.6
1.5
tPD
(s) 0.4
tPD
(s) 1.0
0.2
0.5
85
-40
FO
D
DE
EN
M
OM
RE
C
T
NO
26
0
Ta (C)
NE
0
Ta (C)
R
-40
DE
SI
G
vs. ambient temperature Ta
Data output delay time tPD
N
Data output delay time tPD
W
2. 7
Rev.5.0_03
85
3-WIRE SERIAL E2PROM
S-93C86B
Rev.5.0_03
DE
SI
G
1.
N
Product Name Structure
Product name
S-93C86B
D4
I
-
xxxx
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office)
NE
W
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
Operation temperature
I:
40C to 85C
R
Fixed
FO
Product name
S-93C86B: 16 K-bit
D
Packages
DE
2.
Package Name
Drawing Code
Tape
Reel
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
FJ008-D-C-SD
FJ008-D-C-SD
FT008-E-C-SD
FT008-E-C-SD
FJ008-D-R-SD
FJ008-D-R-S1
FT008-E-R-SD
FT008-E-R-S1
NO
T
RE
C
OM
M
8-Pin TSSOP
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
EN
8-Pin SOP (JEDEC)
Package
27
1
4
DE
SI
G
5
NE
W
8
N
5.02±0.2
DE
D
FO
R
0.20±0.05
1.27
NO
T
RE
C
OM
M
EN
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
N
2.0±0.05
ø1.55±0.05
2.1±0.1
FO
R
NE
8.0±0.1
ø2.0±0.05
W
DE
SI
G
0.3±0.05
5
Feed direction
NO
T
RE
C
OM
M
4
8
EN
1
DE
D
6.7±0.1
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
2,000
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
+0.3
5
1
4
R
NE
W
8
DE
SI
G
3.00 -0.2
DE
D
FO
0.17±0.05
EN
0.2±0.1
NO
T
RE
C
OM
M
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
+0.1
8.0±0.1
NE
ø1.55 -0.05
W
DE
SI
G
N
0.3±0.05
FO
R
(4.4)
+0.4
EN
DE
D
6.6 -0.2
8
M
1
4
NO
T
RE
C
OM
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
EN
DE
D
FO
R
NE
W
DE
SI
G
N
1.
M
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
OM
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
RE
C
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
T
14. For more details on the information described herein, contact our sales office.
NO
2.0-2018.01
www.ablicinc.com
工商网监
湘ICP备2023018690号
