S-93L56AR01-I8T1G

Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 1/2/4 K-bit serial E2PROM with a wide operating voltage range. It is organized as 64-word × 16-bit, 128-word × 16-bit, 256-word × 16-bit, respectively. Each is capable of sequential read, at which time addresses are automatically incremented in 16-bit blocks. The instruction code is compatible with the NM93CS46/56/66. Features • Low current consumption Standby: 1.5 µA Max. (VCC = 5.5 V) Operating: 0.8 mA Max. (VCC = 5.5 V) 0.4 mA Max. (VCC = 2.5 V) Read: 1.6 to 5.5 V Write: 1.8 to 5.5 V (WRITE, ERASE) 2.7 to 5.5 V (WRAL, ERAL) • Wide operating voltage range • Sequential read capable • Write disable function when power supply voltage is low • Function to protect against write due to erroneous instruction recognition • Endurance: 107 cycles/word*1 (at +25°C) write capable, 106 cycles/word*1 (at +85°C) *1. For each address (Word: 16 bits) • Data retention: 10 years (after rewriting 106 cycles/word at +85°C) • S-93L46A: 1 K-bit NM93CS46 instruction code compatible • S-93L56A: 2 K-bit NM93CS56 instruction code compatible • S-93L66A: 4 K-bit NM93CS66 instruction code compatible • Lead-free products Packages Package name SNT-8A 8-Pin SOP(JEDEC) 8-Pin TSSOP WLP-7D WLP-7D (Low profile) Drawing code Package PH008-A FJ008-A FT008-A HD007-A HD007-B Tape PH008-A FJ008-D FT008-E HD007-A HD007-B Reel PH008-A FJ008-D FT008-E HD007-A HD007-B Land PH008-A     Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable. Seiko Instruments Inc. 1 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 Pin Assignment SNT-8A Top view CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC TEST GND Table 1 Pin Number Pin Name Function 1 CS Chip select input 2 SK Serial clock input 3 DI Serial data input 4 DO Serial data output 5 GND Ground *1 6 TEST Test 7 NC No connection 8 VCC Power supply *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 1 S-93L46AD0I-I8T1G S-93L56AD0I-I8T1G S-93L66AD0I-I8T1G 8-Pin SOP(JEDEC) Top view CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC TEST GND Table 2 Pin Number Pin Name Function 1 CS Chip select input 2 SK Serial clock input 3 DI Serial data input 4 DO Serial data output 5 GND Ground *1 6 TEST Test 7 NC No connection 8 VCC Power supply *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 2 S-93L46AD0I-J8T1G S-93L56AD0I-J8T1G S-93L66AD0I-J8T1G 2 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 8-Pin SOP(JEDEC) (Rotated) Top view NC VCC CS SK 1 2 3 4 8 7 6 5 TEST GND DO DI Table 3 Pin Number Pin Name Function 1 NC No connection 2 VCC Power supply 3 CS Chip select input 4 SK Serial clock input 5 DI Serial data input 6 DO Serial data output 7 GND Ground 8 TEST*1 Test *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 3 S-93L46AR0I-J8T1G S-93L56AR0I-J8T1G S-93L66AR0I-J8T1G 8-Pin TSSOP Top view CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC TEST GND Table 4 Pin Number Pin Name Function 1 CS Chip select input 2 SK Serial clock input 3 DI Serial data input 4 DO Serial data output 5 GND Ground 6 TEST*1 Test 7 NC No connection 8 VCC Power supply *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 4 S-93L46AD0I-T8T1G S-93L56AD0I-T8T1G S-93L66AD0I-T8T1G Seiko Instruments Inc. 3 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 WLP-7D Bottom view 4 TEST 5 GND 2 DI 6 7 DO SK (1.49 × 1.27 × 0.6 max.) 3 VCC 1 CS Table 5 Pin Number Pin Name Function 1 CS Chip select input 2 DI Serial data input 3 VCC Power supply 4 TEST*1 Test 5 GND Ground 6 DO Serial data output 7 SK Serial clock input *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 5 S-93L66AD0I-H7T1 WLP-7D (Low profile 0.39 mm max.) Bottom view 4 TEST 5 GND 2 DI 6 7 DO SK (1.49 × 1.27 × 0.39 max.) 3 VCC 1 CS Table 6 Pin Number Pin Name Function 1 CS Chip select input 2 DI Serial data input 3 VCC Power supply 4 TEST*1 Test 5 GND Ground 6 DO Serial data output 7 SK Serial clock input *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings. Figure 6 S-93L66AD0I-H7T3 4 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Block Diagram Memory array Address decoder VCC GND Data register DI Mode decode logic CS Clock pulse monitoring circuit Output buffer DO Voltage detector SK Clock generator Figure 7 Instruction Sets 1. S-93L46A Table 7 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 A5 A5 A5 0 1 1 0 5 A4 A4 A4 1 0 1 0 Address 6 A3 A3 A3 x x x x 7 A2 A2 A2 x x x x 8 A1 A1 A1 x x x x 9 A0 A0 A0 x x x x Data 10 to 25 D15 to D0 Output*1 D15 to D0 Input  D15 to D0 Input    *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Don’t care Seiko Instruments Inc. 5 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 2. S-93L56A Table 8 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 x x x 0 1 1 0 5 6 Address 7 8 9 10 11 Rev.3.1_00 Data 12 to 27 D15 to D0 Output*1 D15 to D0 Input  D15 to D0 Input    A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Don’t care 3. S-93L66A Table 9 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit 1 1 1 1 1 1 1 1 Operation Code 2 1 0 1 0 0 0 0 3 0 1 1 0 0 0 0 4 5 6 Address 7 8 9 10 11 Data 12 to 27 D15 to D0 Output*1 D15 to D0 Input  D15 to D0 Input    A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 0 1 1 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Don’t care 6 Seiko Instruments Inc. Rev.3.1_00 Absolute Maximum Ratings LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Table 10 Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VCC VIN VOUT Topr Tstg Ratings −0.3 to +7.0 −0.3 to VCC +0.3 −0.3 to VCC −40 to +85 −65 to +150 Unit V V V °C °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Parameter Power supply voltage Symbol VCC Table 11 Conditions READ/EWDS WRITE/ERASE/EWEN WRAL/ERAL VCC = 4.5 to 5.5 V High level input voltage VIH VCC = 2.7 to 4.5 V VCC = 1.6 to 2.7 V VCC = 4.5 to 5.5 V Low level input voltage VIL VCC = 2.7 to 4.5 V VCC = 1.6 to 2.7 V Min. 1.6 1.8 2.7 2.0 0.8 × VCC 0.8 × VCC 0.0 0.0 0.0 Typ.          Max. 5.5 5.5 5.5 VCC VCC VCC 0.8 0.2 × VCC 0.15 × VCC Unit V V V V V V V V V Pin Capacitance Table 12 Parameter Input Capacitance Output Capacitance Symbol CIN COUT Conditions VIN = 0 V VOUT = 0 V (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Min. Typ. Max. Unit     8 10 pF pF Seiko Instruments Inc. 7 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Endurance Table 13 Parameter Endurance Symbol NW Operating Temperature −40 to +85°C Min. 106 Typ.  Max.  Rev.3.1_00 Unit cycles/word*1 *1. For each address (Word: 16 bits) DC Electrical Characteristics Table 14 Parameter Current consumption (READ) ICC1 DO no load   0.8   0.5   0.4 mA Symbol Conditions VCC = 4.5 to 5.5 V Min. Typ. Max. VCC = 2.5 to 4.5 V Min. Typ. Max. VCC = 1.6 to 2.5 V Min. Typ. Max. Unit Table 15 Parameter Current consumption (WRITE) Symbol Conditions VCC = 4.5 to 5.5 V Min.  Typ.  Max. 2.0 VCC = 1.8 to 4.5 V Min.  Typ.  Max. 1.5 Unit ICC2 DO no load mA Table 16 Parameter Standby current consumption Input leakage current Output leakage current Symbol Conditions CS = GND, DO = Open, Other inputs to VCC or GND VIN = GND to VCC VOUT = GND to VCC IOL = 2.1 mA Low level output voltage VOL IOL = 100 µA IOH = −400 µA High level output voltage VOH IOH = −100 µA IOH = −10 µA Write enable latch data hold voltage VDH Only when write disable mode  2.4   0.1         0.1           0.1     V V V V V VCC = 4.5 to 5.5 V Min.     Typ. Max.  0.1 0.1  1.5 1.0 1.0 0.4 VCC = 2.5 to 4.5 V Min.     Typ. Max.  0.1 0.1  1.5 1.0 1.0  VCC = 1.6 to 2.5 V Min.     Typ. Max.  0.1 0.1  1.5 1.0 1.0  Unit ISB ILI ILO µA µA µA V VCC− 0.3  VCC− 0.2  1.5  VCC− 0.3  VCC− 0.2  1.5  VCC− 0.2  1.5  8 Seiko Instruments Inc. Rev.3.1_00 AC Electrical Characteristics LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Table 17 Measurement Conditions Input pulse voltage Output reference voltage Output load 0.1 × VCC to 0.9 × VCC 0.5 × VCC 100 pF Parameter CS setup time CS hold time CS deselect time Data setup time Data hold time Output delay time Clock frequency*1 SK clock time “L” *1 SK clock time “H” *1 Output disable time Output enable time Table 18 VCC = 4.5 to 5.5 V Symbol Min. Typ. Max. tCSS 0.2 — — tCSH 0 — — tCDS 0.2 — — tDS 0.1 — — tDH 0.1 — — tPD — — 0.4 fSK 0 — 2.0 tSKL 0.1 — — tSKH 0.1 — — tHZ1, tHZ2 0 — 0.15 tSV 0 — 0.15 VCC = 2.5 to 4.5 V Min. Typ. Max. 0.4 — — 0 — — 0.2 — — 0.2 — — 0.2 — — — — 0.8 0 — 1.0 0.25 — — 0.25 — — 0 — 0.5 0 — 0.5 VCC = 1.6 to 2.5 V Unit Min. Typ. Max. 1.0 — — µs 0 — — µs 0.4 — — µs 0.4 — — µs 0.4 — — µs — — 2.0 µs 0 — 0.25 MHz 1.0 — — µs 1.0 — — µs 0 — 1.0 µs 0 — 1.0 µs *1. The clock cycle of the SK clock (frequency: fSK) is 1/fSK µs. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made equal to tSKL(Min.) + tSKH(Min.). Table 19 VCC = 1.8 to 5.5 V Min — Typ. 4.0 Max. 8.0 Parameter Write time Symbol tPR Unit ms Seiko Instruments Inc. 9 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A tCSS CS SK tDS DI Hi-Z*1 tSV Hi-Z tHZ2 tHZ1 tDH tDS tDH tSKH 1/fSK*2 tSKL tCSH tCDS Rev.3.1_00 Valid data Valid data tPD tPD Hi-Z DO (READ) DO Hi-Z (VERIFY) *1. Indicates high impedance. *2. 1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1/fSK) cannot be made equal to tSKL(Min.) + tSKH(Min.). Figure 8 Timing Chart 10 Seiko Instruments Inc. Rev.3.1_00 Operation LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An instruction set is input in the order of start bit, instruction, address, and data. Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS. While a low level is being input to CS, the S-93L46A/56A/66A is in standby mode, so the SK and DI inputs are invalid and no instructions are allowed. Start Bit A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit is not recognized even if the SK pulse is input as long as the DI pin is low. 1. Dummy clock SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks can be adjusted by inserting a 7-bit dummy clock for the S-93L46A and a 5-bit dummy clock for the S-93L56A/66A. 2. Start bit input failure • When the output status of the DO pin is high during the verify period after a write operation, if a high level is input to the DI pin at the rising edge of SK, the S-93L46A/56A/66A recognizes that a start bit has been input. To prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4.1 Verify operation”). • When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the data output from the CPU and the serial memory collide may be generated, preventing successful input of the start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”. Seiko Instruments Inc. 11 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 3. Reading (READ) The READ instruction reads data from a specified address. After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the last input address (A0) has been latched, the output status of the DO pin changes from high impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of SK. 3.1 Sequential read After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically increments the address, and causes the 16-bit data at the next address to be output sequentially. The above method makes it possible to read the data in the whole memory space. The last address (An A1 A0 = 1 1 1) rolls over to the top address (An A1 A0 = 0 0 0). CS SK DI DO 1 2 3 4 5 6 7 8 9 10 11 12 23 24 25 26 27 28 39 40 41 42 43 44 1 0 A5 A4 A3 A2 A1 A0 Hi-Z 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13 Hi -Z ADRINC ADRINC Figure 9 Read Timing (S-93L46A) CS SK DI DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 40 41 42 43 44 45 1 0 A6 A5 A4 A3 A2 A1 A0 X: S-93L56A Hi-Z A7: S-93L66A 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13 Hi -Z ADRINC ADRINC Figure 10 Read Timing (S-93L56A, S-93L66A) 12 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 4. Writing (WRITE, ERASE, WRAL, ERAL) A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and chip erase (ERAL). A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write period, so do not input an instruction. Input an instruction while the output status of the DO pin is high or high impedance (Hi-Z). A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable (EWDS)”). 4.1 Verify operation A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4 ms), so if the completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to confirm the status of a write operation is called a verify operation. (1) Operation After the write operation has started (CS = low), the status of the write operation can be verified by confirming the output status of the DO pin by inputting a high level to CS again. This sequence is called a verify operation, and the period that a high level is input to the CS pin after the write operation has started is called the verify operation period. The relationship between the output status of the DO pin and the write operation during the verify operation period is as follows. • DO pin = low: Writing in progress (busy) • DO pin = high: Writing completed (ready) (2) Operation example There are two methods to perform a verify operation: Waiting for a change in the output status of the DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing it again to verify the output status of the DO pin. The latter method allows the CPU to perform other processing during the wait period, allowing an efficient system to be designed. Caution 1. Input a low level to the DI pin during a verify operation. 2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is high, the S-93L46A/56A/66A latches the instruction assuming that a start bit has been input. In this case, note that the DO pin immediately enters a high-impedance (Hi-Z) state. Seiko Instruments Inc. 13 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 4.2 Writing data (WRITE) To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address, and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS Standby CS SK DI DO 1 2 0 1 3 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 D15 25 D0 Verify Hi-Z tSV Busy Ready tHZ1 tPR Hi-Z Figure 11 Data Write Timing (S-93L46A) tCDS CS SK DI DO 1 2 1 3 4 5 A6 6 A5 7 A4 Hi-Z x : S-93L56A A7: S-93L66A 8 A3 9 A2 10 A1 11 A0 12 D15 27 D0 Verify Standby 0 tSV Busy Ready tHZ1 tPR Hi-Z Figure 12 Data Write Timing (S-93L56A, S-93L66A) 14 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 4.3 Erasing data (ERASE) To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input the ERASE instruction and address following the start bit. There is no need to input data. The data erase operation starts when CS goes low. If the clocks have been input more than the specified number, the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS Standby CS SK DI DO 1 2 1 1 3 4 A5 Hi-Z 5 A4 6 A3 7 A2 8 A1 9 A0 tSV Verify Busy tHZ1 Ready tPR Hi-Z Figure 13 Data Erase Timing (S-93L46A) tCDS CS SK DI DO 1 2 1 3 1 4 5 A6 6 A5 7 A4 Hi-Z x : S-93L56A A7: S-93L66A 8 A3 9 A2 10 A1 11 A0 Verify Standby tSV Busy Ready tHZ1 Hi-Z tPR Figure 14 Data Erase Timing (S-93L56A, S-93L66A) Seiko Instruments Inc. 15 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 4.4 Writing to chip (WRAL) To write the same 16-bit data to the entire memory address space, change CS to high, and then input the WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. tCDS CS SK DI DO 1 2 0 3 0 0 Hi-Z 4 5 1 4Xs 6 7 8 9 10 D15 25 D0 Verify Standby tSV Busy Ready tHZ1 tPR Hi-Z Figure 15 Chip Write Timing (S-93L46A) tCDS CS SK DI DO 1 2 0 0 3 0 Hi-Z 4 1 6Xs 5 6 7 8 9 10 11 12 D15 27 D0 Verify Standby tSV Busy Ready tHZ1 tPR Hi-Z Figure 16 Chip Write Timing (S-93L56A, S-93L66A) 16 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 4.5 Erasing chip (ERAL) To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to input data. The chips erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”. CS SK DI DO tPR 1 2 0 3 0 4 1 0 4Xs tSV Busy Ready Hi-Z tHZ1 5 6 7 8 9 Verify Standby tCDS Figure 17 Chip Erase Timing (S-93L46A) CS SK DI DO 1 2 0 3 0 4 1 0 6Xs 5 6 7 8 9 10 tCDS 11 Verify Standby tSV Busy tPR Ready tHZ1 Hi-Z Figure 18 Chip Erase Timing (S-93L56A, S-93L66A) Seiko Instruments Inc. 17 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 5. Write enable (EWEN) and write disable (EWDS) Rev.3.1_00 The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is enabled is called the program enable mode. The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is disabled is called the program disable mode. After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address (optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been input. CS SK DI 1 0 2 3 0 4 5 6 7 8 9 Standby 11 = EWEN 00 = EWDS 4Xs Figure 19 Write Enable/Disable Timing (S-93L46A) CS SK DI 1 2 0 3 0 4 5 6 7 8 9 10 11 Standby 11 = EWEN 00 = EWDS 6Xs Figure 20 Write Enable/Disable Timing (S-93L56A, S-93L66A) (1) Recommendation for write operation disable instruction It is recommended to implement a design that prevents an incorrect write operation when a write instruction is erroneously recognized by executing the write operation disable instruction when executing instructions other than write instruction, and immediately after power-on and before power off. 18 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Write Disable Function when Power Supply Voltage is Low The S-93L46A/56A/66A provides a built-in detector to detect a low power supply voltage and disable writing. When the power supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The detection voltage and the release voltage are 1.4 V typ.(refer to Figure 21). Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed. When the power supply voltage drops during a write operation, the data being written to an address at that time is not guaranteed. Power supply Detection voltage (−VDET) 1.4 V Typ. Release voltage (+VDET) 1.4 V Typ. Write instruction cancelled Write disable state (EWDS) automatically set Figure 21 Operation when Power Supply Voltage is Low Seiko Instruments Inc. 19 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 Function to Protect Against Write due to Erroneous Instruction Recognition The S-93L46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation (WRITE, ERASE, WRAL, or ERAL) is detected. Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE) Example of S-93L46A CS 1 SK DI Input EWDS instruction Erroneous recognition as ERASE instruction due to noise pulse 1 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 2 3 4 5 6 7 8 9 Noise pulse 1 1 10 In products that do not include a clock pulse monitoring circuit, FFFF is mistakenly written on address 00h. However the S-93L46A detects the overcount and cancels the instruction without performing a write operation. Figure 22 Example of Clock Pulse Monitoring Circuit Operation 20 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 3-Wire Interface (Direct Connection between DI and DO) There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin. When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins of the S-93L46A/56A/66A via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input to the DI pin (refer to “Figure 23 Connection of 3-Wire Interface”). CPU S-93L46A/56A/66A SIO DI DO R: 10 kΩ to 100 kΩ Figure 23 Connection of 3-Wire Interface I/O Pins 1. Connection of input pins All the input pins of the S-93L46A/56A/66A employ a CMOS structure, so design the equipment so that high impedance will not be input while the S-93L46A/56A/66A is operating. Especially, deselect the CS input (a low level) when turning on/off power and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ pull-down resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin. 2. Input and output pin equivalent circuits The following shows the equivalent circuits of input pins of the S-93L46A/56A/66A. None of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating status. Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected from the internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected. Seiko Instruments Inc. 21 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 2.1 Input pin Rev.3.1_00 CS Figure 24 CS Pin SK, DI Figure 25 SK, DI Pin TEST Figure 26 TEST Pin 22 Seiko Instruments Inc. Rev.3.1_00 2.2 Output pin LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Vcc DO Figure 27 DO Pin 3. Input pin noise elimination time The S-93L46A/56A/66A include a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated. Note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds VIH/VIL. Precaution • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. Precautions for WLP package • The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of the handing of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, and needs to be kept out of contact with the external potential. • In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it may affect the characteristic of a device when exposed a device in the bottom of a high light source. Seiko Instruments Inc. 23 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Characteristics 1. DC Characteristics 1.1 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC = 5.5 V fSK = 2 MHz DATA = 0101 0.4 ICC1 (mA) 0.2 Rev.3.1_00 1.2 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC = 3.3 V fSK = 500 kHz DATA = 0101 0.4 ICC1 (mA) 0.2 0 −40 0 Ta (°C) 85 0 −40 0 Ta (°C) 85 1.3 Current consumption (READ) ICC1 vs. ambient temperature Ta VCC = 1.8 V fSK = 10 kHz DATA = 0101 0.4 ICC1 (mA) 0.2 1.4 Current consumption (READ) ICC1 vs. power supply voltage VCC Ta = 25°C fSK = 1 MHz, 500 kHz DATA = 0101 1 MHz 0.4 ICC1 (mA) 0.2 0 −40 0 Ta (°C) 85 0 2 3 ∼ 500 kHz 4 5 6 7 VCC (V) 1.5 Current consumption (READ) ICC1 vs. power supply voltage VCC Ta = 25°C fSK = 100 kHz, 10 kHz DATA = 0101 1.6 Current consumption (READ) ICC1 vs. Clock frequency fSK VCC = 5.0 V Ta = 25°C 0.4 0.4 ICC1 (mA) 0.2 100 kHz ICC1 (mA) 0.2 10 kHz 0 2 3 4 56 7 VCC (V) 0 10 k 100 k 1 M 2M 10M fSK (Hz) 24 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 1.7 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC = 5.5 V 1.0 ICC2 (mA) 0.5 1.8 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC = 3.3 V 1.0 ICC2 (mA) 0.5 0 −40 0 Ta (°C) 85 0 −40 0 85 Ta (°C) 1.9 Current consumption (WRITE) ICC2 vs. ambient temperature Ta VCC = 2.7 V 1.0 ICC2 (mA) 0.5 1.10 Current consumption (WRITE) ICC2 vs. power supply voltage VCC Ta = 25°C 1.0 ICC2 (mA) 0.5 0 −40 0 Ta (°C) 85 0 2 3 4 56 7 VCC (V) 1.11 Current consumption in standby mode ISB vs. ambient temperature Ta VCC = 5.5 V CS = GND 1.0 ISB (µA) 0.5 1.12 Current consumption in standby mode ISB vs. power supply voltage VCC Ta = 25°C CS = GND ISB (µA) 1.0 0.5 0 −40 0 0 85 Ta (°C) 2 3 4 56 VCC (V) 7 Seiko Instruments Inc. 25 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 1.13 Input leakage current ILI vs. ambient temperature Ta VCC = 5.5 V CS, SK, DI, TEST = 0 V 1.0 ILI (µA) 0.5 1.14 Input leakage current ILI vs. ambient temperature Ta VCC = 5.5 V CS, SK, DI, TEST = 5.5 V 1.0 ILI (µA) 0.5 0 0 −40 0 85 −40 0 Ta (°C) 85 1.15 Output leakage current ILO vs. ambient temperature Ta VCC = 5.5 V DO = 0 V 1.0 ILO (µA) 0.5 1.16 Output leakage current ILO vs. ambient temperature Ta VCC = 5.5 V DO = 5.5 V 1.0 ILO (µA) 0.5 0 −40 0 Ta (°C) 85 0 −40 0 85 1.17 High-level output voltage VOH vs. ambient temperature Ta VCC = 4.5 V IOH = −400 µA Ta (°C) 1.18 High-level output voltage VOH vs. ambient temperature Ta VCC = 2.7 V IOH = −100 µA 4.6 VOH (V) 4.4 4.2 2.7 VOH (V) 2.6 2.5 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 26 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 1.19 High-level output voltage VOH vs. ambient temperature Ta VCC = 2.5 V IOH = −100 µA 1.20 High-level output voltage VOH vs. ambient temperature Ta VCC = 1.8 V IOH = −10 µA 2.5 VOH (V) 2.4 2.3 1.9 VOH (V) 1.8 1.7 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 1.21 Low-level output voltage VOL vs. ambient temperature Ta VCC = 4.5 V IOL = 2.1 mA 1.22 Low-level output voltage VOL vs. ambient temperature Ta VCC = 1.8 V IOL = 100 µA 0.3 VOL (V) 0.2 0.1 0.03 VOL 0.02 (V) 0.01 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 1.23 High-level output current IOH vs. ambient temperature Ta VCC = 4.5 V VOH = 2.4 V −20.0 IOH (mA) −10.0 1.24 High-level output current IOH vs. ambient temperature Ta VCC = 2.7 V VOH = 2.4 V IOH (mA) −2 −1 0 −40 0 Ta (°C) 85 0 −40 0 85 Ta (°C) Seiko Instruments Inc. 27 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 1.25 High-level output current IOH vs. ambient temperature Ta VCC = 2.5 V VOH = 2.2 V −2 IOH (mA) −1 1.26 High-level output current IOH vs. ambient temperature Ta VCC = 1.8 V VOH = 1.6 V −1.0 IOH (mA) −0.5 0 0 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 1.27 Low-level output current IOL vs. ambient temperature Ta VCC = 4.5 V VOL = 0.4 V 20 IOL (mA) 10 1.28 Low-level output current IOL vs. ambient temperature Ta VCC = 1.8 V VOL = 0.1 V 1.0 IOL (mA) 0.5 0 −40 0 85 Ta (°C) 0 −40 0 85 Ta (°C) 1.29 Input inverted voltage VINV vs. power supply voltage VCC Ta = 25°C CS, SK, DI 3.0 VINV (V) 1.5 1.30 Input inverted voltage VINV vs. ambient temperature Ta VCC = 5.0 V CS, SK, DI 3.0 VINV (V) 2.0 0 1 2 3 45 67 0 VCC (V) −40 0 Ta (°C) 85 28 Seiko Instruments Inc. Rev.3.1_00 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 1.31 Low supply voltage detection voltage −VDET vs. ambient temperature Ta 1.32 Low supply voltage release voltage +VDET vs. ambient temperature Ta 2.0 -VDET (V) 1.0 2.0 +VDET (V) 1.0 0 -40 0 Ta (°C) 85 0 -40 0 Ta (°C) 85 2. AC Characteristics 2.1 Maximum operating frequency fMAX. vs. power supply voltage VCC Ta = 25°C 2M 1M 100k 10k 1 2 3 4 5 2.2 Write time tPR vs. power supply voltage VCC Ta = 25°C 4 tPR (ms) 2 fMAX. (Hz) 1 2 3 4 56 7 VCC (V) VCC (V) 2.3 Write time tPR vs. ambient temperature Ta VCC = 5.0 V tPR (ms) 6 4 2 2.4 Write time tPR vs. ambient temperature Ta VCC = 3.0 V tPR (ms) 6 4 2 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 Seiko Instruments Inc. 29 LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A Rev.3.1_00 2.5 Write time tPR vs. ambient temperature Ta VCC = 2.7 V tPR (ms) 6 4 2 2.6 Data output delay time tPD vs. ambient temperature Ta VCC = 4.5 V tPD (µs) 0.3 0.2 0.1 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 2.7 Data output delay time tPD vs. ambient temperature Ta VCC = 2.7 V tPD (µs) 0.6 0.4 0.2 2.8 Data output delay time tPD vs. ambient temperature Ta VCC = 1.8 V tPD (µs) 1.5 1.0 0.5 −40 0 Ta (°C) 85 −40 0 Ta (°C) 85 30 Seiko Instruments Inc. Rev.3.1_00 Product Code Structure LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L46A/56A/66A 1. SNT-8A, 8-Pin SOP(JEDEC), 8-Pin TSSOP package S-93LxxA x 0I - xxxx G Package name (abbreviation) and IC packing specifications I8T1: SNT-8A, Tape J8T1: 8-Pin SOP(JEDEC), Tape T8T1: 8-Pin TSSOP, Tape Fixed Pin assignment D: SNT-8A 8-Pin SOP(JEDEC) 8-Pin TSSOP R: 8-Pin SOP(JEDEC) (Rotated) Product name S-93L46A : 1 K-bit S-93L56A : 2 K-bit S-93L66A : 4 K-bit 2. WLP-7D package S-93L66A D0I - H7Tx Package name (abbreviation) and IC packing specifications H7T1 : WLP-7D, Tape H7T3 : WLP-7D (Low profile type), Tape Fixed Product name S-93L66A : 4k-bit Seiko Instruments Inc. 31 1 .97±0.03 8 7 6 5 1 0.5 2 3 4 0.08 -0.02 +0.05 0.48±0.02 0.2±0.05 No. PH008-A-P-SD-2.0 TITLE No. SCALE UNIT SNT-8A-A-PKG Dimensions PH008-A-P-SD-2.0 mm Seiko Instruments Inc. ø1.5 -0 +0.1 2.0±0.05 4.0±0.1 0.25±0.05 5° 2.25±0.05 ø0.5±0.1 4.0±0.1 0.65±0.05 4 321 5 6 78 Feed direction No. PH008-A-C-SD-1.0 TITLE No. SCALE UNIT SNT-8A-A-Carrier Tape PH008-A-C-SD-1.0 mm Seiko Instruments Inc. 12.5max. Enlarged drawing in the central part ø13±0.2 9.0±0.3 (60°) (60°) No. PH008-A-R-SD-1.0 TITLE No. SCALE UNIT mm SNT-8A-A-Reel PH008-A-R-SD-1.0 QTY. 5,000 Seiko Instruments Inc. 0.52 2.01 0.52 0.3 0.2 0.3 0.2 0.3 0.2 0.3 Caution Making the wire pattern under the package is possible. However, note that the package may be upraised due to the thickness made by the silk screen printing and of a solder resist on the pattern because this package does not have the standoff. No. PH008-A-L-SD-3.0 TITLE No. SCALE UNIT SNT-8A-A-Land Recommendation PH008-A-L-SD-3.0 mm Seiko Instruments Inc. 5.02±0.2 8 5 1 4 0.20±0.05 1.27 0.4±0.05 No. FJ008-A-P-SD-2.1 TITLE No. SCALE UNIT SOP8J-D-PKG Dimensions FJ008-A-P-SD-2.1 mm Seiko Instruments Inc. 2.0±0.05 ø1.55±0.05 4.0±0.1(10 pitches:40.0±0.2) 0.3±0.05 ø2.0±0.05 5°max. 8.0±0.1 2.1±0.1 6.7±0.1 1 8 4 5 Feed direction No. FJ008-D-C-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Carrier Tape FJ008-D-C-SD-1.1 mm Seiko Instruments Inc. 60° 2±0.5 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 13.5±0.5 No. FJ008-D-R-SD-1.1 TITLE No. SCALE UNIT SOP8J-D-Reel FJ008-D-R-SD-1.1 QTY. mm 2,000 Seiko Instruments Inc. 3.00 -0.2 8 5 +0.3 1 4 0.17±0.05 0.2±0.1 0.65 No. FT008-A-P-SD-1.1 TITLE No. SCALE UNIT TSSOP8-E-PKG Dimensions FT008-A-P-SD-1.1 mm Seiko Instruments Inc. 4.0±0.1 2.0±0.05 ø1.55±0.05 0.3±0.05 8.0±0.1 ø1.55 -0.05 +0.1 (4.4) 6.6 -0.2 +0.4 1 4 8 5 Feed direction No. FT008-E-C-SD-1.0 TITLE No. SCALE UNIT TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0 mm Seiko Instruments Inc. 13.4±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.5 17.5±1.0 No. FT008-E-R-SD-1.0 TITLE No. SCALE UNIT mm TSSOP8-E-Reel FT008-E-R-SD-1.0 QTY. 3,000 Seiko Instruments Inc. 1.49±0.02 1.27±0.02 0.6max. 0.4±0.02 S 0.06 S ø0.25±0.02 0.6max. 0.15±0.03 0.5 0.5 7-(ø0.25) 4 ø0.05 M S A B 0.43 3 2 1 7 5 0.43 6 0.5 No. HD007-A-P-SD-1.0 TITLE No. SCALE UNIT WLP-7D-A-PKG Dimensions HD007-A-P-SD-1.0 Seiko Instruments Inc. ø1.5 -0 +0.1 2.0±0.05 4.0±0.1 0.18±0.05 ø0.5±0.05 2.0±0.1 4.0±0.1 Count mark(R0.3,Depth 0.2) (Every 10 pockets) 0.75±0.05 1.88 1.1 0.7 0.9 1.58±0.05 7 1 3 4 6 5 Feed direction No. HD007-A-C-SD-2.0 TITLE No. SCALE UNIT WLP-7D-A-C a r r i e r T a p e HD007-A-C-SD-2.0 mm Seiko Instruments Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 No. HD007-A-R-SD-1.0 TITLE No. SCALE UNIT WLP-7D-A-Reel HD007-A-R-SD-1.0 QTY. mm 3,000 Seiko Instruments Inc. 1.49±0.02 1.27±0.02 0.265±0.025 0.39max. S 0.04 S 0.39max. ø0.25±0.02 0.08±0.02 0.5 0.5 7-(ø0.25) 4 ø0.05 M S A B 0.43 3 2 1 7 5 0.43 6 0.5 No. HD007-B-P-SD-1.0 TITLE No. SCALE UNIT WLP-7D-B-PKG Dimensions HD007-B-P-SD-1.0 Seiko Instruments Inc. ø1.5 -0 +0.1 2.0±0.05 4.0±0.1 0.18±0.05 ø0.5±0.05 2.0±0.1 4.0±0.1 0.55±0.05 1.66 0.7 0.5 1.36±0.05 3 4 5 1 7 6 Feed direction No. HD007-B-C-SD-1.0 TITLE No. SCALE UNIT WLP-7D-B-C a r r i e r T a p e HD007-B-C-SD-1.0 mm Seiko Instruments Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 No. HD007-B-R-SD-1.0 TITLE No. SCALE UNIT WLP-7D-B-Reel HD007-B-R-SD-1.0 QTY. mm 3,000 Seiko Instruments Inc. • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.