Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM
S-93L76A
The S-93L76A is a low voltage operating, high speed, low current consumption, 8 K-bit serial E2PROM with a wide operating voltage range. It is organized as 512-word × 16-bit respectively. Each is capable of sequential read, at which time addresses are automatically incremented in 16-bit blocks.
Features
• Low current consumption Standby: 2.0 µA Max. (VCC = 5.5 V) Operating: 0.8 mA Max. (VCC = 5.5 V) 0.4 mA Max. (VCC = 2.5 V) Read: 1.6 to 5.5 V Write: 1.8 to 5.5 V (WRITE, ERASE) 2.7 to 5.5 V (WRAL, ERAL)
• Wide operating voltage range
• Sequential read capable • Write disable function when power supply voltage is low • Endurance: 107 cycles/word* (at +25°C) write capable, 106 cycles/word* (at +85°C) * For each address (Word: 16 bits) • Data retention: 10 years (after rewriting 106 cycles/word at +85°C) • S-93L76A: 8 K-bit • Lead-free products
Packages
Package name SNT-8A 8-Pin SOP(JEDEC) 8-Pin TSSOP Package PH008-A FJ008-A FT008-A Drawing code Tape Reel PH008-A PH008-A FJ008-D FJ008-D FT008-E FT008-E Land PH008-A
Caution
This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable.
Seiko Instruments Inc.
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
Pin Assignment
SNT-8A Top view
NC VCC SK CS 1 2 3 4 8 7 6 5 GND TEST DI DO
Table 1 Pin Number Pin Name Function 1 NC No connection 2 VCC Power supply 3 SK Serial clock input 4 CS Chip select input 5 DO Serial data output 6 DI Serial data input Test 7 TEST*1 8 GND Ground *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings.
Figure 1 S-93L76AD0I-I8T1G
8-Pin SOP(JEDEC) Top view
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC TEST GND
Table 2 Pin Number Pin Name Function 1 CS Chip select input 2 SK Serial clock input 3 DI Serial data input 4 DO Serial data output 5 GND Ground *1 6 TEST Test 7 NC No connection 8 VCC Power supply *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings.
Figure 2 S-93L76AD0I-J8T1G
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Seiko Instruments Inc.
Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
8-Pin TSSOP Top view
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC TEST GND
Table 3 Pin Number Pin Name Function 1 CS Chip select input 2 SK Serial clock input 3 DI Serial data input 4 DO Serial data output 5 GND Ground *1 6 TEST Test 7 NC No connection 8 VCC Power supply *1. Connect to GND or VCC. Even if this pin is not connected, performance is not affected so long as the absolute maximum rating is not exceeded. Remark See Dimensions for details of the package drawings.
Figure 3 S-93L76AD0I-T8T1G
Seiko Instruments Inc.
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
Block Diagram
Memory array Address decoder VCC GND
Data register DI Mode decode logic
Output buffer
DO
CS
SK
Clock generator
Voltage detector
Figure 4
Instruction Sets
Table 4 Instruction SK input clock READ (Read data) WRITE (Write data) ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) Start Bit Operation Code 1 2 3 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 4 x x x 0 1 1 0 5 6 7 Address 8 9 10 11 12 13 Data 14 to 29
A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input A8 A7 A6 A5 A4 A3 A2 A1 A0 1 x x x x x x x x D15 to D0 Input 0 x x x x x x x x 1 x x x x x x x x 0 x x x x x x x x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter
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Rev.2.2_00 Absolute Maximum Ratings
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Table 5 Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VCC VIN VOUT Topr Tstg Ratings −0.3 to +7.0 −0.3 to VCC +0.3 −0.3 to VCC −40 to +85 −65 to +150 Unit V V V °C °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 6 Parameter Power supply voltage Symbol VCC Conditions READ / EWDS WRITE / ERASE / EWEN WRAL / ERAL VCC = 4.5 to 5.5 V High level input voltage VIH VCC = 2.7 to 4.5 V VCC = 1.6 to 2.7 V VCC = 4.5 to 5.5 V Low level input voltage VIL VCC = 2.7 to 4.5 V VCC = 1.6 to 2.7 V Min. 1.6 1.8 2.7 2.0 0.8 × VCC 0.8 × VCC 0.0 0.0 0.0 Typ. Max. 5.5 5.5 5.5 VCC VCC VCC 0.8 0.2 × VCC 0.15 × VCC V V V V V V V Unit
Pin Capacitance
Table 7 Parameter Input Capacitance Output Capacitance Symbol CIN COUT Conditions VIN = 0 V VOUT = 0 V (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Min. Typ. Max. Unit 8 10 pF pF
Endurance
Table 8 Parameter Endurance Symbol NW Operation Temperature −40 to +85°C Min. 106 Typ. Max. Unit cycles/word*
* For each address (Word: 16 bits)
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A DC Electrical Characteristics
Table 9 Parameter Current consumption (READ) Symbol Conditions ICC1
Rev.2.2_00
VCC = 4.5 to 5.5 V VCC = 2.5 to 4.5 V VCC = 1.6 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. DO no load 0.8 0.5 0.4 mA Table 10
Parameter Current consumption (WRITE)
Symbol Conditions ICC2 DO no load
VCC = 4.5 to 5.5 V VCC = 1.8 to 4.5 V Min. Typ. Max. Min. Typ. Max. 2.0 1.5
Unit mA
Table 11 Parameter Standby current consumption Input leakage current Output leakage current Low level output voltage High level output voltage Write enable latch data hold voltage Symbol ISB ILI ILO VOL VOH Conditions CS = GND, DO = Open, Other inputs to VCC or GND VIN = GND to VCC VOUT = GND to VCC IOL = 2.1 mA IOL = 100 µA IOH = −400 µA IOH = −100 µA IOH = −10 µA Only when write disable mode VCC = 4.5 to 5.5 V VCC = 2.5 to 4.5 V VCC = 1.6 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.4 VCC− 0.3 VCC− 0.2 1.5 2.0 0.1 1.0 0.1 1.0 2.0 0.1 1.0 0.1 1.0 2.0 µA 0.1 1.0 µA 0.1 1.0 µA 0.1 V V V V V V
0.4 0.1 VCC− 0.3 VCC− 0.2 1.5
0.1 VCC− 0.2 1.5
VDH
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Rev.2.2_00 AC Electrical Characteristics
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Table 12 Measurement Conditions Input pulse voltage Output reference voltage Output load 0.1 × VCC to 0.9 × VCC 0.5 × VCC 100 pF
Table 13 Parameter CS setup time CS hold time CS deselect time Data setup time Data hold time Output delay time Clock frequency Clock pulse width Output disable time Output enable time Symbol tCSS tCSH tCDS tDS tDH tPD fSK tSKL, tSKH tHZ1, tHZ2 tSW VCC = 4.5 to 5.5 V VCC = 2.5 to 4.5 V VCC = 1.6 to 2.5 V Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 0.2 0 0.2 0.1 0.1 — 0 0.1 0 0 — — — — — — — — — — — 0.4 — 0 — 0.2 — 0.2 — 0.2 0.4 — 2.0 0 — 0.25 0.15 0 0.15 0 — — — — — — — — — — — — — — — 0.8 1.0 — 0.5 0.5 1.0 0 0.4 0.4 0.4 — 0 1.0 0 0 — — — — — — — — — — — µs — µs — µs — µs — µs 2.0 µs 0.25 MHz — µs 1.0 µs 1.0 µs
Table 14 Parameter Write time
tCSS CS tSKH SK tDS DI Hi-Z tSV Hi-Z tHZ2 tHZ1 Hi-Z tDH tDS tDH
Symbol tPR
Min.
VCC = 1.8 to 5.5 V Typ. Max. 4.0 10.0
Unit ms
tCDS
tSKL
tCSH
Valid data tPD
Valid data tPD Hi-Z
DO (READ) DO
(VERIFY)
Figure 5 Timing Chart
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A Operation
Rev.2.2_00
All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the period of tCDS in between instructions. “L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.
1. Reading (READ) The READ instruction is used to read the data at a specified address. When this instruction is executed, the address A0 is input at the rising edge of SK and the DO pin, which has been in a highimpedance (Hi-Z) state, outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK. If SK is output after the 16-bit data of the specified address has been output, the address is automatically incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at “H”, the data of the entire memory space can be read. When the address is incremented from the last address (A8 … A1 A0 = 1 … 1 1), it returns to the first address (A8 … A1 A0 = 0 … 0 0).
CS
SK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
26 27 28 29 30 31 32
42 43 44 45 46 47 48
DI
1
1
0
X A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z Hi-Z
DO
0 D15 D14 D13
D2 D1 D0 D15 D14 D13 A8A7A6A5A4A3A2A1A0+1
D2 D1 D0 D15 D14 D13 A8A7A6A5A4A3A2A1A0+2
Figure 6 Read Timing
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Seiko Instruments Inc.
Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
2. Writing (WRITE, ERASE, WRAL, ERAL) Write instructions (WRITE, ERASE, WRAL, and ERAL) are used to start writing data to the non-volatile memory by making CS “L” after the specified number of clocks has been input. The write operation is completed within the write time tPR (10 ms) no matter which write instruction is used. The typical write time is less than half 10 ms. If the end of the write operation is known, therefore, the write cycle can be minimized. To ascertain the end of a write operation, make CS “L” to start the write operation and then make CS “H” again to check the status of the DO output pin. This series of operations is called a verify operation. If DO outputs “L” during the verify operation period in which CS is “H”, it indicates that a write operation is in progress. If DO outputs “H”, it indicates that the write operation is finished. The verify operation can be executed as many times as required. This operation can be executed in two ways. One is detecting the positive transition of DO output from “L” to “H” while holding CS at “H”. The other is detecting the positive transition of DO output from “L” to “H” by making CS “H” once and checking DO output, and then returning CS to “L”. During the write period, SK and DI are invalid. Do not input any instructions during this period. Input an instruction while the DO pin is outputting “H” or is in a high-impedance state. Even while the DO pin is outputing “H”, DO immediately goes into a high-impedance (Hi-Z) state if “H” of DI (start bit) is input at the rising edge of SK. Keep DI “L” during the verify operation period. 2.1 Writing data (WRITE) This instruction is used to write 16-bit data to a specified address. After making CS “H”, input a start bit, the WRITE instruction, an address, and 16-bit data. If data of more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16 bits input last are the valid data. The write operation is started when CS is made “L”. It is not necessary to set data to “1” before it is written.
tCDS CS SK DI DO 1 2 0 3 1 4 X 5 A8 6 A7 7 A6 Hi-Z 8 A5 9 A4 10 A3 11 A2 12 A1 13 14 29 D0 tSV Busy tPR tHZ1 Ready Hi-Z Verify Stand by
A0 D15
Figure 7 Data Write Timing
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
2.2 Erasing data (ERASE) This instruction is used to erase specified 16-bit data. All the 16 bits of the data are “1”. After making CS “H”, input a start bit, the ERASE instruction, and an address. It is not necessary to input data. The data erase operation is started when CS is made “L”.
tCDS CS SK DI DO 1 2 1 3 1 4 X 5 A8 6 A7 7 A6 Hi-Z 8 A5 9 A4 10 A3 11 A2 12 A1 13 A0 tSV Busy tPR tHZ1 Ready Hi-Z Verify Stand by
Figure 8 Data Erase Timing 2.3 Writing to chip (WRAL) This instruction is used to write the same 16-bit data to the entire address space of the memory. After making CS “H”, input a start bit, the WRAL instruction, an address, and 16-bit data. Any address may be input. If data of more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16-bit data input last is the valid data. The write operation is started when CS is made “L”. It is not necessary to set the data to “1” before it is written.
tCDS CS SK DI DO 1 2 0 3 0 4 0 5 1 Hi-Z 8Xs 6 7 8 9 10 11 12 13 14 D15 29 D0 tSV Busy tPR tHZ1 Ready Hi-Z Verify Stand by
Figure 9 Chip Write Timing 2.4 Erasing chip (ERAL) This instruction is used to erase the data of the entire address space of the memory. All the data is “1”. After making CS “H”, input a start bit, the ERAL instruction, and an address. Any address may be input. It is not necessary to input data. The chip erase operation is started when CS is made “L”.
tCDS Verify 1 2 0 3 0 4 1 5 0 6 7 8 9 10 8Xs 11 12 13 tSV Busy tPR tHZ1 Ready Stand by
CS SK DI DO
Hi-Z
Hi-Z
Figure 10 Chip Erase Timing
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Seiko Instruments Inc.
Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
3. Write enable (EWEN) and write disable (EWDS) The EWEN instruction is used to enable a write operation. The status in which a write operation is enabled is called the program-enabled mode. The EWDS instruction is used to disable a write operation. The status in which a write operation is disabled is called the program-disabled mode. The write operation is disabled upon power application and detection of a low supply voltage. To prevent an unexpected write operation due to external noise or a CPU malfunctions, it should be kept in write disable mode except when performing write operations, after power-on and before shutdown.
CS SK DI 1 2 0 3 0 11=EWEN 00=EWDS 8Xs 4 5 6 7 8 9 10 11 12 13 Stand by
Figure 11 Write Enable/Disable Timing
Start Bit
A start bit is recognized by latching the high level of DI at the rising edge of SK after changing CS to high (start bit recognition). A write operation begins by inputting the write instruction and setting CS to low. Subsequently, by setting CS to high again, the DO pin outputs a low level if the write operation is still in progress and a high level if the write operation is complete (verify operation). Therefore, only after a write operation, in order to input the next command, CS is set to high, which switches the DO pin from a highimpedance state (Hi-Z) to a data output state. However, if start bit is recognized, the DO pin returns to the high-impedance state (refer to Figure 5 Timing Chart). Make sure that data output from the CPU does not interfere with the data output from the serial memory IC when configuring a 3 -wire interface by connecting the DI input pin and DO output pin, as such interference may cause a start bit fetch problem. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
Seiko Instruments Inc.
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A Write Disable Function when Power Supply Voltage is Low
Rev.2.2_00
The S-93L76A provides a built-in detector to detect a low power supply voltage and disable writing. When the power supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The detection voltage and the release voltage are 1.4 V typ. (refer to Figure 12). Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed. When the power supply voltage drops during a write operation, the data being written to an address at that time is not guaranteed.
Power supply voltage Detection voltage (−VDET) 1.4 V Typ. Release voltage (+VDET) 1.4 V Typ.
Write instruction cancelled Write disable state (EWDS) automatically set
Figure 12 Operation when Power Supply Voltage is Low
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Seiko Instruments Inc.
Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin. When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins of the S-93L76A via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input to the DI pin (refer to Figure 13).
CPU
S-93L76A
SIO
DI DO R: 10 kΩ to 100 kΩ
Figure 13 Connection of 3-Wire Interface
I/O Pins
1. Connection of input pins
All the input pins of the S-93L76A employ a CMOS structure, so design the equipment so that high impedance will not be input while the S-93L76A is operating. Especially, deselect the CS input (a low level) when turning on/off power and during standby. When the CS pin is deselected (a low level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ pull-down resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin.
2. Input and output pin equivalent circuits
The following shows the equivalent circuits of input pins of the S-93L76A. None of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating status. Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected from the internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected.
Seiko Instruments Inc.
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
2.1 Input pin
Rev.2.2_00
CS
Figure 14 CS Pin
SK, DI
Figure 15 SK, DI Pin
TEST
Figure 16 TEST Pin
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Seiko Instruments Inc.
Rev.2.2_00
2.2 Output pin
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Vcc
DO
Figure 17 DO Pin 3. Input pin noise elimination time
The S-93L76A includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated. Note, therefore, that noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds VIH/VIL.
Precaution
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ● SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A Characteristics
1. DC Characteristics 1.1 Current consumption (READ) ICC1 vs. ambient temperature Ta
VCC = 5.5 V fSK = 2 MHz DATA = 0101 0.4 ICC1 (mA) 0.2
Rev.2.2_00
1.2 Current consumption (READ) ICC1 vs. ambient temperature Ta
VCC = 3.3 V fSK = 500 kHz DATA = 0101
0.4 ICC1 (mA) 0.2
0
−40
0 Ta (°C)
85
0
−40
0 Ta (°C)
85
1.3 Current consumption (READ) ICC1 vs. ambient temperature Ta
VCC = 1.8 V fSK = 10 kHz DATA = 0101 0.4 ICC1 (mA) 0.2
1.4 Current consumption (READ) ICC1 vs. power supply voltage VCC
Ta = 25°C fSK = 1 MHz, 500 kHz DATA = 0101
1 MHz
0.4 ICC1 (mA) 0.2
0
−40
0 Ta (°C)
85
0
2
3
∼
500 kHz
4
5
6
7
VCC (V)
1.5 Current consumption (READ) ICC1 vs. power supply voltage VCC
Ta = 25°C fSK = 100 kHz, 10 kHz DATA = 0101
1.6 Current consumption (READ) ICC1 vs. Clock frequency fSK
VCC = 5.0 V Ta = 25°C
0.4
0.4 ICC1 (mA) 0.2
100 kHz
ICC1 (mA)
0.2
10 kHz 0 2 3 4 56 7 VCC (V)
0
10 k
100 k
1 M 2M 10M
fSK (Hz)
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Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
1.7 Current consumption (WRITE) ICC2 vs. ambient temperature Ta
VCC = 5.5 V 1.0 ICC2 (mA) 0.5
1.8 Current consumption (WRITE) ICC2 vs. ambient temperature Ta
VCC = 3.3 V 1.0 ICC2 (mA) 0.5
0
−40
0 Ta (°C)
85
0
−40
0 85 Ta (°C)
1.9 Current consumption (WRITE) ICC2 vs. ambient temperature Ta
VCC = 2.7 V 1.0 ICC2 (mA) 0.5
1.10 Current consumption (WRITE) ICC2 vs. power supply voltage VCC
Ta = 25°C 1.0 ICC2 (mA) 0.5
0
−40
0 Ta (°C)
85
0
2
3
4
56
7
VCC (V)
1.11 Current consumption in standby mode ISB vs. ambient temperature Ta
VCC = 5.5 V CS = GND 1.0 ISB (µA) 0.5
1.12 Current consumption in standby mode ISB vs. power supply voltage VCC
Ta = 25°C CS = GND ISB (µA) 1.0
0.5
0
−40
0
0 85 Ta (°C)
2 3 4 56 VCC (V)
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
1.13 Input leakage current ILI vs. ambient temperature Ta
VCC = 5.5 V CS, SK, DI, TEST = 0 V 1.0 ILI (µA) 0.5
1.14 Input leakage current ILI vs. ambient temperature Ta
VCC = 5.5 V CS, SK, DI, TEST = 5.5 V 1.0 ILI (µA) 0.5
0
0
−40 0 Ta (°C) 85
−40
0 Ta (°C)
85
1.15 Output leakage current ILO vs. ambient temperature Ta
VCC = 5.5 V DO = 0 V 1.0 ILO (µA) 0.5
1.16 Output leakage current ILO vs. ambient temperature Ta
VCC = 5.5 V DO = 5.5 V 1.0 ILO (µA) 0.5
0
−40
0 Ta (°C)
85
0
−40
0 Ta (°C)
85
1.17 High-level output voltage VOH vs. ambient temperature Ta VCC = 4.5 V IOH = −400 µA 4.6
VOH (V) 4.4 4.2
1.18 High-level output voltage VOH vs. ambient temperature Ta
2.7 VOH (V) 2.6 2.5 VCC = 2.7 V IOH = −100 µA
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
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Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
1.19 High-level output voltage VOH vs. ambient temperature Ta
2.5 VOH (V) 2.4 2.3 VCC = 2.5 V IOH = −100 µA
1.20 High-level output voltage VOH vs. ambient temperature Ta
1.9 VOH (V) 1.8 1.7 VCC = 1.8 V IOH = −10 µA
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
1.21 Low-level output voltage VOL vs. ambient temperature Ta
0.3 VOL (V) 0.2 0.1 VCC = 4.5 V IOL = 2.1 mA
1.22 Low-level output voltage VOL vs. ambient temperature Ta
0.03 VOL 0.02 (V) 0.01 VCC = 1.8 V IOL = 100 µA
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
1.23 High-level output current IOH vs. ambient temperature Ta
VCC = 4.5 V VOH = 2.4 V −20.0 IOH (mA) −10.0
1.24 High-level output current IOH vs. ambient temperature Ta VCC = 2.7 V VOH = 2.4 V
IOH (mA) −2
−1
0
−40
0 Ta (°C)
85
0
−40
0 85 Ta (°C)
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LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
1.25 High-level output current IOH vs. ambient temperature Ta
VCC = 2.5 V VOH = 2.2 V
−2
1.26 High-level output current IOH vs. ambient temperature Ta
VCC = 1.8 V VOH = 1.6 V −1.0 IOH (mA)
IOH (mA)
−1
−0.5
0
0
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
1.27 Low-level output current IOL vs. ambient temperature Ta
VCC = 4.5 V VOL = 0.4 V 20 IOL (mA) 10
1.28 Low-level output current IOL vs. ambient temperature Ta VCC = 1.8 V VOL = 0.1 V
1.0 IOL (mA) 0.5
0
−40
0 85 Ta (°C)
0
−40
0 85 Ta (°C)
1.29 Input inverted voltage VINV vs. power supply voltage VCC
Ta = 25°C CS, SK, DI 3.0 VINV (V) 1.5
1.30 Input inverted voltage VINV vs. ambient temperature Ta
VCC = 5.0 V CS, SK, DI 3.0 VINV ( V) 2.0
0
1
2
3
45
67
0
−40
VCC (V)
0 Ta (°C)
85
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Seiko Instruments Inc.
Rev.2.2_00
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
1.31 Low supply voltage detection voltage −VDET vs. ambient temperature Ta
1.32 Low supply voltage release voltage +VDET vs. ambient temperature Ta
2.0 -VDET (V) 1.0 +VDET (V)
2.0
1.0
0
-40
0 Ta (°C)
85
0
-40
0 Ta (°C)
85
2. AC Characteristics 2.1 Maximum operating frequency fmax vs. power supply voltage VCC
Ta = 25°C 2M 1M 100k 10k 1 2 3 4 5
2.2 Write time tPR vs. power supply voltage VCC
Ta = 25°C 4 tPR (ms) 2
fmax. (Hz)
1
2
3
4
56
7
VCC (V)
VCC (V)
2.3 Write time tPR vs. ambient temperature Ta
VCC = 5.0 V tPR (ms) 6 4 2
2.4 Write time tPR vs. ambient temperature Ta
VCC = 3.0 V tPR (ms) 6 4 2
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
Seiko Instruments Inc.
21
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
Rev.2.2_00
2.5 Write time tPR vs. ambient temperature Ta
VCC = 2.7 V tPR (ms) 6 4 2
2.6 Data output delay time tPD vs. ambient temperature Ta
VCC = 4.5 V tPD (µs) 0.3 0.2 0.1
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
2.7 Data output delay time tPD vs. ambient temperature Ta
VCC = 2.7 V tPD (µs) 0.6 0.4 0.2
2.8 Data output delay time tPD vs. ambient temperature Ta
VCC = 1.8 V tPD (µs) 1.5 1.0 0.5
−40
0 Ta (°C)
85
−40
0 Ta (°C)
85
22
Seiko Instruments Inc.
Rev.2.2_00 Product Name Structure
S-93L76A D0I − xxxx G
LOW VOLTAGE OPERATION CMOS SERIAL E2PROM S-93L76A
IC direction in tape specification I8T1 : SNT-8A, Tape J8T1 : 8-Pin SOP(JEDEC), Tape T8T1 : 8-Pin TSSOP, Tape Fixed Product name S-93L76A : 8K-bit
Seiko Instruments Inc.
23
1 .97±0.03
8 7 6 5
1
0.5
2
3
4
0.08 -0.02
+0.05
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.0
TITLE No. SCALE UNIT
SNT-8A-A-PKG Dimensions PH008-A-P-SD-2.0
mm
Seiko Instruments Inc.
ø1.5 -0
+0.1
2.0±0.05
4.0±0.1
0.25±0.05
5°
2.25±0.05
ø0.5±0.1
4.0±0.1
0.65±0.05
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-1.0
TITLE No. SCALE UNIT
SNT-8A-A-Carrier Tape PH008-A-C-SD-1.0
mm
Seiko Instruments Inc.
12.5max.
Enlarged drawing in the central part ø13±0.2
9.0±0.3
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE No. SCALE UNIT mm
SNT-8A-A-Reel PH008-A-R-SD-1.0
QTY. 5,000
Seiko Instruments Inc.
0.52
2.01
0.52
0.3
0.2
0.3
0.2
0.3
0.2
0.3
Caution Making the wire pattern under the package is possible. However, note that the package may be upraised due to the thickness made by the silk screen printing and of a solder resist on the pattern because this package does not have the standoff.
No. PH008-A-L-SD-3.0
TITLE No. SCALE UNIT
SNT-8A-A-Land Recommendation
PH008-A-L-SD-3.0
mm
Seiko Instruments Inc.
5.02±0.2
8 5
1
4
0.20±0.05
1.27
0.4±0.05
No. FJ008-A-P-SD-2.1
TITLE No. SCALE UNIT
SOP8J-D-PKG Dimensions FJ008-A-P-SD-2.1
mm
Seiko Instruments Inc.
2.0±0.05 ø1.55±0.05
4.0±0.1(10 pitches:40.0±0.2) 0.3±0.05
ø2.0±0.05 5°max.
8.0±0.1
2.1±0.1
6.7±0.1
1
8
4
5
Feed direction
No. FJ008-D-C-SD-1.1
TITLE No. SCALE UNIT
SOP8J-D-Carrier Tape FJ008-D-C-SD-1.1
mm
Seiko Instruments Inc.
60°
2±0.5 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.2 13.5±0.5
No. FJ008-D-R-SD-1.1
TITLE No. SCALE UNIT
SOP8J-D-Reel FJ008-D-R-SD-1.1
QTY. mm 2,000
Seiko Instruments Inc.
3.00 -0.2
8 5
+0.3
1
4
0.17±0.05
0.2±0.1 0.65
No. FT008-A-P-SD-1.1
TITLE No. SCALE UNIT
TSSOP8-E-PKG Dimensions FT008-A-P-SD-1.1
mm
Seiko Instruments Inc.
4.0±0.1 2.0±0.05 ø1.55±0.05 0.3±0.05
8.0±0.1
ø1.55 -0.05
+0.1
(4.4)
6.6 -0.2
+0.4
1 4
8 5
Feed direction
No. FT008-E-C-SD-1.0
TITLE No. SCALE UNIT
TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0
mm
Seiko Instruments Inc.
13.4±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.5 17.5±1.0
No. FT008-E-R-SD-1.0
TITLE No. SCALE UNIT mm
TSSOP8-E-Reel FT008-E-R-SD-1.0
QTY. 3,000
Seiko Instruments Inc.
• • • • • •
The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.