4022-DKDB13

Si4022 Universal ISM Band FSK Transmitter Si4022 PIN ASSIGNMENT DESCRIPTION Silicon Labs’ Si4022 is a single chip, low power, multi-channel FSK transmitter designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the bands at 868 and 915 MHz. Used in conjunction with Integration’s FSK receivers, it is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated. Only an external crystal and bypass filtering is needed for operation. The transmitter has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. In addition, highly stable and accurate FSK modulation is accomplished by direct closed-loop modulation with bit rates up to 115.2 kbps. The integrated power amplifier of the transmitter has an open-collector differential output and can directly drive a loop antenna with programmable output level, no additional matching network is required. An automatic antenna tuning circuit is built in to avoid both costly trimming procedures and de-tuning due to the “hand effect”. For battery-operated applications the device supports various power saving modes with wake-up interrupt generation options based on a low battery voltage detector and a sleep timer. Several additional features ease system design. Power-on reset and clock signals are provided to the microcontroller. An on-chip baud rate generator and a data FIFO are available. The transmitter is programmed and controlled via an SPI compatible interface. FUNCTIONAL BLOCK DIAGRAM XTL 9 CRYSTAL OSCILLATOR REFERENCE   CLOCK VDD 15 VSS_A 11 VDD_B 14 VSS_D 8 VREFO 7 RF01 1 16 2 15 VDD nSEL 3 14 VSS_B SDO 4 13 RF02 nIRQ 5 12 RF01 FSK CLK 6 11 VSS_A VREFO 7 10 nRES VSS_D 8 9 XTL / REF This document refers to Si4022-IC Rev A0. See www.silabs.com/integration for any applicable errata. See back page for ordering information. FEATURES • • • • • • • • • • • • • • • • • • • • • Fully integrated (low BOM, easy design-in) No alignment required in production Fast settling, programmable, high-resolution PLL Fast frequency hopping capability Stable and accurate FSK modulation with programmable deviation Programmable PLL loop bandwidth Direct loop antenna drive Automatic antenna tuning circuit Programmable output power level SPI bus for interfacing with microcontroller Clock and reset signals for microcontroller 64 bit TX data FIFO Integrated programmable crystal load capacitor Standard 10 MHz crystal reference Power-saving modes Multiple event handling options for wake-up activation Wake-up timer Low battery detection 2.2 to 3.8 V supply voltage Low power consumption Low standby current (typ. 0.3 μA) LEVEL LOW BAT TRESHOLD 6 CLK 5 nIRQ 4 SDO 1 SDI 2 SCK CONTROLLER TIMEOUT WAKE -UP TIMER RF02 12 FREQUENCY LOAD CAP LOW BATTERY DETECT 13 SYNTHESIZER SDI SCK 3 nSEL 16 FSK PERIOD 10 nRES TYPICAL APPLICATIONS • • • • • • • • • Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy control Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading 1IA4 222-DS rev 1.1r 030     Si4i  022 DETAILED FEATURE-LEVEL DESCRIPTION The Si4022 FSK transmitter is designed to cover the unlicensed frequency bands at 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. PLL The low battery detector circuit monitors periodically (typ. 8 ms) the supply voltage and generates an interrupt if it falls below a programmable threshold level. The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The FSK deviation is selectable (from 20 to 160 kHz with 20 kHz increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is also highly accurate due to the direct closed-loop modulation of the PLL. The transmitted digital data can be sent asynchronously through the FSK pin or over the control interface using the appropriate command. Wake-Up Timer The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. To ensure proper operation in the programmed frequency band, the RF VCO is automatically calibrated upon activation of the synthesizer. In order to minimize current consumption, the transmitter supports the sleep mode. Switching between the various modes is controlled by the appropriate bits in the Power Management Command (page 11). RF Power Amplifier (PA) Si4022 generates an interrupt signal on several events (wakeup timer timeout, low supply voltage detection, on-chip FIFO almost empty). This signal can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The cause of the interrupt can be read out from the receiver by the microcontroller through the SDO pin. The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called “hand effect.” Crystal Oscillator and Microcontroller Clock Output The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transmitter can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. In normal operation it is divided from the reference 10 MHz. During sleep mode a low frequency (typical 32 kHz) output clock signal can be switched on. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Power Management Command, the chip provides a certain number (default is 128) of further clock pulses (“clock tail”) for the microcontroller to let it go to idle or sleep mode.   Low Battery Voltage Detector   The wake-up timer has very low current consumption (4 μA max) and can be programmed from 1 ms to several hours. It calibrates itself to the crystal oscillator at every startup and then at every 40 seconds with an accuracy of ±0.5%. When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. The periodic autocalibration feature can be turned off. Event Handling Interface and Controller An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the output power. Division ratio for the microcontroller clock, wakeup timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transmitter.   Si4022 PIN DEFINITION Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output SDI SCK 2 nSEL 3 SDO 4 nIRQ CLK VREFO VSS_D   1 5 6 7 8       IA4222         16 FSK 15 VDD 14 VSS_B 13 RF02 12 RF01 11 VSS_A 10 nRES 9 XTL / REF Pin Name Function Type 1 SDI SDI DI Serial control / data input 2 SCK SCK DI Serial interface clock input 3 nSEL nSEL DI Chip (interface) select input (active low) 4 SDO SDO DO Serial status data output 5 nIRQ nIRQ DO Interrupt request output (active low) 6 CLK CLK DO Clock output for the microcontroller 7 VREFO VREFO AO Voltage reference output 8 VSS_D VSS_D S 9 XTL / REF XTL AIO REF DI External reference input 10 nRES nRES DO Reset output (active low) 11 VSS_A VSS_A S 12 RFO1 RFO1 AO RF differential signal output (open collector) 13 RFO2 RFO2 AO RF differential signal output (open collector) 14 VSS_B VSS_B S Negative supply voltage (bulk) 15 VDD VDD S Positive supply voltage 16 FSK FSK DI Data input for asynchronous modulation   Description Negative supply voltage (digital) Crystal connection (other terminal of crystal to VSS) Negative supply voltage (analog)   Si4022 GENERAL DEVICE SPECIFICATION All voltages are referenced to V ss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Parameter Min Max Units Vdd Positive supply voltage -0.5 6.0 V Vin Voltage on any pin -0.5 Vdd+0.5 V Iin Input current into any pin except VDD and VSS -25 25 mA ESD Electrostatic discharge with human body model Tst Tld   1000 Storage temperature -55 Lead temperature (soldering, max 10 s)   V 125 o 260 o C C Recommended Operating Range Symbol Parameter Vdd Positive supply voltage Top Min Max 2.2 3.8 Ambient operating temperature -40 Units V o C +85 ELECTRICAL SPECIFICATION (Min/max values are valid over the whole recommended operating range, typ conditions: T op = 27 oC; V dd = Voc = 2.7 V) DC Characteristics Symbol Parameter Conditions/Notes Idd,TX0 Supply current 868 MHz band, Pout = 0dBm 915 MHz band, Pout = 0dBm   14 15   mA Idd,TXmax Supply current 868 MHz band, Pout = Pmax 915 MHz band, Pout = Pmax   23 24   mA Ipd Standby current (Note 1) all blocks disabled 1   µA Ilb Low battery voltage detector and wake-up timer current     Ix Idle current crystal oscillator is ON Vlb Low battery detection threshold programmable in 0.1 V steps Vlba Low battery detection accuracy VPOR Vdd threshold required to generate a POR VPOR,hyst POR hysteresis larger glithches on the Vdd generate a POR even above the threshold VPOR SRVdd Vdd slew rate for proper POR generation       Min Typ Max     5 0.5 2.0       1.5   0.6           µA mA 3.5 ± 0.05 0.1   Units V V V V V/ms Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period for sending 100 bytes packets in length at 19.2 kbps with +6 dBm output power in the 915 MHz band.       Si4022 DC Characteristics (continued) Symbol Parameter Conditions/Notes Vil Digital input low level Vih Digital input high level Iil Digital input current Vil = 0 V -1 Iih Digital input current Vih = Vdd, Vdd = 3.8 V -1 Vol Digital output low level Iol = 2 mA Voh Digital output high level Ioh = -2 mA     Min   0.7*Vdd   Vdd-0.4 Typ             Max Units 0.3*Vdd V   V 1 µA 1 µA 0.4 V   V AC Characteristics Symbol Parameter Conditions/Notes fLO Transmitter frequency 868 MHz band, 20 kHz resolution 915 MHz band, 20 kHz resolution fref PLL reference frequency (Note 1) fres PLL frequency resolution   Min 801.92 881.92   9 10     tlock PLL lock time Frequency error < 1kHz after 1 MHz step tsp PLL startup time Initial calibration after power-up with running crystal oscillator Cxl Crystal load capacitance, see crystal selection guide Programmable in 0.5 pF steps, tolerance +/- 10% tPOR Internal POR pulse width (Note 2) After Vdd has reached 90% of final value   tsx Crystal oscillator startup time Crystal ESR < 100    tPBt Wake-up timer clock period Calibrated every 40 seconds (Note 3) twake-up Programmable wake-up time   Typ 20 30   8.5 Units 878.06 958.06 MHz 11 MHz     kHz μs   500 μs   16 pF 50 100 ms 2 5 ms 1 1.005 ms 0.995 1 Max   6 8.4*10 ms Note 1: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency parameters will change accordingly. Note 2: No command are accepted by the chip during this period. Note 3: Autocalibration can be turned off.       Si4022 AC Characteristics (continued) Symbol Parameter Conditions/Notes BR FSK bit rate (Note 4) Iout Open collector output current Adjustable in 8 steps Pmax Available output power With optimal antenna impedance (Note 5) Pout Typical output power Adjustable in 8 steps (3 dB/step) Psp Spurious emission Out of band, EIRP (Note 6) Cout Output capacitance Set by the automatic antenna tuning circuit Qout Quality factor of the output capacitance Lout Output phase noise Cin, D Digital input capacitance tr, f Digital output rise/fall time 15 pF pure capacitive load tr, f ,ckout Clock output rise/fall time 10 pF pure capacitive load fckout, slow Slow clock frequency Tolerance +/- 1 kHz Min Typ       0.5       100 kHz from carrier 1 MHz from carrier (Note 4)   115.2 kbps 6 mA dBm   Pmax dBm   -52 dBm pF 1.6 2.2 2.8 16 18 22 -85 -105           Units   6 Pmax - 21 Max         32 dBc/Hz 2 pF 10 ns 15 ns   Setting (bw1, bw0) Max. datarate [kbps] Phase noise at 1 MHz offset [dBc/Hz] 00 19.2 -112 15 kHz 01 38.4 -110 30 kHz 10 64 -107 60 kHz (POR default) 11 115.2 -102 120 kHz Y antenna [S] Z antenna [Ω] L antenna [nH] Band   kHz PLL bandwidth 868 MHz 1.35E-3 – j1.2E-2 9 + j82 15.2 915 MHz 1.45E-3 – j1.3E-2 8.7 + j77 13.6 Note 4: The maximum FSK bitrate and the output phase noise are dependent on the PLL settings (with the Extended Features Command). Note 5: Optimal antenna / admittance / inductance for the Si4022 Note 6: With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration).       Si4022 TYPICAL PERFORMANCE DATA Phase noise measurements in the 868 MHz ISM band 100, 50, 33% Charge pump current settings (Ref. level: -70 dBc/Hz, 5 dB/div) 50% Charge pump current setting (Ref. level: -60 dBc/Hz, 10 dB/div) 11:52:47 May 5, 2005 Carrier Power -11.11 dBm Atten Ref -60.00dBc/Hz 10.00 1 dB/ Phase Noise L Mkr4 0.00 dB 13:30:49 May 5, 2005 Carrier Power -11.03 dBm Atten Ref -70.00dBc/Hz 5.00 dB/ 5.00800 MHz -115.65 dBc/Hz L Phase Noise Mkr1 1.1 dB 1.00000 MHz -101.95 dBc/Hz 2 4 1 2 10 kHz Frequency Offset Marker Trace Type 1 2 3 4 2 2 2 2 Spot Freq Spot Freq Spot Freq Spot Freq 10 kHz 10 MHz X Axis 10 kHz 151 kHz 1 MHz 5.008 MHz Value -76.65 dBc/Hz -86.95 dBc/Hz -107.11 dBc/Hz -115.65 dBc/Hz Frequency Offset Marker Trace Type 1 2 3 1 2 3 Spot Freq Spot Freq Spot Freq 10 MHz X Axis 1 MHz 1 MHz 1 MHz Value -101.95 dBc/Hz -107.05 dBc/Hz -109.98 dBc/Hz Unmodulated RF Spectrum The output spectrum is measured at different frequencies. The output is loaded with 50 Ohm through a matching network. At 915 MHz At 868 MHz L 10:26:50 May 5, 2005 Ref 0 dBm Samp Log 10 dB/ Ref 0 dBm Samp Log 10 dB/ 1 VAvg 100 W1 S2 S3 FC AA     VBW 10 kHz   Span 2 MHz Sweep 40.74 ms (2001 pts)   Center 915 MHz Res BW 10 kHz Mkr1 915.0020 MHz -14.09 dBm Atten 10 dB VAvg 100 W1 S2 S3 FC AA Center 868 MHz Res BW 10 kHz L 10:34:57 May 5, 2005 Mkr1 868.0010 MHz -12.2 dBm Atten 10 dB                       VBW 10 kHz                     Span 2 MHz Sweep 40.74 ms (2001 pts)   Si4022 At 868 MHz with 180 kHz Deviation at 9.6 kbps L 11:14:40 May 5, 2005 Ref 0 dBm Samp Log 10 dB/           VAvg 100   W1 S2   S3 FC AA       Atten 10 dB                     Center 868 MHz Res BW 10 kHz                     VBW 10 kHz Span 2 MHz Sweep 40.74 ms (2001 pts) Antenna Tuning Characteristics 750–970 MHz The antenna tuning characteristics was recorded in “max-hold” state of the spectrum analyzer. During the measurement, the transmitters were forced to change frequencies by forcing an external reference signal to the XTL pin. While the carrier was changing the antenna tuning circuit switched trough all the available states of the tuning circuit. The graph clearly demonstrates that while the complete output circuit had about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words the tuning circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread.       Si4022 CONTROL INTERFACE Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer multiple of 8 (except for the Transmitter FIFO Write Command). All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. Timing Specification Symbol Parameter Minimum value [ns] tCH Clock high time 25 tCL Clock low time 25 tSS Select setup time (nSEL falling edge to SCK rising edge) 10 tSH Select hold time (SCK falling edge to nSEL rising edge) 10 tSHI Select high time 25 tDS Data setup time (SDI transition to SCK rising edge) 5 tDH Data hold time (SCK rising edge to SDI transition) 5 tOD Data delay time 10 Timing Diagram tSS tSHI nSEL tCH tCL tOD tSH SCK tDS   tDH SDI BIT15 SDO BIT15   BIT14 BIT14 BIT13 BIT13 BIT8 BIT8 BIT7 BIT7 BIT1 BIT1 BIT0 BIT0   Si4022 Control Commands Control Word Related Parameters/Functions Configuration Setting Command frequency band and deviation, output power, crystal oscillator load capacitance Frequency Setting Command frequency of the local oscillator Power Managament Command crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer, clock output buffer Transmitter FIFO Write Command transmitter FIFO write FIFO Setting Command FIFO functions Data Rate Command bit rate Low Battery and Microcontroller Clock Divider Command LBD voltage threshold and microcontroller clock division ratio Wake-up Timer Command wake-up time period Extended Wake-up Timer Command wake-up time period finer adjustment Extended Features Command low frequency output clock, wake-up timer extra functions Status Register Read Command transmitter status read Note: In the following tables the POR column shows the default values of the command registers after power-on. Configuration Setting Command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 bs p2 p1 p0 x3 x2 x1 x0 ms m2 m1 m0   bs Frequency Band [MHz] 0 868 1 915 p2 p1 p0 0 0 0 Output Power [dBm] 0 0 0 1 -3 0 1 0 -6 0 1 1 -9 1 0 0 -12 1 0 1 -15 1 1 0 -18 1 1 1 -21 The output power is given in the table as relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note available from http://www.silabs.com/integration).     x3 x2 x1 x0 Crystal Load Capacitance [pF] 0 0 0 0 8.5 0 0 0 1 9.0 0 0 1 0 9.5 0 0 1 1 10.0 1 1 1 0 15.5 1 1 1 1 16.0 …… POR 9082h …. The resulting output frequency can be calculated as: fout = f0 – (-1)SIGN * (M + 1) * (20 kHz) where: f0 is the channel center frequency (see the next command) M is the three bit binary number SIGN = (ms) XOR (FSK input)   Si4022 Frequency Setting Command bit   15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR AD57h 0 dc POR C002h The constant C is determined by the selected band as: The 12-bit parameter of the Frequency Setting Command has the value F. The value F should be in the range of 96 and 3903. When F is out of range, the previous value is kept. The synthesizer center frequency f 0 can be calculated as: Band [MHz] f0 = 8 * 10 MHz * (C + F/4000) C 868 10 915 11 Power Management Command bit   15 1 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 ex 4 es 3 etr 2 eb 1 et Bit 5 : Enables the the crystal oscillator. Bit 4 : Enables the synthesizer. Bit 3 : Enables the power amplifier. If the ex and es bit is not set, it switches on the crystal oscillator and the synthesizer as well. In FIFO mode (bit fe is set in the FIFO Setting Command) setting this bit will roll out the content of the FIFO. Bit 2 : Enables the low battery detector. Bit 1 : Enables the wake-up timer. Bit 0 : Disables the clock output buffer. Note: If faster operation is needed, then leave ex and es bit set to ‘1’ and toggle only the etr bit. Power Saving Modes The different operating modes of the chip depend on the following control bits: Operating Mode eb or et es etr ex Active (transmit) X x 1 x Idle X 0 0 1 Sleep 1 0 0 0 Standby 0 0 0 0 Transmitter FIFO Write Command Bit   7 1 6 1 5 0 4 0 3 0 2 1 1 1 0 0 POR - With this command, the controller can write databits to the transmitter FIFO. Bit (fe) must be set in the FIFO Setting Command.       Si4022 Transmitter FIFO register write nSEL 0 1 2 3 4 5 6 7 0 1 2 3 4 5 N-2 N-1 SCK instruction filling up FIFO SDI N data bits Data Transmit Sequence Through the FSK Pin It is possible to transmit data without the FIFO by using the FSK input pin. In that case the power amplifier should be enabled first with the Power Management Comand. Power Management command nSEL C0h 38h SCK instruction SDI   Internal operations ex, es, etr = 1   xtal osc. stable Xtal osc staus   synthesizer / PLL / PA status don't care FSK tsx * tsp * synthesizer on, PLL locked, PA ready to transmit TX DATA NOTE: * See page 5 for the timing values Note: • If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs tsx time, to switch on. The actual value depends on the type of quartz crystal used. • If the synthesizer was formerly switched off (es=0), the internal PLL needs tsp startup time. Valid data can be transmitted only when the internal locking process is finished.       Si4022 FIFO Setting Command bit   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 1 1 1 0 fe 0 f5 f4 f3 f2 f1 f0 CE00h Bit 7 : Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO. Bit 5-0 : FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this leve Data Rate Command bit   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 1 0 0 0 cs r6 r5 r4 r3 r2 r1 r0 C813h The bit rate of the transmitted data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs. BR = 10 MHz / 29 / (R+1) / (1 + cs*7) In the receiver set R according the next function: R= (10 MHz / 29 /(1 + cs*7)/ BR) – 1 Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Low Battery and Microcontroller Clock Divider Command bit   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 0 0 1 0 d2 d1 d0 elfc t3 t2 t1 t0 C213h The 4-bit value T of t3-t0 determines the threshold voltage of the threshold voltage Vlb of the detector: Vlb = 2.0 V + T * 0.1 V Bit 4 : Enables low frequency (32 kHz) microcontroller output clock during sleep mode. Clock divider configuration (valid only if the crystal oscillator is on): d2 d1 d0 0 0 0 Clock Output Frequency [MHz] 1 0 0 1 1.25 0 1 0 1.66 0 1 1 2 1 0 0 2.5 1 0 1 3.33 1 1 0 5 1 1 1 10 Wake-Up Timer Command bit   15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 The wake-up time period can be calculated by M , R and D : T wake-up = M * 2R-D ms     POR E196h   Si4022 N o t e :• The wake-up timer generates interrupts continuously at the programmed interval while the et bit is set. Extended Wake-Up Timer Command bit   15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 1 7 d1 6 d0 5 m13 4 m12 3 m11 2 m10 1 m9 0 m8 POR C300h These bits can be used for further fine adjustment of the wake-up timer. The explanation of the bits can be found above.     Extended Features Command: bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 exlp ctls 0 dcal bw1 bw0 dsfi ewi   POR B0CAh Bit 7 : Enables low power mode for the crystal oscillator. Bit 6 : Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128. Bit 4 : Disables the wake-up timer autocalibration. Bit 3-2 : Select the bandwidth of the PLL. bw1 bw0 PLL bandwidth 0 0 15 kHz 0 1 30 kHz 1 0 60 kHz 1 1 120 kHz Bit 1 : Disables autosleep on FIFO interrupt if set to 1. Bit 0 : Enables the automatic wake-up on any interrupt event. Status Register Read Command bit   15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 With this command, it is possible to read the status register of the chip through the SDO pin. FFIT The number of data bits in the FIFO has gone below the preprogrammed limit FFEM FIFO is empty FFOV FIFO overflow LBD Low battery detect, the power supply voltage is below the preprogrammed limit WK-UP POR   Wake-up timer overflow Power-on reset   0 0 POR -   Si4022 Status Register Read Sequence nSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 SCK SDI status out SDO   FFIT   FFEM FFOV LBD WK-UP POR 13 14 15   Si4022 Dual Clock Output When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz clock signal is available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the Low Battery and Microcontroller Clock Divider Command (page13). During startup and in sleep or standby mode (crystal oscillator disabled), the CLK output is pulled to logic low. On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the Low Battery and Microcontroller Clock Divider Command. The clock frequency is 32 kHz which is derived from the low-power RC oscillator of the wake-up timer. In order to use this slow clock the wake-up timer should be enabled by setting the et bit in the Power Management Command (page 11) even if the wakeup timer itself is not used. Slow clock feature can be enabled by entering into sleep mode (page 11). Driving the output will increase the sleep mode supply current. Actual worst-case value can be determined when the exact load and min/max operating conditions are defined. After poweron reset the chip goes into sleep mode and the slow frequency clock appears on the CLK pin. Switching back into fast clock mode can be done by setting the ex or etr bits in the approriate commands. It is important to leave bit dc in the Power Management Command at its default state (0) otherwise there will be no clock signal on the CLK pin. Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at least a half cycle of the fast clock. During switching the clock can be logic low once for an intermediate period i.e. for any time between the half cycle of the fast and the slow clock. Tslow clock periods are not to scale slow clock fast clock output 0.5 * Tfast < Tx < 0.5 * Tslow Tx Tfast The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of 0 to T slow + Tfast from the occurrence of a clock change request (entering into sleep mode or interrupt) until the beginning of the intermediate length (T ) half cycle. The x other is that both clocks should be up and running for the change to occur. Changing from fast to slow clock, it is automatically ensured by entering into the sleep mode in the appropriate way provided that the wake-up timer is continouosly enabled. As the crystal oscillator is normally stopped while the slow clock is used, when changing back to fast clock the crystal oscillator startup time has to pass first before the above mentioned latency period starts. The startup condition is detected internally, so no software timing is necessary. Wake-Up Timer Calibration By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Power Management Command. After timeout the timer can be stopped by resetting this bit otherwise it operates continuously. If the timer is programmed to run for longer periods, at approximately every 40 seconds it performs additional self-calibration. This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software algorithm can then compensate for the gradual shift caused by temperature change. Bit dcal in the Extended Features Command (page 14) controls the automatic calibration feature. It is reset to 0 at power-on and the automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit to 1.       Si4022 MATCHING NETWORK FOR A 50 OHM SINGLE ENDED OUTPUT Matching Network Schematic VDD L3 to RFP C1 , C2 [pF] 3.9 L1 [nH] 6.8 L3 [nH] 100 C1 50 Ohm load L1 GND to RFN C2 GND RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).       Si4022 CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4022 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. It is recommended to keep the PCB parasitic capacitances on the XTL pin as low as possible. The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency (f ). cTherefore f c is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable carrier frequency error. Maximum XTAL Tolerances Including Temperature and Aging [ppm] Bit Rate: Bit Rate: Bit Rate: Bit Rate: 2.4 kbps   Transmitter Deviation [+/- kH z] 20 40 60 80 100 120 140 160 868 2 12 25 30 40 50 70 80 915 2 12 20 30 40 50 60 70 9.6 kbps   Transmitter Deviation [+/- kH z] 20 40 60 80 100 120 140 160 868 do not use 8 20 30 40 50 60 70 915 do not use 8 15 30 40 50 60 70 38.4  kbps Transmitter Deviation [+/- kH z] 20 40 60 80 100 120 140 160 868 do not use do not use 10 20 30 40 50 70 915 do not use do not use 10 20 30 40 50 60 115.2   kbps Transmitter Deviation [+/- kHz] 20 40 60 80 100 120 140 160 868 do not use do not use do not use do not use do not use 2 12 25 915 do not use do not use do not use do not use do not use 2 12 20 Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C . 0 Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or channel separations.       Si4022 EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION Data packet structure An example data packet structure using theSi4022 –Si4022 pair for data transmission. This packet structure is an example of how to use the high efficiency FIFO mode at the receiver side: AA AA AA 2D D4 D 0 D 1 D 2 Preamble ... DN Databytes (received in the FIFO of the receiver) Synchron pattern The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes compose a 16 bit synchron pattern which is essential for the receiver’s FIFO to find the byte synchron in the received bit stream. The synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D 0 in the picture above) will be the first received byte in the FIFO. Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side will be unable to track. Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual.       Si4022 PACKAGE INFORMATION 16-pin TSSOP       Si4022 ORDERING INFORMATION Si4022 Universal ISM Band FSK Transmitter DESCRIPTION ORDERING NUMBER Si4022 16-pin TSSOP Si4022-IC CC16 die see Silicon Labs Rev A0 Demo Boards and Development Kits DESCRIPTION ORDERING NUMBER ISM Chipset Development Kit IA ISM – DK3 Related Resources DESCRIPTION ORDERING NUMBER Antenna Selection Guide IA ISM – AN1 Antenna Development Guide IA ISM – AN2 IA4322 Universal ISM Band FSK Receiver see http://www.silabs.com/integration for details Note: Volume orders must include chip revision to be accepted.           Smart. Connected. Energy-Friendly. Products Quality www.silabs.com/products www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. 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