4455CPCE10D915M-K

Si4455 E ASY - TO - U SE , L O W - C URRENT OOK/(G)FSK S UB -GH Z T RANSCEIVER Features   Pin Assignments Applications Remote control Home security and alarm  Telemetry  Garage and gate openers Remote keyless entry Home automation  Industrial control  Sensor networks  Health monitors     Description Silicon Laboratories’ Si4455 is an easy-to-use, low current, sub-GHz EZRadio® transceiver. Covering all major bands, it combines plug-and-play simplicity with the flexibility needed to handle a wide variety of applications. The compact 3x3 mm package size combined with a low external BOM count makes the Si4455 both space efficient and cost effective. The +13 dBm output power and excellent sensitivity of –116 dBm allows for a longer operating range, while the low current consumption of 18 mA TX (at 10 dBm), 10 mA RX, and 50 nA standby, provides for superior battery life. By fully integrating all components from the antenna to the GPIO or SPI interface to the MCU, the Si4455 makes realizing this performance in an application easy. Design simplicity is further exemplified in the Wireless Development Suite (WDS) user interface module. This configuration module provides simplified programming options for a broad range of applications in an easy to use format that results in both a faster and lower risk development. The Si4455 is capable of supporting major worldwide regulatory standards such as FCC, ETSI, ARIB and China regulatory standards. Rev 1.1 10/13 Copyright © 2013 by Silicon Laboratories XOUT Low standby current = 50 nA  20 19 18 17 16 nSEL GND 1 SDN 2 RXp 3 RXn 4 13 SCLK TX 5 12 nIRQ GND 6 15 SDI 14 SDO Si4455 7 8 9 10 GPIO0  mA RX mA TX @ +10 dBm  XIN 18  GND 10  GPIO2 Max output power = +13 dBm  Low active power consumption   Max data rate = 500 kbps Power supply = 1.8 to 3.6 V TX and RX 64 byte FIFOs Automatic frequency control (AFC) Automatic gain control (AGC) Integrated battery voltage sensor Packet handling including preamble, sync word detection, and CRC Low BOM 20-Pin 3x3 mm QFN package VDD OOK  GPIO3 (G)FSK  VDD Frequency range = 283–960 MHz  Receive sensitivity = –116 dBm  Modulation  11 GPIO1 Patents pending Si4455 Si4455 Functional Block Diagram GPIO3 GPIO2 XIN XOUT Synthesizer SDN 25-32MHz XO Rx Chain RXn LNA PGA ADC Rx/Tx Modem SPI Interface Controller RXp nSEL SDI SDO SCLK nIRQ TX Battery Voltage Sensor PA VDD 2 Aux ADC GPIO1 GPIO0 Rev 1.1 Si4455 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. Typical Applications Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1. Receiver Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2. Receiver Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.4. Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.6. Battery Voltage and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Configuration Options and User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1. Radio Configuration Application (RCA) GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 11.1. Si4455 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev 1.1 3 Si4455 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature Supply Voltage I/O Drive Voltage Test Condition Min Typ Max Unit TA –40 25 85 °C VDD 1.8 3.6 V VGPIO 1.8 3.6 V Table 2. DC Characteristics* Parameter Symbol Supply Voltage Range VDD Power Saving Modes TUNE Mode Current Test Condition Min Typ Max Unit 1.8 3.3 3.6 V IShutdown RC oscillator, main digital regulator, and low power digital regulator OFF. — 30 — nA IStandby Register values maintained. — 50 — nA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. — 2 — mA ISPI Active SPI active state ITune_RX RX Tune — 6.5 — mA ITune_TX TX Tune — 6.9 — mA — 10 — mA +10 dBm output power, 868 MHz — 18 — mA +13 dBm output power, 868 MHz — 30 — mA RX Mode Current IRX TX Mode Current ITX 1.35 mA *Note: All specifications are guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in section "1.1. Definition of Test Conditions" on page 11. 4 Rev 1.1 Si4455 Table 3. Synthesizer AC Electrical Characteristics1 Parameter Synthesizer Frequency Range Synthesizer Frequency Resolution2 Symbol Test Condition FSYN Min Typ Max Unit 283 — 350 MHz 425 — 525 MHz 850 — 960 MHz FRES-960 850–960 MHz — 114.4 — Hz FRES-525 425–525 MHz — 57.2 — Hz FRES-350 283–350 MHz — 38.1 — Hz Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in section "1.1. Definition of Test Conditions" on page 11. 2. Guaranteed by qualification. Qualification test conditions are listed in section "1.1. Definition of Test Conditions" on page 11. Rev 1.1 5 Si4455 Table 4. Receiver AC Electrical Characteristics1 Parameter Symbol RX Frequency Range FRX RX Sensitivity 350 MHz 425 — 525 MHz 850 — 960 MHz PRX-_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, F = 25 kHz, 114 kHz Rx BW)2 — –108 — dBm PRX-_128 (BER < 0.1%) (128 kbps, GFSK, BT = 0.5, F = 70 kHz, 305 kHz Rx BW)2 — –103 — dBm PRX-_OOK (BER < 0.1%, 1 kbps, 185 kHz Rx BW, OOK, PN15 data)2 — –113 — dBm (BER < 0.1%, 40 kbps, 185 kHz Rx BW, OOK, PN15 data)2 — –102 — dBm 40 — 850 kHz — 0 0.1 ppm — ±0.5 — dB Desired Ref Signal 3 dB above sensitivity, BER < 0.1%. Interferer is CW and desired modulated with 1.2 kbps, F = 5.2 kHz, GFSK with BT= 0.5, RX BW = 58 kHz channel spacing = 100 kHz — –56 — dB — –59 — dB 200KBLOCK Desired Ref Signal 3 dB above sensitivity, BER < 0.1%. Interferer is CW and 1MBLOCK desired modulated with 1.2 kbps F = 5.2 kHz GFSK with BT = 0.5, 8MBLOCK RX BW = 58 kHz — –58 — dB — –61 — dB — –79 — dB RESRSSI C/I1-CH 2 C/I2-CH Spurious Emissions3 — dBm Selectivity2 Image Rejection2 283 — RSSI Resolution Blocking 8 MHz Offset2 Unit –116 PRX_RES Blocking 1 MHz Offset2 Max — BER Variation vs Power Level2 Blocking 200 kHz–1 MHz Typ (BER < 0.1%) (2.4 kbps, GFSK, BT = 0.5, F = 30 kHz, 114 kHz Rx BW)2 BW 2-Ch Offset Selectivity Min PRX-_2 RX Channel Bandwidth2 1-Ch Offset Test Condition Up to +5 dBm Input Level ImREJ Rejection at the image frequency IF = 468 kHz — –35 — dB POB_RX1 Measured at RX pins — –54 — dBm Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in section "1.1. Definition of Test Conditions" on page 11. 2. Guaranteed by qualification. Qualification test conditions are listed in section "1.1. Definition of Test Conditions" on page 11. 3. Emissions specifications are based on frequency, matching components, and board layout. 6 Rev 1.1 Si4455 Table 5. Transmitter AC Electrical Characteristics1 Parameter Symbol TX Frequency Range Test Condition FTX Min Typ Max Unit 283 — 350 MHz 425 — 525 MHz 850 — 960 MHz (G)FSK Data Rate2 DRFSK 1.0 — 500 kbps OOK Data Rate2 DROOK 0.5 — 120 kbps Modulation Deviation Range Modulation Deviation Resolution2 Output Power Range 3 TX RF Output Steps2 f960 850–960 MHz — — 500 kHz f525 425–525 MHz — — 500 kHz f350 283–350 MHz — — 500 kHz FRES-960 850–1050 MHz — 114.4 — Hz FRES-525 425–525 MHz — 57.2 — Hz FRES-350 283–350 MHz — 38.1 — Hz –40 — +13 dBm PTX PRF_OUT Using switched current match within 6 dB of max power — 0.1 — dB TX RF Output Level2 Variation vs. Temperature PRF_TEMP –40 to +85 C — 1 — dB TX RF Output Level Variation vs. Frequency2 PRF_FREQ Measured across 902–928 MHz — 0.5 — dB B*T Gaussian Filtering Bandwith Time Product — 0.5 — POB-TX1 POUT = +13 dBm, Frequencies < 1 GHz — –54 — dBm POB-TX2 1–12.75 GHz, excluding harmonics — –42 — dBm P2HARM Using reference design TX matching network and filter with max output power. Harmonics reduce linearly with output power. — –42 — dBm — –42 — dBm Transmit Modulation Filtering2 Spurious Emissions3 Harmonics3 P3HARM Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11. 2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 11. 3. Output power and emissions specifications are dependent on transmit frequency, matching components, and board layout. Rev 1.1 7 Si4455 Table 6. Auxiliary Block Specifications1 Parameter XTAL Range2 30 MHz XTAL Start-Up time 30 MHz XTAL Cap Resolution3 POR Reset Time Symbol Test Condition Min Typ Max Unit 25 — 32 MHz — 250 — µs 30MRES — 70 — fF tPOR — — 5 ms XTALRANGE t30M Using XTAL and board layout in reference design. Start-up time will vary with XTAL type and board layout. Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11. 2. XTAL Range tested in production using an external clock source (similar to using a TCXO). 3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 11. 8 Rev 1.1 Si4455 Table 7. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ)1 Parameter Symbol Test Condition Min Typ Max Unit Rise Time TRISE 0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV = LL VDD = 3.3 V — 2.3 — ns Fall Time TFALL 0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV = LL VDD = 3.3 V — 2 — ns Input Capacitance CIN — 2 — pF Logic High Level Input Voltage VIH VDD x 0.7 — — V Logic Low Level Input Voltage VIL — — VDD x 0.3 V Input Current IIN 0 < VIN < VDD –10 — 10 µA Input Current if Pullup is Activated IINP VIL = 0 V 1 — 10 µA IOmaxLL DRV[1:0] = LL — 6.66 — mA IOmaxLH DRV[1:0] = LH — 5.03 — mA IOmaxHL DRV[1:0] = HL — 3.16 — mA IOmaxHH DRV[1:0] = HH — 1.13 — mA IOmaxLL DRV[1:0] = LL — 5.75 — mA IOmaxLH DRV[1:0] = LH — 4.37 — mA IOmaxHL DRV[1:0] = HL — 2.73 — mA IOmaxHH DRV[1:0] = HH — 0.96 — mA IOmaxLL DRV[1:0] = LL — 2.53 — mA IOmaxLH DRV[1:0] = LH — 2.21 — mA IOmaxHL DRV[1:0] = HL — 1.7 — mA IOmaxHH DRV[1:0] = HH — 0.80 — mA Logic High Level Output Voltage VOH DRV[1:0] = HL VDD x 0.8 — — V Logic Low Level Output Voltage VOL DRV[1:0] = HL — — VDD x 0.2 V Drive Strength for Output Low Level2 Drive Strength for Output High Level (GPIO1, GPIO2, GPIO3)2 Drive Strength for Output High Level (GPIO0)2 Notes: 1. All specifications guaranteed by qualification. Qualification test conditions are listed under “Qualification Test Conditions” in "1.1. Definition of Test Conditions" on page 11. 2. GPIO output current measured at 3.3 VDC VDD with VOH = 2.64 VDC and VOL = 0.66 VDC. Rev 1.1 9 Si4455 Table 8. Thermal Characteristics Parameter Symbol Test Condition Max Value Unit Thermal Resistance Junction to Ambient φJA Still Air 30 °C/W Junction Temperature TJ 92 °C Table 9. Absolute Maximum Ratings Parameter Value Unit –0.3, +3.6 V Voltage on Digital Control Inputs –0.3, VDD + 0.3 V Voltage on Analog Inputs –0.3, VDD + 0.3 V +10 dBm Operating Ambient Temperature Range TA –40 to +85 C Storage Temperature Range TSTG –55 to +125 C VDD to GND RX Input Power Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device. 10 Rev 1.1 Si4455 1.1. Definition of Test Conditions Production Test Conditions: TA = +25 °C VDD = +3.3 VDC Sensitivity measured at 434 MHz using a PN15 modulated input signal and with packet handler mode enabled. External reference signal (XIN) = 1.0 VPP at 30 MHz, centered around 0.8 VDC RF input and output levels can typically be achieved at the antenna port after filtering components. Qualification Test Conditions: TA = –40 to +85 °C (typical = 25 °C) VDD = +1.8 to +3.6 VDC (typical = 3.3 VDC) Use RF TX/RX Split Antenna reference design or production test schematic input and output levels can typically be achieved at the antenna port after filtering components. Rev 1.1 11 Si4455 C4 L1 C7 C8 C9 100 p 100 n 1u Figure 1. Si4455 Application Circuit Rev 1.1 GP2 SDO GP3 SCLK GP4 nIRQ 12 11 GPIO1 VDD 12 SDI GP5 Microcontroller nSEL 16 17 XIN 18 GPIO2 19 XOUT 13 10 6 TX 5 C1 C3 Si4455 4 GND C5 3 14 GPIO0 L2 15 2 9 RXn GP1 GND L3 L4 RXp C2 GP0 8 L5 30 MHz VDD SDN L6 1 7 GND VDD C6 20 GPIO3 2. Typical Applications Schematic Si4455 3. Functional Description GPIO3 GPIO2 XIN XOUT Synthesizer SDN 25-32MHz XO Rx Chain RXn LNA PGA ADC Rx/Tx Modem SPI Interface Controller RXp nSEL SDI SDO SCLK nIRQ TX Battery Voltage Sensor PA Aux ADC VDD GPIO1 GPIO0 Figure 2. Si4455 Functional Block Diagram The Si4455 is an easy-to-use, size efficient, low current wireless ISM transceiver that covers the sub-GHz bands. The wide operating voltage range of 1.8–3.6 V and low current consumption make the Si4455 an ideal solution for battery powered applications. The Si4455 operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the FSK/GFSK or OOK/ASK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA), the signal is converted to the digital domain by a high performance  ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in digital modem, increasing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte Rx FIFO. A single high-precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO signal is generated by an integrated VCO and  Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates up to 500 kbps. The Si4455 operates in the frequency bands of 283–350, 425–525, and 850–960 MHz. The transmit FSK data is modulated directly into the  data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The Si4455 contains a power amplifier (PA) that supports output powers up to +13 dBm and is designed to support single coin cell operation with current consumption of 18 mA for +10 dBm output power. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. Additional system features, such as 64-byte TX/RX FIFOs, preamble detection, sync word detector, and CRC, reduce overall current consumption and allow for the use of lower-cost system MCUs. Power-on-reset (POR) and GPIOs further reduce overall system cost and size. The Si4455 is designed to work with an MCU, crystal, and a few passives to create a very compact and low-cost system. Rev 1.1 13 Si4455 3.1. Receiver Chain The internal low-noise amplifier (LNA) is designed to be a wideband LNA that can be matched with three external discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low noise to suppress the noise of the following stages and achieve optimal sensitivity; therefore, no external gain or front-end modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC) algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and PGA for use in the AGC algorithm. The RX and TX pins can be directly tied externally. 3.2. Receiver Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem performs the following functions: Channel selection filter Preamble detection Invalid preamble detection TX modulation RX demodulation Automatic Gain Control (AGC) Automatic frequency compensation (AFC) Radio signal strength indicator (RSSI) Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 850 kHz down to 40 kHz. A large variety of data rates are supported ranging from 0.5 kbps up to 500 kbps. The configurable preamble detector is used with the synchronous demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only sync detection, which is a valuable feature of the asynchronous demodulator when very short preambles are used. The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. A wireless communication channel can be corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller, allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK, considerably reducing the energy in adjacent channels. The default bandwidth-time (BT) product is 0.5 for all programmed data rates. 3.2.1. Received Signal Strength Indicator The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the desired or undesired in-band signal power. The Si4455 uses a fast response register to read RSSI and so can complete the read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value reported by this API command can be converted to dBm using the following equation: 14 Rev 1.1 Si4455 RSSI_value RSSI dBm = --------------------------------- – 130 2 The value of 130 in the above formula is based on bench characterization of the EZRadio RF Pico boards (evaluation boards). The RSSI value is latched at sync word detection and can be read via the fast response register. The latched value of RSSI is available until the device re-enters Rx mode. In addition, the current value of RSSI can be read out using the GET_MODEM_STATUS command. This can be used to implement CCA (clear channel assessment) functionality. The user can set up an RSSI threshold value using the WDS Radio Configuration Application GUI. 3.3. Synthesizer The Si4455 includes an integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from 283–350, 425–525, and 850–960 MHz. The synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider, which results in very precise accuracy and control over the transmit deviation. The frequency resolution is (2/3)Freq_xo/(219) for 283–350 MHz, Freq_xo/(219) for 425–525 MHz, and Freq_xo/(218) for 850–960 MHz. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used. The modem configuration calculator in WDS will automatically account for the XTAL frequency being used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed by a configurable divider, which will divide the signal down to the desired output frequency band. 3.3.1. Synthesizer Frequency Control The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will automatically provide these settings, but the synthesizer equation is shown below for convenience. Initial frequency settings are configured in the EZConfig setup and can also be modified using the API commands: FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and FREQ_CONTROL_FRAC0. fc_frac 4  freq_xo -  -------------------------------  Hz  RF frequency =  fc_inte + ----------------19   outdiv 2 Note: The fc_frac/219 value in the above formula must be a number between 1 and 2. The LSB of fc_frac must be "1". Table 10. Output Divider (Outdiv) Values Outdiv 12 8 4 Lower (MHz) 284 425 850 Upper (MHz) 350 525 960 3.3.1.1. EZ Frequency Programming EZ frequency programming allows for easily changing radio frequency using a single API command. The base frequency is first set using the EZConfig setup. This base frequency will correspond to channel 0. Next, a channel step size is also programmed within the EZConfig setup. The resulting frequency will be: RF Frequency = Base Frequency + Channel  Step Size The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to 900 MHz, and a CHANNEL number of 5 is programmed during the START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0 and so will be set to the base frequency if this argument is never used. Rev 1.1 15 Si4455 3.4. Transmitter The Si4455 contains a +13 dBm power amplifier that is capable of transmitting from –40 to +13 dBm. The output power set size is dependent on the power level and can be seen in Figure 3. The PA power level is set using the API command: PA_PWR_LVL. The power amplifier is single-ended to allow for easy antenna matching and low BOM cost. For detailed matching values, BOM, and performance expectations, refer to "AN686: Antennas for the Si4455/4355 RF ICs". Power ramp-up and ramp-down is automatically performed to reduce unwanted spectral spreading. Figure 3. Tx Power vs PA_PWR_LVL and VDD 16 Rev 1.1 Si4455 3.5. Crystal Oscillator The Si4455 includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is designed to handle any XTAL from 25 to 32 MHz, set in the EZConfig setup. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in Figure 4. Figure 4. Capacitor Bank Frequency Offset Characteristics An external signal source can easily be used in lieu of a conventional XTAL and should be connected to the XIN pin. The incoming clock signal is recommended to be ac-coupled to the XIN pin since the dc bias is controlled by the internal crystal oscillator buffering circuitry. The input swing range should be between 600 mV–1.8 V peak-to-peak. If external drive is desired, the incoming signal amplitude should not go below 0 V or exceed 1.8 V. The best dc bias should be approximately 0.7 V. However, if the signal swing exceeds 1.4 Vpp, the dc bias can be set to 1/2 the peak-to-peak voltage swing. The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the POWER_UP command should be invoked with the TCXO option whenever external drive is used. 3.6. Battery Voltage and Auxiliary ADC The Si4455 contains an integrated auxiliary 11-bit ADC used for the internal battery voltage detector or an external component via GPIO. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first sending the GET_ADC_READING command and enabling the desired inputs. When the conversion is finished and all the data is ready, CTS will go high, and the data can be read out. For details on this command and the formulas needed to interpret the results, refer to the EZRadio API documentation zip file available from www.silabs.com. Rev 1.1 17 Si4455 4. Configuration Options and User Interface 4.1. Radio Configuration Application (RCA) GUI The Radio Configuration Application (RCA) GUI is part of the Wireless Development Suite (WDS) program. This setup interface provides an easy path to quickly selecting and loading the desired configuration for the device. The RCA allows for two different methods for device setup. One option is the configuration table, which provides a list of preloaded, common configurations. A second option allows for custom configurations to be loaded. After the desired configuration is selected, the RCA automatically creates the EZConfig configuration array that will be passed to the chip for setup. The program then gives the option to load a sample project with the selected configuration onto the evaluation board or launch IDE with the new configuration array preloaded into the user program. For more information on EZConfig usage, refer to application note, “AN692: Si4355/Si4455 Programming Guide”. Figure 5. Device Configuration Options 18 Rev 1.1 Si4455 4.1.1. Configuration Table The configuration table is a list of predefined configurations that have been optimized for performance and validated by Silicon Labs. These configurations are listed for many common application conditions and so most users will be able to find the configuration they need in this table. These configurations are set to provide optimized performance for a given application and can be implemented with low design risk. Once the list item is selected, the specific frequency, power level, and packet handler features can also be applied. 4.1.2. Radio Configuration Application The Radio Configuration Application provides an intuitive interface for directly modifying the device configuration. Using this control panel, the device parameters such as modulation type, data rate, frequency deviation, and any packet related settings can be set. The program then takes these parameters and automatically determines the appropriate device settings. This method allows the user to have complete flexibility in determining the configuration of the device without the need to translate the system requirements into device specific properties. The resulting configuration array is automatically generated and available for use in the user's program. The resulting configuration array is obfuscated; therefore, its content changes every time a new array is generated, even if the input parameters are the same. 4.2. Configuration Options 4.2.1. Frequency Band The Si4455 can operate in the 283–350 MHz, 425–525 MHz, or 850–960 MHz bands. One of these three bands will be selected during the configuration setup and then the specific transmission frequency that will be used within this band can be selected. 4.2.2. Modulation Type The Si4455 can operate using On/Off Keying (OOK), Frequency Shift Keying (FSK), or Gaussian Frequency Shift Keying (GFSK). OOK modulation is the most basic modulation type available. It is the most power-efficient method and does not require as high oscillator accuracy as FSK. FSK provides the best sensitivity and range performance, but generally requires more precision from the oscillator used. GFSK is a version of FSK where the signal is passed through a Gaussian filter, limiting its spectral width. As a result, the out-of-band components of the signal are reduced. The Si4455 also has an option for Manchester coding. This method provides a state transition at each bit and so allows for more reliable clock recovery. Manchester code is available only when using the packet handler option and, if selected, will be applied to the entire packet (the preamble pattern is set to continuous “1” if the Manchester mode is enabled; therefore, the chip rate of the resulting preamble pattern is the same as for the rest of the packet). The polarity can be configured to a “10” or “01”. C lock D ata 1 0 1 0 0 1 1 1 M anchester Figure 6. Manchester Code Example Rev 1.1 19 Si4455 4.2.3. Frequency Deviation If FSK or GFSK modulation is selected, then a frequency deviation will also need to be selected. The frequency deviation is the maximum instantaneous difference between the FM modulated frequency and the nominal carrier frequency. The Si4455 can operate across a wide range of data rates and frequency deviations. If a frequency deviation needs to be selected, the following guideline might be helpful to build a robust link. A proper frequency deviation is linked to the frequency error between transmitter and receiver. The frequency error can be calculated using the crystal tolerance parameters and the RF operating frequency: (ppm_tx+ppm_rx)*Frf/1E-6. For frequency errors below 50 kHz, the deviation can be about the same as the frequency error. For frequency errors exceeding 50 kHz, the frequency deviation can be set to about 0.75 times the frequency error. It is advised to position the modulation index (= 2*freq_dev/data_rate) into a range between 1 and 100 for Packet Handling mode and 2 to 100 for direct mode (non-standard preamble). For example, when in Packet Handling mode and the frequency error is smaller than data_rate/2, the frequency deviation is set to about data_rate/2. When the frequency error exceeds 100xdata_rate/2, the frequency deviation is preferred to be set to 100xdata_rate/2. 4.2.4. Data Rate The Si4455 can be set to communicate at between 1 to 500 kbps in (G)FSK mode and between 0.5 to 120 kbps in OOK mode. Higher data rates allow for faster data transfer while lower data rates result in improved sensitivity and range performance. 4.2.5. Channel Bandwidth The channel bandwidth sets the bandwidth for the receiver. Since the receiver bandwidth is directly proportional to the noise allowed in the system, this will normally be set as low as possible. The specific channel bandwidth used will usually be determined based upon the precision of the oscillator and the frequency deviation of the transmitted signal. The RCA can provide the recommended channel bandwidth based upon these two parameters to help optimize the system. 4.2.6. Preamble Length A preamble is a defined simple bit sequence used to notify the receiver that a data transmission is imminent. The length of this preamble will normally be set as short as possible to minimize power while insuring that it will be reliably detected given the receiver characteristics, such as duty cycling and packet error rate performance. The Si4455 allows the preamble length to be set between 0 to 255 bytes in length with a default length of 4 bytes. The preamble pattern for the Si4455 will always be 55h with a first bit of "0" if the packet handler capability is used. 4.2.7. Sync Word Length and Pattern The sync word follows the preamble in the packet structure and is used to identify the start of the payload data and to synchronize the receiver to the transmitted bit stream. The Si4455 allows for sync word lengths of 1 to 4 bytes and the specific pattern can be set within the RCA program. The default is a 2 byte length 2d d4 pattern. 4.2.8. Cyclic Redundancy Check Cyclic Redundancy Check (CRC) is used to verify that no errors have occurred during transmission and the received packet has exactly the same data as it did when transmitted. If this function is enabled in the Si4455, the last byte of transmitted data must include the CRC generated by the transmitter. The Si4455 then performs a CRC calculation on the received packet and compares that to the transmitted CRC. If these two values are the same, the Si4455 will set an interrupt indicating a valid packet has been received and is waiting in the Rx FIFO. If these two CRC values differ, the Si4455 will flag an interrupt indicating that a packet error occurred. The Si4455 uses CRC(16)-IBM: x16+x15+x2+1 with a seed of 0xFFFF. 20 Rev 1.1 Si4455 4.3. Configuration Commands The RCA provides all of the code needed for basic radio configuration. Once the setup is completed in the GUI, the program outputs configuration array(s) that can be sent to the radio via the SPI interface. No additional setup coding is needed. The configuration command process is shown in Figure 7. As shown below, the configuration is sent to the device in two EZCONFIG_ARRAY_WRITE commands with a NOP between them. The second EZCONFIG_ARRAY_WRITE can be sent after CTS is received for the NOP command. The NOP can be sent immediately after the first EZCONFIG_ARRAY_WRITE command. EZCONFIG_ARRAY_WRITE uses the same command code as WRITE_TX_FIFO (0x66). The EZCONFIG_SETUP passes the configuration array to the device and the EZCONFIG_CHECK insures that all of the configuration data was written correctly. For more information on the setup commands, refer to “AN692: Si4355/Si4455 Programming Guide” and the EZRadio API Documentation zip file available from www.silabs.com. EZ C O N FIG _A R R A Y_W R IT E NOP EZ C O N FIG _A R R A Y_W R IT E E Z C O N F IG _C H E C K Figure 7. Configuration Command Flowchart Rev 1.1 21 Si4455 5. Controller Interface 5.1. Serial Peripheral Interface The Si4455 communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI, SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters are listed in Table 11. The host MCU writes data over the SDI pin and can read data from the device on the SDO output pin. Figure 8 shows an SPI write command. The nSEL pin should go low to initiate the SPI command. The first byte of SDI data will be one of the API commands followed by n bytes of parameter data which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the center of the SDI data. Table 11. Serial Interface Timing Parameters Symbol Parameter Min (ns) tCH Clock high time 40 tCL Clock low time 40 tDS Data setup time 20 tDH Data hold time 20 tDD Output data delay time 20 tEN Output enable time 20 tDE Output disable time 50 tSS Select setup time 20 tSH Select hold time 50 tSW Select high period 80 Diagram SCLK tSS tCL tCH tDS tDH tDD tSH tDE SDI SDN SDO tEN tSW nSEL nSEL SDO SDI API Command ParamByte 0 SCLK Figure 8. SPI Write Command 22 Rev 1.1 ParamByte n Si4455 The Si4455 contains an internal MCU which controls all the internal functions of the radio. For SPI read commands, a typical communication flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the command and prepared the data to be output over the SDO pin. Figure 9 demonstrates the general flow of an SPI read command. Once the CTS value reads FFh, then the read data is ready to be clocked out to the host MCU. The typical time for a valid FFh CTS reading is 20 µs. Figure 10 demonstrates the remaining read cycle after CTS is set to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the SDO data on the rising edge of SCLK. Send Command Read CTS CTS Value 0xFF Retrieve Response 0x00 nSEL CTS SDO SDI ReadCmdBuff SCLK Figure 9. SPI Read Command—Check CTS Value nSEL SDO Response Byte 0 Response Byte n SDI SCLK Figure 10. SPI Read Command—Clock Out Read Data Rev 1.1 23 Si4455 5.2. Operating Modes and Timing The primary states of the Si4455 are shown in Figure 11. The shutdown state completely shuts down the radio, minimizing current consumption and is controlled using the SDN (pin 2). All other states are controlled using the API commands START_RX, START_TX and CHANGE_STATE. Table 12 shows each of the operating modes with the time required to reach either RX or TX state as well as the current consumption of each state. The times in Table 12 are measured from the rising edge of nSEL until the chip is in the desired state. This information is included for reference only since an automatic sequencer moves the chip from one state to another and so it is not necessary to manually step through each state. Figure 12 and Figure 13 demonstrate this timing and the current consumption for each radio state as the chip moves from shutdown or standby to TX and back. Most applications will utilize the standby mode since this provides the fastest transition response time, maintains all register values, and results in nearly the same current consumption as shutdown. Standby Shutdown SPI Active Config Ready Tx Tune Rx Tune Tx Rx Figure 11. State Machine Diagram 24 Rev 1.1 Si4455 Table 12. Operating State Response Time and Current Consumption State / Mode Response Time to Current in State / Mode Tx Rx Shutdown 30 ms 30 ms 30 nA Standby 500 μs 460 μs 50 nA SPI Active 500 μs 330 μs 1.35 mA Ready 150 μs 130 μs 1.8 mA Tx Tune 75 μs 6.9 mA Rx Tune 75 μs 6.5 mA Tx 150 μs 18 mA @ +10 dBm 150 μs 10 mA Rx 150 μs TX = 19 mA Tune = 100 us@6.9 mA POR = 1 ms@1.25 mA Ready = 300 us@1.8 mA Standby = 10 us@50 nA Reg Inrush = 5 us@2 mA POWER_UP / CONFIG_SETUP = 29 ms@2 mA Shutdown = 30 nA Shutdown = 30 nA Figure 12. Start-Up Timing and Current Consumption using Shutdown State Rev 1.1 25 Si4455 TX = 19 mA Tune = 100us@6.9 mA Ready = 300 us@1.8 mA Reg Inrush = 5 us@2 mA Standby = 50 nA Standby = 50 nA Figure 13. Start-Up Timing and Current Consumption using Standby State 5.2.1. Shutdown State The shutdown state is the lowest current consumption state of the device and is entered by driving SDN (Pin 2) high. In this state, all register contents are lost and there is no SPI access. To exit this mode, drive SDN low. The device will then initiate a power on reset (POR) along with internal calibrations. Once this POR period is complete, the POWER_UP command is required to initialize the radio and the configuration can then be loaded into the device. The SDN pin must be held high for at least 10 µs before driving it low again to insure the POR can be executed correctly. The shutdown state can be used to fully reset the part. If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the host processor rather than tying it to GND on the board. 5.2.2. Standby State The standby state has similar current consumption to the shutdown state but retains all register values, allowing for a much faster response time. Because of these benefits, most applications will want to use standby mode rather than shutdown. The standby state is entered by using the CHANGE_STATE API command. While in this state, the SPI is accessible but any SPI event will automatically transition the chip to the SPI active state. After the SPI event, the host will need to re-command the device to standby mode. 5.2.3. SPI Active State The SPI active state enables the device to process any SPI events, such as API commands. In this state, the SPI and boot up oscillator are enabled. The SPI active state is entered by using the CHANGE_STATE command or automatically through an SPI event while in standby mode. If the SPI active state was entered automatically from standby mode, a CHANGE_STATE command will be needed to return the device to standby mode. 5.2.4. Ready State Ready state is designed to give a fast transition time to TX or RX state with minimized current consumption. In this mode the crystal oscillator remains enabled to minimize the transition time. Ready state can be entered using the CHANGE_STATE command. 26 Rev 1.1 Si4455 5.2.5. Power on Reset A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this process, VDD must ramp within 1 ms and must remain applied to the device for at least 10 ms. If VDD is removed, then it must stay below 0.15 V for at least 10 ms before being applied again. Refer to Figure 14 and Table 13 for details. Figure 14. POR Timing Diagram Table 13. POR Timing Variable Description Min Typ Max Units tPORH High time for VDD to fully settle POR circuit. 10 ms tPORL Low time for VDD to enable POR. 10 ms VRRH Voltage for successful POR. 90%*Vdd V VRRL Starting Voltage for successful POR. tSR 0 Slew rate of VDD for successful POR. Rev 1.1 150 mV 1 ms 27 Si4455 5.2.6. TX State The TX state is used whenever the device is required to transmit data. It is entered using either the START_TX or CHANGE_STATE command. With the START_TX command, the next state can be defined to insure optimal timing. When either command is sent to enter TX state, an internal sequencer automatically takes care of all actions required to move between states with no additional user commands needed. Examples of the timing of this transition can be seen in Figure 12 and Figure 13. The specific sequencer controlled events that take place during this time can include enable internal LDOs, start up crystal oscillator, enable PLL, calibrate VCO/PLL, active power amplifier, and transmit packet. Figure 15 shows an example of the commands and timing for the START_TX command. CTS will go high as soon as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS will be low and no new commands or property changes are allowed. If the nIRQ is used to monitor the current state, there will be a slight delay caused by the internal hardware from when the event actually occurs to when the transition occurs on the nIRQ. The time from entering TX state to when the nIRQ will transition is 13 µs. If a GPIO is programmed for TX state or used as control for a transmit/receive switch (TR switch), there is no delay. CTS nSEL SDI START_TX Current State FRR Initial State TX State Initial State TXCOMPLETE_STATE TX State TXCOMPLETE_STATE nIRQ GPIO-TX State Figure 15. START_TX Commands and Timing 5.2.7. RX State The RX state is used whenever the device is required to receive data. It is entered using either the START_RX or CHANGE_STATE commands. With the START_RX command, the next state can be defined to insure optimal timing. When either command is sent to enter RX state, an internal sequencer automatically takes care of all actions required to move between states with no additional user commands needed. The sequencer controlled events can include enable the digital and analog LDOs, start up the crystal oscillator, enable PLL, calibrate VCO, enable receiver circuits, and enable receive mode. The device will also automatically set up all receiver features such as packet handling based upon the initial configuration of the device. 28 Rev 1.1 Si4455 5.3. Interrupts The Si4455 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change in status is detected. The interrupt sources are grouped into three categories: packet handler, chip status, and modem. The individual interrupts in these groups can be enabled/disabled in the interrupt property registers, 0x0101, 0x0102, and 0x0103. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as the individual interrupts in API property 0x0100. When an interrupt event occurs and the nIRQ pin is low, the interrupts are read and cleared using the GET_INT_STATUS command. By default all interrupts will be cleared once read. The instantaneous status of a specific function may be read if the specific interrupt is enabled or disabled. The status results are provided after the interrupts and can be read with the same commands as the interrupts. The status bits will give the current state of the function whether the interrupt is enabled or not. The following is a list of possible interrupts: Chip status status Packet handler status Packet sent Packet received CRC error Invalid preamble detected Invalid sync detected Preamble detected Sync detected State change Command error Chip ready TX FIFO almost empty RX FIFO almost full RSSI interrupt Modem Rev 1.1 29 Si4455 5.4. GPIO Four General Purpose IO (GPIO) pins are available for use in the application. The GPIOs are configured using the GPIO_PIN_CFG command. GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more susceptibility to generating spurious components in the synthesizer than pins 0 and 1. The drive strength of the GPIO's can be adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default, the drive strength is set to the minimum. The default configuration and the state of the GPIO during shutdown are shown in Table 14. For a complete list of the GPIO options, please refer to the EZRadio API documentation zip file available from www.silabs.com. Table 14. GPIOs 30 Pin SDN State POR Default GPIO0 0 POR GPIO1 0 CTS GPIO2 0 POR GPIO3 0 POR nIRQ Resistive VDD pull-up nIRQ SDO Resistive VDD pull-up SDO SDI High Z SDI SCLK High Z SCLK NSEL High Z NSEL Rev 1.1 Si4455 6. Data Handling and Packet Handler 6.1. RX and TX FIFOs Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX. Writing to command register 66h loads data into the TX FIFO and reading from command register 77h reads data from the RX FIFO. For packet lengths greater than 64 bytes, RX_FIFO_ALMOST_FULL and TX_FIFO_ALMOST_EMPTY status bits and interrupts can be used to manage the FIFO. The threshold value for these can be configured via the WDS radio configuration application GUI. The maximum payload length supported in packet handler mode is 255 bytes. 6.2. Packet Handler The Si4455 includes integrated packet handler features such as preamble and sync word detection as well as CRC calculation. This allows the chip to qualify and synchronize with legitimate transmissions independent of the microcontroller. These features can be enabled using the RCA. In this setup, the preamble and sync word length can be modified and the sync word pattern can be selected. If the preamble is greater than or equal to 4 bytes, the device uses the preamble detection circuit with a 2-byte detection threshold. If the preamble is less than 32 bits, then at least two bytes of sync word are required plus at least one byte of 0101 pattern (3 bytes total). In this case, preamble detection is skipped, and only sync word detection is used. For any combination of preamble and sync word less than three bytes, the device will use direct mode. The general packet structure is shown in Figure 16. The EZConfig setup also provides the option to select a variable packet length. With this setting, the receiver is not required to know the packet length ahead of time. The transmitter sends the length of the packet immediately after the sync word. The packet structure for variable length packets is shown in Figure 17. Preamble 0 – 255 Bytes Sync Word 1 – 4 Bytes Data 1 – 255 Bytes CRC 2 Bytes Figure 16. Packet Structure for Fixed Packet Length Preamble 0 – 255 Bytes Sync Word 1 – 4 Bytes Length 1 Byte Data 1 – 255 Bytes CRC 2 Bytes Figure 17. Packet Structure for Variable Packet Length 6.3. Direct Mode In direct mode, the packet handler (including FIFO) is bypassed, and the host MCU must feed the data stream to the device in TX mode and read out the data stream in RX mode via GPIOs. The host MCU will process the data and perform packet handler functions. This is commonly used to support legacy implementations where host MCU software exists or to support non-standard packet structures. Some examples are packets with non 1010 preamble pattern, no preamble or sync word, or sync word with no edge transitions. WDS provides example projects to support both packet handler and direct modes. Rev 1.1 31 Si4455 Pin 1 Pin Name GND I/O GND 2 SDN I 3 4 5 6 7 8 9 10 11 RXp RXn TX GND VDD VDD GND GPIO0 GPIO1 I I O GND VDD VDD GND I/O I/O 12 nIRQ O 13 SCLK I 14 SDO O 15 SDI I 16 nSEL I 17 XOUT O 18 XIN I 19 20 GPIO2 GPIO3 I/O I/O 32 GPIO3 GPIO2 XIN XOUT 7. Pin Descriptions 20 19 18 17 16 nSEL 15 SDI 14 SDO 4 13 SCLK TX 5 12 nIRQ GND 6 11 GPIO1 RXp 3 RXn Si4455 7 8 9 10 GPIO0 2 GND SDN VDD 1 VDD GND Description Ground Shutdown (0 – VDD V) – SDN=1, part will be in shutdown mode and contents of all registers are lost. SDN=0, all other modes Differential RF receiver input pin Differential RF receiver input pin Transmit RF output pin Ground Supply voltage Supply voltage Ground General Purpose Digital I/O General Purpose Digital I/O Interrupt Status Output – nIRQ = 0, interrupt event has occurred. Read interrupt status for event details Serial Clock Input (0 – VDD V): Provides serial data clock for 4-line serial data bus Serial Data Output (0 – VDD V): Provides serial data readback function of internal control registers Serial Data Input (0 – VDD V): Serial data stream input for 4-line serial data bus Serial Interface Select Input (0 – VDD V): Provides select/enable function for 4-line serial data bus Crystal Oscillator Output Crystal Oscillator Input: No dc bias required, but if used, should be set to 0.7 V. Also used for external TCXO input. General Purpose Digital I/O General Purpose Digital I/O Rev 1.1 Si4455 Pin Pin Name PKG PADDLE_GND I/O GND Description The exposed metal paddle on the bottom of the package supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the underlying PCB. Rev 1.1 33 Si4455 8. Ordering Information Part Number* Description Package Type Operating Temperature Si4455-B1A-FM EZRadio Transceiver 3x3 QFN-20 Pb-free –40 to 85 °C *Note: Add an “R” at the end of the device part number to denote tape and reel option. 34 Rev 1.1 Si4455 9. Package Outline Figure 18. 20-pin QFN Package Rev 1.1 35 Si4455 Table 15. Package Diagram Dimensions Dimension A A1 A3 b c D D2 e E E2 f L aaa bbb ccc ddd eee fff Min 0.80 0.00 0.18 0.25 1.55 1.55 0.30 Nom 0.85 0.02 0.20 REF 0.25 0.30 3.00 BSC. 1.70 0.50 BSC. 3.00 BSC. 1.70 2.40 BSC. 0.40 0.15 0.10 0.10 0.05 0.08 0.10 Max 0.90 0.05 0.30 0.35 1.85 1.85 0.50 Note: All dimensions shown are in millimeters (mm) unless otherwise noted. 36 Rev 1.1 Si4455 10. PCB Land Pattern Figure 19. 20-pin QFN PCB Land Pattern Table 16. PCB Land Pattern Dimensions Dimension C1 C2 E X1 X2 Y1 Y2 Y3 f c MIN MAX 3.00 3.00 0.50 REF 0.25 1.65 0.85 1.65 0.37 0.35 1.75 0.95 1.75 0.47 2.40 REF 0.25 0.35 Note: All dimensions shown are in millimeters (mm) unless otherwise noted. Rev 1.1 37 Si4455 11. Top Marking 11.1. Si4455 Top Marking Figure 20. Si4455 Top Marking 11.2. Top Marking Explanation Mark Method: Laser Line 1 Marking: Part Number 455A = Si4455-B1A Firmware Revision A = B1A Line 2 Marking: TTTT = Trace Code Internal tracking number Line 3 Marking: Circle = 0.5 mm Diameter (Bottom-Left Justified) Y = Year WW = Workweek 38 Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev 1.1 Si4455 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1                Removed API section and updated references to EZRadio API documentation in various sections to reflect the latest revision. Changed references to EZConfig Setup to Radio Configuration Application (RCA) in various sections. Updated " Functional Block Diagram" on page 2. Removed Vdd connection to PA Updated Table 3, “Synthesizer AC Electrical Characteristics1,” on page 5. Removed Synthesizer settling time (covered in state transition timing in Table 12). Updated Table 4, “Receiver AC Electrical Characteristics1,” on page 6. Changed Image Rejection and Spurious emissions spec Added footnote to highlight that emissions are layout-dependent and not only an IC specification. Updated Table 5, “Transmitter AC Electrical Characteristics1,” on page 7. Changed Emissions and Harmonics from Max to Typical specs. Added footnote to highlight that emissions are layout dependent and not only an IC specification. Updated Table 7 on page 9. Changed Rise and Fall time test conditions. Updated Drive Strength levels. Updated Table 8 on page 10. Updated Junction Temperature spec. Updated "1.1. Definition of Test Conditions" on page 11. Added comments Updated "3.2.1. Received Signal Strength Indicator" on page 14. Updated RSSI description. Updated Figure 5 on page 18. Updated Figure 7 on page 21. Updated Table 11 on page 22. Changed SDN to SDI. Updated "5.3. Interrupts" on page 29. Added Interrupt options. Section "5.4. GPIO" on page 30. Updated Updated "7. Pin Descriptions" on page 32. Updated XIN pin description and added ground paddle description.  Updated Figure 19 on page 37 to show top view of the package.  Table 14 to include SCLK and NSEL. Updated "6. Data Handling and Packet Handler" on page 31.  Added "6.3. Direct Mode" on page 31.  Rev 1.1 39 Simplicity Studio One-click access to MCU tools, documentation, software, source code libraries & more. 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